Commit Graph

22432 Commits

Author SHA1 Message Date
Yanfeng Liu
634ee5b1f6 board/maix-bit: add cmake support
This adds initial CMake support for `maix-bit` device.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-24 11:08:25 +08:00
Ville Juven
29f8648ecc arm64: Initial implementation of CONFIG_BUILD_KERNEL
This is the initial version for kernel mode build on the arm64 platform.
It works much in the same way as the risc-v implementation so any
highlights can be read from there.

Features that have been tested working:
- Creating address environments
- Loading init (nsh) from elf file
- Booting to nsh
- Starting other processes from nsh
- ostest runs to completion

Features that are not tested / do not work:
- SHM / shared memory support
- Kernel memory mapping (MM_KMAP)
- fork/vfork

An example qemu target is provided as a separate patch:
tools/configure.sh qemu-armv8a:knsh
2024-08-23 10:26:34 -03:00
Ville Juven
7f228b1554 arm64/barriers.h: Generalize barrier macros
Make it possible to define arguments for barriers
2024-08-23 10:26:34 -03:00
Ville Juven
52781221b3 arm64_sync_exc: Use temporaries x9/x10 instead of x0/x1
Why? Because this allows optimizing the user system call path in such
a way that the parameter registers don't have to be read from the saved
integer register context when the system call is executed.
2024-08-23 10:26:34 -03:00
wangchen
f0cdaca660 nuttx-names.in:add popen & pclose assign to glibc interface
Signed-off-by: wangchen <wangchen41@xiaomi.com>
2024-08-23 20:20:25 +08:00
chao an
a0afd38f24 arm/spinlock: up_testset() sould not depends on SMP
up_testset() sould not depends on SMP

Signed-off-by: chao an <anchao@lixiang.com>
2024-08-23 20:20:06 +08:00
Xu Xingliang
cfdbc856ff sim/lcd: fix compile break
Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
2024-08-23 15:26:16 +08:00
jianglianfang
a5afa11238 sim: Support to use of non-consecutive framebuffers
Some hardware devices use discontinuous framebuffers, which require SIM support for simulating discontinuous framebuffers.

Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
2024-08-23 15:26:16 +08:00
Yanfeng Liu
74080e8659 arm/qemu: use WFI to avoid busy loop
This adds WFI based up_idle() for arm/qemu to fix busy loop.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-23 15:09:44 +08:00
Matheus Catarino
93b520f7b0 swift6 embedded support 2024-08-23 09:02:20 +08:00
yinshengkai
53ddc3ef7f arch/sim: suppress libasan checks
There is a false positive in asan of gcc-13, we need to mask it to ensure that other parts work properly

sanitizer_common/sanitizer_common_interceptors.inc:
   // FIXME: under ASan the call below may write to freed memory and corrupt
   // its metadata. See
   // https://github.com/google/sanitizers/issues/321.

==572161==ERROR: AddressSanitizer: dynamic-stack-buffer-overflow on address 0xed3d3f00 at pc 0xef46af64 bp 0xed3d3de8 sp 0xed3d39bc
WRITE of size 128 at 0xed3d3f00 thread T0
     #0 0xef46af63 in __interceptor_pthread_sigmask ../../../../../src/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc:4419
     #1 0x5486aa7d in up_irq_save sim/posix/sim_hostirq.c:97

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-08-23 08:53:52 +08:00
yinshengkai
0111cb73f1 sim: update sim_asan dependencies
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-08-23 08:53:52 +08:00
jinxiuxu
b874d95beb drivers/audio: fix samp rate conversion issue
Signed-off-by: jinxiuxu <jinxiuxu@xiaomi.com>
2024-08-22 09:13:51 -03:00
jinxiuxu
618a51fa84 audio: add 12K support in sim_alsa driver
Signed-off-by: jinxiuxu <jinxiuxu@xiaomi.com>
2024-08-22 09:13:51 -03:00
jianglianfang
f5fe7646ed sim: read the second buffer
It can only read the contents of the first buffer, so fblen should be changed to ensure that it can read the second buffer as well.

Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
2024-08-22 16:17:43 +08:00
Yanfeng Liu
01219b415c board/qemu-armv7a: add Cmake support
This adds Cmake support for `qemu-armv7a` device.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-22 15:25:02 +08:00
fangxinyong
9b3fe17743 arch/arm/arm_mpu.c: fix build warning
armv7-m/arm_mpu.c: In function 'mpu_dump_region':
armv7-m/arm_mpu.c:621:13: warning: format '%X' expects argument of type 'unsigned int', but argument 4 has type 'long unsigned int' [-Wformat=]
  621 |       _info("MPU-%d, alignedbase=0%08X l2size=%"PRIu32" SRD=%X"
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
armv7-m/arm_mpu.c:621:13: warning: format '%X' expects argument of type 'unsigned int', but argument 6 has type 'long unsigned int' [-Wformat=]
  621 |       _info("MPU-%d, alignedbase=0%08X l2size=%"PRIu32" SRD=%X"
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
armv7-m/arm_mpu.c:621:13: warning: format '%X' expects argument of type 'unsigned int', but argument 7 has type 'long unsigned int' [-Wformat=]
  621 |       _info("MPU-%d, alignedbase=0%08X l2size=%"PRIu32" SRD=%X"
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
armv7-m/arm_mpu.c:621:13: warning: format '%u' expects argument of type 'unsigned int', but argument 8 has type 'long unsigned int' [-Wformat=]
  621 |       _info("MPU-%d, alignedbase=0%08X l2size=%"PRIu32" SRD=%X"

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
2024-08-22 01:58:46 +08:00
chenrun1
3a6a23d157 xtensa_mpu:Modify the specified Region attributes
Due to the xtensa mpu feature, the size of the Region depends on the Base of the next Region. e.g.
Region[1] = 0x20000000
Region[0] = 0x30000000
Then Region[1] length = Region[0] - Region[1]
So this approach is not suitable to implement the behavior of cleaning
up the Region and such a configuration will result in affecting the very beginning (the higher) Region
Therefore, to address this feature, in this change we return the Region
value and implement the ability to modify the target Region's attributes

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-22 01:58:46 +08:00
chenrun1
054c564a2d arm_mpu:Fix mpu_initialize not taking effect
Modified the input parameters of mpu_initialize to require the caller to provide the number of entries in the table

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-22 01:58:46 +08:00
chenrun1
62f598e547 arm_mpu:Reentrant allocation Region
Changes have been completed:
1.armv7m
2.armv8m
3.armv7r
4.arm64

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-22 01:58:46 +08:00
chenrun1
8e1a042eef nuttx/atomic.h:Fix missing type declarations at compile time
Summary:
  1.Modify the conditions for entering different include header files
  2.Added pre-definition for _Atomic _Bool when it is missing
  3.Added nuttx for stdatomic implementation. When toolchain does not support atomic, use lib/stdatomic to implement it

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-22 01:44:29 +08:00
chenrun1
667e92390b nuttx/atomic.h:replace ALL stdatomic.h with nuttx/stdatomic.h in nuttx/
Summary:
  1. Add nuttx/atomic.h in include
  2. Use nuttx/atomic.h instead of stdatomic.h in the nuttx directory

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-22 01:44:29 +08:00
liqinhui
91d849b70e simwifi: Resolve the error of getting the network ID.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2024-08-21 23:36:26 +08:00
liqinhui
6d3fdd4f15 simwifi: Suppress the scanning times to avoid the popen crash.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2024-08-21 23:36:26 +08:00
liqinhui
577e2fa73f simwifi: Avoid to set the mode of wlan repeatedly.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2024-08-21 23:36:26 +08:00
liqinhui
01b39074a2 simwifi: Support the ioctl of SIOCGIWENCODEEXT and SIOCGIWSENS.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2024-08-21 23:36:26 +08:00
shizhenghui
8d1f4e9697 sim_camera: rename video to camera
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-08-21 23:29:47 +08:00
shizhenghui
6ff3ed83fc m2m sim codec: add wqueue.h to fix build warning
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-08-21 23:29:47 +08:00
Tiago Medicci Serrano
568917bfd2 espressif: Fix MCUboot build on RISC-V and unify linker script
This commit fixes building MCUboot on Espressif's RISC-V SoCs and
unify the associated linker scripts to make improve readability.
2024-08-21 23:28:45 +08:00
Tiago Medicci Serrano
5680e9d5a4 espressif: Update internal libraries reference
Update internal reference to get the most updated Espressif's
libraries. Those libraries are based on branch `release/v5.1` of
the ESP-IDF and include `v5.1.4` version of it.
2024-08-21 23:28:45 +08:00
jinxiuxu
45d41af6db nuttx/audio: add offload buffer size config
Signed-off-by: jinxiuxu <jinxiuxu@xiaomi.com>
2024-08-21 17:59:28 +08:00
jinxiuxu
31fe15b6e0 audio:fix crash when driver_audio capture
sim/posix/sim_alsa.c:728:24: runtime error: member
access within null pointer of type 'const struct sim_codec_ops_s'

Signed-off-by: jinxiuxu <jinxiuxu@xiaomi.com>
2024-08-21 17:59:28 +08:00
qiaohaijiao1
d7088fe376 sim/alsa: use default bps as 16 in offload mode.
Signed-off-by: qiaohaijiao1 <qiaohaijiao1@xiaomi.com>
2024-08-21 17:59:28 +08:00
chenrun1
bb4d710d62 xtensa_cache:Disable clean/flush optimization in case of SMP restriction
In a multicore task scenario, there may be a situation where the task runs on different cores at different time slices (when the task is not bound to a particular core).
When the task calls cache clean/flush(range > cache size), depending on the optimization, clean_all, flush_all are called. however, at this point, there may be dirty data or incomplete data profiles in the cache on the kernel that is running the task, which may result in dirty data being flushed into memory or make the application think that the flushed data should be successfully flushed into memory, leading to unknown consequences.

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-21 03:04:41 +08:00
chenrun1
91cf97ed84 arm_cache:Disable clean/flush optimization in case of SMP restriction
In a multicore task scenario, there may be a situation where the task runs on different cores at different time slices (when the task is not bound to a particular core).
When the task calls cache clean/flush(range > cache size), depending on the optimization, clean_all, flush_all are called. however, at this point, there may be dirty data or incomplete data profiles in the cache on the kernel that is running the task, which may result in dirty data being flushed into memory or make the application think that the flushed data should be successfully flushed into memory, leading to unknown consequences.

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-21 03:04:41 +08:00
wangming9
0c12fb9237 arm/armv8-r: Fix cache interface
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2024-08-21 03:04:41 +08:00
wangming9
0bfd4c5e0d arm/armv8-r: Adding a cache interface to armv8-r
Summary:
1. Add up_get_icache_size、up_get_dcache_size
2. Added L2 cahce PL310 implementation

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2024-08-21 03:04:41 +08:00
fangxinyong
13cb355a4e arm/armv[7|8]-m: add syn barrier for MPU ops
Execute data and instruction sync barriers after writing MPU register,
to ensure MPU setting take effects that the new changes are seen.

testing in lm3s6965-ek:qemu-protected

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
2024-08-21 02:57:25 +08:00
jianglianfang
1e29b8de1d driver/fb:remove overlay from fb_notify_vsync
Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
2024-08-21 02:57:08 +08:00
jianglianfang
8122cbd5d2 drivers/video: add fb_vsync_pollnotify
when the vsync comes, fb drivers should call fb_vsync_pollnotify to notify POLLPRI, so that users can catch the synchronization time of vsync and do something.

Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
2024-08-21 02:57:08 +08:00
guoshichao
24ce8dfbf2 armv7-a/irq: add up_irq_disable method implementation
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
(cherry picked from commit 7059b05e501d67c342f1753e8eb96e723b99d6b8)
2024-08-21 02:53:04 +08:00
guoshichao
0aa7e39eef nuttx/arch/irq: add up_irq_disable method implementation
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-21 02:53:04 +08:00
liqinhui
4c69ef988f simwifi: Add the netlink event of connect/disconnect.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2024-08-21 02:08:10 +08:00
zhanghongyu
4e79741e7d usbdev: add ncm driver
The compilation and verification commands are shown below:
./tools/configure.sh sim:usbdev
make -j
sudo ./nuttx
nsh> conn 2
nsh> dhcpd_start eth1

Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2024-08-21 02:01:01 +08:00
hujun5
4cb419866f arch: inline up_testset in arm arm64 riscv xtensa
test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-08-21 01:45:10 +08:00
cuiziwei
7b43a9413a arch/EXTRA_LIBS: link all staging library.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-08-21 01:40:15 +08:00
guoshichao
07c370817c armv7a/irq: enable fiq in tee, enable irq in ap
According to the current design on the armv7-a platform,
only fiq is processed in TEE, while irq and fiq are processed
in REE.
If we enable the irq function in TEE, when we process
some signal-related scenarios in TEE,
such as the ostest sighand testcase, this testcase will
call up_irq_enable() to enable irq interrupt in the
arm_sigdeliver() function. After the signal processing
logic is executed, irq will be disabled again.
During the interval of enabling irq, some external device
irq interrupts will be enabled, but these external device
irqs do not have corresponding handlers registered in TEE,
so an "unexpected irq isr exception" will be triggered.
Therefore, a better implementation is to keep the original
implementation of the up_irq_enable() function, that is,
to enable only fiq in TEE and to enable irq and fiq in REE.
Then  for vendor-specific requirements, such as the need to
briefly enable irq during the TEE initialization process
and then disable irq before starting APz in TEE, we directly
provide a separate implementation of enabling irq in the
vendor, without modifying the implementation of the public
up_enable_irq() function.

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-21 01:36:32 +08:00
Filipe Cavalcanti
4d4d8a6ca5 arch/risc-v/esp32c3: fix AP password memcpy typo 2024-08-20 00:50:26 +02:00
cuiziwei
837410fad2 nuttx/sim:By default, stack-use-after-return is not checked when enabling SIM_ASAN.
==263401==ERROR: AddressSanitizer: stack-use-after-return on address 0xf515f260 at pc 0x042434f0 bp 0x9ac24e78 sp 0x9ac24e68
WRITE of size 4 at 0xf515f260 thread T0
    #0 0x42434ef in nxsem_get_value semaphore/sem_getvalue.c:65
    #1 0x413110d in work_thread wqueue/kwork_thread.c:195
    #2 0x412c4f6 in nxtask_start task/task_start.c:129
    #3 0x427b1fc in pre_start sim/sim_initialstate.c:52

Address 0xf515f260 is located in stack of thread T0 at offset 32 in frame
    #0 0x928c9e3 in host_settimer sim/posix/sim_hosttime.c:104

  This frame has 1 object(s):
    [32, 48) 'it' (line 105) <== Memory access at offset 32 is inside this variable
HINT: this may be a false positive if your program uses some custom stack unwind mechanism, swapcontext or vfork
      (longjmp and C++ exceptions *are* supported)

Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-08-19 19:54:17 +08:00
Yanfeng Liu
3166c6d9c6 riscv/qemu-rv: add RPTUN cmake
This adds cmake support for RPTUN.
2024-08-19 19:53:03 +08:00
Windrow14
190c8787ff arch/xtensa/src/esp32s3/Kconfig|Make.defs|esp32s3_sdmmc.c,
arch/xtensa/src/esp32s3/hardware/esp32s3_sdmmc.h|esp32s3_soc.h,
boards/xtensa/esp32s3/common/include/esp32s3_board_sdmmc.h,
boards/xtensa/esp32s3/common/src/Make.defs|esp32s3_board_sdmmc.c,
boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c: add SD/mmc driver

Support 1-bit bus width and 4-bit bus width. Support eMMC high speed SDR mode.
Support transfer data with DMA. Support SD clock frequency up to 40MHZ.

Signed-off-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
Reviewed-by: Yuezhang Mo <Yuezhang.Mo@sony.com>
Reviewed-by: Jacky Cao <Jacky.Cao@sony.com>
Tested-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
2024-08-19 19:52:39 +08:00
chenrun1
12318bd947 xtensa_cache:add up_get_cachesize api
Summary:
  Added up_get_dcache_size and up_get_icache_size common APIs

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-19 13:54:53 +08:00
guoshichao
29e50ebed8 greenhills: add dummy implementation for unused function
add dummy implementation to avoid the link error

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-19 10:37:54 +08:00
yanghuatao
b3627bb8c6 toolchain/ghs: Fix zero used for undefined preprocessing identifier "NR_IRQS" warnings
CC:  unistd/lib_setregid.c "/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 53: warning #193-D:
          zero used for undefined preprocessing identifier "NR_IRQS"
  #  if NR_IRQS <= 256
        ^
"/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 82: warning #193-D:
          zero used for undefined preprocessing identifier "NR_IRQS"
  #if NR_IRQS <= 256
CC:  mount/fs_umount2.c "/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 72: warning #193-D:
          zero used for undefined preprocessing identifier "NR_IRQS"
  #if NR_IRQS <= 256

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-19 10:37:54 +08:00
guoshichao
0cf0bece2e arch/strarg: provide the stdarg implementation for greenhills compiler
the greenhills compiler provide its own implementation of va_start,
va_end, va_arg, va_copy. so if we are build vela with greenhills
compiler, we should using the stdarg implementation provided by
greenhills, not our own

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-19 10:37:54 +08:00
xuxin19
9fdd299d32 cmake:split the archive process to avoid parameter problems
refer to:https://cmake.org/cmake/help/latest/variable/CMAKE_LANG_ARCHIVE_APPEND.html

this will solve the problem of too long parameters
when executing ar in cygwin environment such as msys.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-18 23:26:01 +08:00
Yanfeng Liu
b9fde453ce riscv/qemu-rv: add RPTUN support
This adds initial RPTUN support for qemu-rv and rv-virt device.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-18 19:55:27 +08:00
Yanfeng Liu
2af5ad174f riscv/qemu-rv: add RPTUN Kconfig
This add RPTUN related Kconfigs for qemu-rv chip.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-18 19:55:27 +08:00
Eren Terzioglu
e11a53bec9 esp32[c3|c6|h2]: Add adjustable SPI clock speed 2024-08-17 13:43:58 +08:00
Tiago Medicci
69a8e2697f espressif: Fix default pins for SPI bus 2 on ESP32-[C3|C6|H2]
Fix the correct pin number for the SPI 2 bus on ESP32-C3, ESP32-C6
and ESP32-H2.
2024-08-17 13:43:58 +08:00
Eren Terzioglu
61dff51a33 esp32[c3|c6|h2]: Fix SPI clock issue 2024-08-17 13:43:58 +08:00
Jouni Ukkonen
9c2af7284b arch/arm64/imx93: Add more base addresses
mem slice and src base address added

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-08-16 19:39:02 +08:00
Gao Feng
87ff0ddf6d xtensa/esp32s3: reserve memory for a mutex struct depending on the OS
Enabling CONFIG_PRIORITY_INHERITANCE config causes a build error

Based on Nuttx OS reserve memory for mutex struct.

Pass build based on
 - CONFIG_PRIORITY_INHERITANCE y
 - CONFIG_SEM_PREALLOCHOLDERS 0/8
2024-08-16 15:25:20 +08:00
Gao Feng
ddbbdd7fd3 xtensa/esp32s3: partition name duplicate and free 2024-08-16 15:11:14 +08:00
Jinliang Li
a5bfbca869 arm/armv8-r: invalidate d-cache on boot
Pass CP15_CACHE_INVALIDATE argument with r1 register to cp15_dcache_op_level.
cache level is 0(L1 D-Cache) with r0 register.
prototype:
void cp15_dcache_op_level(uint32_t level, int op)

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2024-08-16 13:41:19 +08:00
Jinliang Li
0e825b230d arm/armv8-r: add cp15 ops for mpu
Add some cp15 definitions for mpu configuration

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2024-08-16 13:27:31 +08:00
Alexis Guijarro
f05c85e622 arm/stm32h7x3x_rcc.c: Add External Power Supply option to stm32h7x3x targets 2024-08-15 02:52:45 +08:00
pengyiqiang
08cdff2046 arch/sim/Kconfig: set SIM_FBBPP to 32 by default
32bpp is the most commonly used option and should be used as the default

Signed-off-by: pengyiqiang <pengyiqiang@xiaomi.com>
2024-08-15 02:38:31 +08:00
chenxiaoyi
7ce5241f0e types.h: fix windows build error
Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt.h(605,39): error C2371: 'wint_t': redefinition; different basic types
Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt.h(606,39): error C2371: 'wctype_t': redefinition; different basic types

Co-authored-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
Co-authored-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-14 22:36:57 +08:00
chenxiaoyi
f512f5e8a9 windows sim:add MSCV atomic support for fix windows build error
VC\Tools\MSVC\14.40.33807\include\vcruntime_c11_stdatomic.h(36,24): error C2061: syntax error: identifier 'atomic_bool'
VC\Tools\MSVC\14.40.33807\include\vcruntime_c11_stdatomic.h(36,24): error C2059: syntax error: ';'
VC\Tools\MSVC\14.40.33807\include\vcruntime_c11_stdatomic.h(37,23): error C2061: syntax error: identifier 'atomic_char'
VC\Tools\MSVC\14.40.33807\include\vcruntime_c11_stdatomic.h(37,23): error C2059: syntax error: ';'
VC\Tools\MSVC\14.40.33807\include\vcruntime_c11_stdatomic.h(38,30): error C2061: syntax error: identifier 'atomic_schar'
VC\Tools\MSVC\14.40.33807\include\vcruntime_c11_stdatomic.h(38,30): error C2059: syntax error: ';'

Co-authored-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
Co-authored-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-14 22:36:57 +08:00
chenxiaoyi
b65efdba12 sim_hostmemory.c: fix windows build error
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(39,40): error C2146: syntax error: missing ')' before identifier 'exec'
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(39,35): error C2081: 'bool': name in formal parameter list illegal
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(39,40): error C2061: syntax error: identifier 'exec'
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(39,40): error C2059: syntax error: ';'
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(39,44): error C2059: syntax error: ')'
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(40,1): error C2449: found '{' at file scope (missing function header?)
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(42,1): error C2059: syntax error: '}'

Co-authored-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
Co-authored-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-14 22:36:57 +08:00
Yanfeng Liu
41dba46c1d arch/riscv: fix IRQ_SOFT for non-SMP
This fixes software interrupt number for non-SMP cases

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-14 20:59:52 +08:00
xuxin19
b073b3efc1 cmake:bugfix SIM_ASAN cannot automatically link libasan in cmake build
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-14 20:58:59 +08:00
simbit18
155517b5fc arch/sim/src/cmake/Toolchain.cmake: macOS fix unknown options: --gc-sections
fix
ld: unknown options: --gc-sections

added -> add_link_options(-Wl,-dead_strip)
2024-08-12 15:10:01 -03:00
Yanfeng Liu
f5b2fc371e riscv/qemu-rv: use cluster PLIC/CLINT configs
This uses cluster speficic PLIC, CLINT and ACLINT devices in NuttX.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-12 20:43:05 +08:00
Yanfeng Liu
6db85498a2 riscv/qemu-rv: add cluster PLIC/CLINT configs
This adds cluster specific configs for PLIC, CLINT and ACLINT
devices.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-12 20:43:05 +08:00
anjiahao
ce6d308cef armv8-m:fix log warnning
armv8-m/arm_securefault.c:72:11: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'uint32_t' {aka 'long unsigned int'} [-Wformat=]
   72 |   sfalert("\tCFSR: %08x HFSR: %08x DFSR: %08x\n", getreg32(NVIC_CFAULTS),
      |           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-08-12 01:52:35 +08:00
yanghuatao
fecc5091af toolchain/ghs: Fix SP_DSB warnings
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
          argument to macro is empty
    SP_DMB();
           ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
          argument to macro is empty
    SP_DMB();
           ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 296: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-11 14:28:12 -03:00
guoshichao
693e869404 arm-m/barrier: fix green hills build ARM_ISB error
according to armv6-m/armv7-m arch reference manual:
the three ISB {<opt>}, DSB {<opt>}, DMB {<opt>} instructions <opt>
field are defined as:
Specifies an optional limitation on the ISB/DSB/DMB operation. Allowered
values are:
Full system ISB/DSB/DMB operation, encoded as option=='1111'. Can be
omitted.
All other encodings of the options are RESERVED.
the "#opt" field of "isb #opt"

So we could remove the options field in Armv7-m platform.
The following are the build error with greenhills compiler:

CC:  common/arm_exit.c [asarm] (error #2071) /tmp/gh_001h70j1.si 92: bad parameter
  isb 15
------^

[asarm] (error #2071) /tmp/gh_001h70j1.si 112: bad parameter
  isb 15
------^

[asarm] (error) errors during processing

According to armv8-m arch reference manual:
the ISB/DMB instruction's "opt" encoding rule is same as
armv6-m/armv7-m, but the "DSB" instruction is different, in armv8-m, the
"DSB {<opt>}" field has two valid encoding options: 0b0000, 0b0100.
and all other encoding options are reserved.

In Armv7-a/Armv8-a, the dsb/dmb option field has 8 valid state value.

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-11 14:28:12 -03:00
fangxinyong
6da525704d toolchain/ghs: fix the inline assembly code register alloc compile error
The following are the compile error that reported
by GreenHills compiler:

"/mnt/yang/qixinwei_commit/nuttx/include/arch/syscall.h", line 156 (col. 17): error #2036-D:
          cannot allocate "reg0" to specified caller-saved register

 "/mnt/yang/qixinwei_commit/nuttx/include/arch/syscall.h", line 157 (col. 17): error #2036-D:
          cannot allocate "reg1" to specified caller-saved register

Then we fix this greenhills compilation error by explicitly specifying
the registers in the clobber list in the inline assembly code.
This fix is successful in compiling on the
nuttx/boards/arm/mps/mps2-an500/configs/nsh platform and passes
the ostest test.
However, if we keep the implementation the same for both the default
and Greenhills compilers, the default compiler will report the
following two issues:
1. the "sys_call6" function will report compile error when
compiling on "./vendor/qemu/boards/smartspeaker/configs/smartspeaker-knsh"
platform, the detailed error info:

CC:  proxies/PROXY_mq_getattr.c In file included from /home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/sys/syscall.h:35,
                 from /home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/syscall.h:30,
                 from proxies/PROXY_mmap.c:5:
In function 'sys_call6',
    inlined from 'mmap' at proxies/PROXY_mmap.c:9:22:
/home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/arch/syscall.h:297:3: error: 'asm' operand has impossible constraints
  297 |   __asm__ __volatile__
      |   ^~~~~~~

2. when running on qemu-armv7-a platform, the modification to
"smh_call()" function will make the system fail to boot up, so
we need to keep the default compiler implementation and greenhills
compiler implementation separate

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
(cherry picked from commit cb48b749b1c9cad8cfb96bff7c5e9b6ebf20fc8a)
2024-08-11 14:28:12 -03:00
yanghuatao
5bb805b229 toolchain/ghs: Fix green hills toolchain build Vela asarm errors
common/gnu/fork.S 29: unknown instruction
  .syntax unified
--^
[asarm] (error #2230) common/gnu/fork.S 81: bad directive
  .type up_fork , function
------------------^
[asarm] (error #2067) armv7-m/arm_saveusercontext.S 31: unknown instruction
  .syntax unified
--^

[asarm] (error #2230) armv7-m/arm_saveusercontext.S 55: bad directive
  .type up_saveusercontext , % function
--^

[asarm] (error #2004) armv7-m/arm_saveusercontext.S 65: not within valid register range
  str r12 , [ r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 4 ) ) ]
------^

[asarm] (error #2004) armv7-m/arm_saveusercontext.S 66: not within valid register range
  str r14 , [ r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 5 ) ) ]
------^

[asarm] (error #2004) armv7-m/arm_saveusercontext.S 67: not within valid register range
  str r14 , [ r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 6 ) ) ]
------^

[asarm] (error #2014) armv7-m/arm_saveusercontext.S 72: expected a register
  str r1 , [ r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 7 ) ) ]
------------------^

[asarm] (error #2004) armv7-m/arm_saveusercontext.S 75: not within valid register range
  add r1 , r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 8 ) )
-----------^

[asarm] (error #2071) armv7-m/arm_saveusercontext.S 89: bad parameter
  stmia r0 ! , { r2 - r11 }
--------^

[asarm] (error #2014) armv7-m/arm_saveusercontext.S 93: expected a register
  mov r1 , - 1
-----------^

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-11 14:28:12 -03:00
yanghuatao
3e171489bd toolchain/ghs: Fix green hills toolchain build Vela link error
[elxr] (error #412) unresolved symbols:
 __builtin_frame_address     from libarch.a(arm_checkstack.o)

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-11 14:27:02 -03:00
Yanfeng Liu
47b0414eab arch/riscv: add cluster local hartid
Some multicore RV chips (mpfs, jh7110 etc) have hart clusters
and globally numbered mhartids. Clusters with single hart or
SMP support can be managed by one NuttX instance. Currently
NuttX expects to use cluster-local ids.

This allows us to get local ids by offsetting mhartids with a
base value.

Note that there are chips (e.g. k230) that use cluster-local
ids directly, so this is not needed for them.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-12 00:10:13 +08:00
anjiahao
029411f00c arm:Select ram vector on armv6m
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-08-12 00:09:56 +08:00
Nicolas Gariepy
af78534df9 fix stm32wl5_rcc.h: Add the missing argument to RCC_PLLCFG_PLLP define. 2024-08-11 03:10:20 +08:00
chenwen@espressif.com
cde0de00fe xtensa/esp32s3: Update the rtc code to fix system blocking issue
1. For some reasons, the bootloader will set CPU source to BBPLL and enable it,
      but there are calibration issues, so we need turn off the BBPLL and do calibration again to fix the issue.
   2. Corresponding issue link: 89cc9084ab

Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-08-09 12:49:34 -03:00
Yanfeng Liu
46f4a24d59 riscv/qemu: add CMake for PROTECTED
This adds CMake support for PROTECTED build mode on rv-virt target.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-09 23:43:31 +08:00
Yanfeng Liu
01c37f7012 riscv/rv32m1: fix build issue
This exports `return_from_exception` symbol to fix build issue with
unified in-kernel syscall.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 21:25:59 +08:00
Yanfeng Liu
6986cd4105 arch/riscv: unify in-kernel syscall
This generalizes the in-kernel syscall approach from KERNEL mode to
all build modes so that to unify in-kernel syscall invocations.  As
a result, machine mode ECALL and the supervisor folder are no longer
needed.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 21:25:59 +08:00
nuttxs
2af8a886ab arch/xtensa/esp32: Replace nxsig_usleep() with up_udelay() to
avoid context switching, and the actual time difference caused
by the setting of TICK in nxsig_usleep() is quite large.
2024-08-08 20:01:46 +08:00
Daniel Jasinski
8399a780d8 build: Fix Toolchain.cmake for CONFIG_SIM_ASAN enabled
This commit adds missing add_link_options to specify sanitizers
also during linking stage.

Signed-off-by: Daniel Jasinski <jasinskidaniel95szcz@gmail.com>
2024-08-08 09:44:47 +08:00
Yanfeng Liu
77cfbf8914 riscv/fork: fix gp register handling
This fixes the handling of gp register in fork.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 09:42:29 +08:00
Yanfeng Liu
3f021d5429 riscv/fork: fix fp/s0 field position
The fp/s0 field position shall be in line with the macro
FORK_FP_OFFSET/FORK_S0_OFFSET.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 09:42:29 +08:00
Shoukui Zhang
f94160095e Adapt i2c slave callback interface for rp2040 and s32k11x
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Ville Juven
622e5b26b3 riscv/syscall: Fix fork() system call
When executing fork() via a system call, the parent's stack gets corrupted
by the child, as during exception return the child loads the parent's
stack pointer from the context save area.

This happens because the full parent stack (including what has been pushed
during the system call) is copied to the child. What should be copied, is
only the user stack of the parent (the kernel stack is not interesting).

Fix this by only copying the parent's user stack to the child; and make
the child return directly to userspace (not via dispatch_syscall).
2024-08-07 02:41:14 +08:00
Ville Juven
2cf8ac2f63 risc-v/riscv_swint.c: Simplify implementation of dispatch_syscall
Simplifies the implementation of dispatch_syscall, making it easier to
understand and maintain. Let the C-compiler do most of the work, instead
of doing everything as inline assembly.
2024-08-07 02:41:14 +08:00
Ville Juven
fa71bc3d74 riscv/syscall: Add dependency to RISCV_PERCPU_SCRATCH when LIB_SYSCALL=y
The per CPU scratch register is needed by system calls -> enable it by
default.
2024-08-07 02:41:14 +08:00
Julian Oes
75c65c7ce9 arch/stm32h7: add defines for USART clock selection
This adds the necessary defines to set the USARTs' kernel clock source
selection.

This is required for a configuration where the bootloader (running
before NuttX) changes the USARTs' clock selection, so they need to be
restored on board init.

This is according to the reference manual RM0399 page 448.
2024-08-06 14:31:21 +08:00
Filipe Cavalcanti
65e989e063 arch/risc-v: add support for motor control on ESP32|C6|H2 2024-08-05 15:35:19 -03:00
Yanfeng Liu
a36c168e54 riscv/nsbi: fix up_udelay for rv32
This fixes riscv_sbi_get_time for rv32 and NuttSBI is used.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-05 16:21:49 +08:00
chao an
4ef3eeb305 arch/x86_64: fix build break if disable CONFIG_SPINLOCK
Create version.h
chip/intel64_irq.c:78:34: error: conflicting type qualifiers for ‘g_irq_spin’
   78 | static spinlock_t                g_irq_spin;
      |                                  ^~~~~~~~~~
In file included from chip/intel64_irq.c:40:
include/nuttx/spinlock.h:168:28: note: previous declaration of ‘g_irq_spin’ with type ‘spinlock_t’ {aka ‘volatile unsigned char’}
  168 | extern volatile spinlock_t g_irq_spin;
      |                            ^~~~~~~~~~
chip/intel64_cpu.c: In function ‘x86_64_cpu_ready_set’:
chip/intel64_cpu.c:314:3: warning: implicit declaration of function ‘spin_lock’ [-Wimplicit-function-declaration]
  314 |   spin_lock(&g_ap_boot);
      |   ^~~~~~~~~
chip/intel64_cpu.c:322:3: warning: implicit declaration of function ‘spin_unlock’; did you mean ‘sched_unlock’? [-Wimplicit-function-declaration]
  322 |   spin_unlock(&g_ap_boot);
      |   ^~~~~~~~~~~

Signed-off-by: chao an <anchao@lixiang.com>
2024-08-05 16:20:47 +08:00
Yanfeng Liu
5848a8e77c riscv/qemu-rv: revise PROTECTED mode
This revises PROTECTED build for qemu-rv mainly to avoid hard-coded
addresses in linker scripts. It also added rv32 support, cleaned up
config `pnsh64` and added config `pnsh`.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-04 11:09:26 +08:00
Yanfeng Liu
cafee0e086 mm/mm.h: add mm_free_delaylist interface
This adds explicit `void mm_free_delaylist(heap)` interface so that
to force freeing the heap's delaylist.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-03 01:30:04 +08:00
Ville Juven
1f928b2338 qemu-rv: Add test target pnsh64 for BUILD_PROTECTED
This adds BUILD_PROTECTED target for rv-virt (rv-virt:pnsh64).
2024-08-02 20:29:11 +08:00
adriendesp
6ef8a73614 arch/xmc4 : fixed critical section in i2c_transfer
The critical section was declared at the wrong place.
The critical section wasn't left if error returned.
2024-08-02 20:28:25 +08:00
Lwazi Dube
a50dc7746c arm: Make ARMv5 boards work again
Fix some bugs found while trying run modern NuttX on an old board.
2024-08-02 13:39:40 +08:00
Yanfeng Liu
918ad10859 riscv/qemu: add NuttSBI support
This adds NuttSBI support for rv-virt device so that to enable CI
checks for NuttSBI later. It allows using `-bios nuttx` option to
run NuttX with QEMU v6.2 w/o OpenSBI.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-01 23:32:01 +08:00
Yanfeng Liu
ab7bc90ebb riscv/nsbi: halt upon sbi_mexception
This avoids endless restart if NuttSBI fails to enter S-mode.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-01 23:32:01 +08:00
Yanfeng Liu
5e551632dd riscv/nsbi: prefer PMP settings in device hook
This adjusts sbi_start behavior so that if SBI late initialization hook
is defined, PMP setting is assumed to be fully done in the hook, because
the default PMP operation may fail for various reasons such as lacking
free entries or the default setting doesn't work on devices like QEMU
v6.2.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-01 23:32:01 +08:00
Huang Qi
f9cc33468f riscv/espressif: Mark private data as static in esp_spi.c
These symbols only used in esp_spi.c and too simple
to conflict with others, so mark them as static:
- cfg
- ctx
- dev_cfg
- timing_param

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-08-01 23:28:53 +08:00
Ville Juven
cbb07a595e k230_start.c: Fix condition for k230_copy_init_data()
Fixes regression from https://github.com/apache/nuttx/pull/12220

Error: chip/k230_start.c:80:13: error: 'k230_copy_init_data' defined but not used [-Werror=unused-function]
   80 | static void k230_copy_init_data(void)
      |             ^~~~~~~~~~~~~~~~~~~
2024-08-01 23:27:30 +08:00
p-szafonimateusz
3c05da536a arch/intel64: add support for HPET as system clock
HPET can be used as system clock for x86_64

to set HPET as system clock you have to enable:
  CONFIG_ONESHOT=y
  CONFIG_ALARM_ARCH=y
  CONFIG_INTEL64_ONESHOT=y
  CONFIG_ARCH_INTEL64_HPET_ALARM=y

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-08-01 17:49:41 +08:00
Tiago Medicci
24954800a7 espressif: Update HAL version for all Espressif SoCs
Provides the most update libraries to support the drivers for the
Espressif SoCs.
2024-08-01 16:04:53 +08:00
Tiago Medicci
54b27c3d32 esp32s3/kconfig: Add more ESP32-S3 modules and fix comments
Other ESP32-S3 modules (with embedded flash and PSRAM) were added.
Also, the `help` section of the Kconfig was updated to better
describe the modules' flash and PSRAM sizes.
2024-08-01 16:04:53 +08:00
Huang Qi
6ea3bc1217 riscv/debug: Add support for steppoint
Steppoint can be implemented by icount(instruction count)
from RISC-V debug extension, but it may not implemented in all RISC-V cores.

Unfortunately, the currently supported RISC-V cores do not implement it.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-08-01 13:57:51 +08:00
Eren Terzioglu
00ff9ef15c esp32[c3|c6|h2]: Add SPI slave DMA support 2024-08-01 01:26:29 +08:00
Eren Terzioglu
f5b63cea18 esp32[c3|c6|h2]: Add SPI master DMA support 2024-08-01 01:26:29 +08:00
Inochi Amaoto
b35f7aed48 arch/risc-v: qemu: add AIA support
Implement AIA support for qemu rv-virt.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-31 12:43:04 -03:00
Inochi Amaoto
5f70307111 arch/risc-v: introduce AIA support
Advanced Interrupt Architecture (AIA) introduces flexiable interrupt
controll for RISC-V. It includes three parts: AIA CSRs, Incoming Message
Signaled Interrupt Controller (IMSIC) and  Advanced Platform-Level
Interrupt Controller (APLIC).

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-31 12:43:04 -03:00
Tiago Medicci
c99c3ceec2 up_copy_section: Improve function description
Add "Input Parameters" section to already existing definitions
and declarations of `up_copy_section` function.
2024-07-31 02:33:12 +08:00
Tiago Medicci Serrano
016bc47a63 esp32s3/elf: Enable ELF loader for ESP32-S3
Provide `up_copy_section` function that enables copying data using
the data bus. If the memory destination address is accessible
through the instruction bus, the data is copied using the
correspondent address accessible through the data bus.
2024-07-31 02:33:12 +08:00
zouboan
d74a612a6e zynq-mpsoc/zcu111: independent JTAG configs from normal nsh configs 2024-07-30 12:41:30 -03:00
p-szafonimateusz
07c1f5db92 arch/intel64/irq.h: rename rdtsc macros
rename _rdtsc macro to rdtsc to avoid conflict with external code
rename rdtsc macro to rdtscp to be the same as asm instruction used

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-07-30 21:53:08 +08:00
p-szafonimateusz
90e47bf1f5 arch/x86_64/src/intel64/intel64_cpu.c: remove workaround for spin_lock
remove workaround for spin_lock which is no longer needed after inline splinlock change
2024-07-30 21:40:53 +08:00
adriendesp
cd4fdf27c5 arch/xmc4 : i2c driver
Added lower half i2c driver
2024-07-30 18:23:19 +08:00
Yanfeng Liu
a6c7e68b5d riscv/qemu-rv: skip reloading mhartid
As a0 already has mhartid passed by SBI  or ZSBL, no need to load it
again here.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-30 18:20:22 +08:00
Tiago Medicci Serrano
c91599d34c esp32s3/i2s: Fix faulty initialization when SMP is enabled
The buffer initialization function (`i2s_buf_initialize`) calls
`i2s_buf_free`, which performs buffer initialization within a
critical section (`spin_lock_irqsave`). If this function is called
under the same critical section (same spinlock), initialization
will hang.
2024-07-30 01:44:57 +08:00
Tiago Medicci Serrano
1ab1a905b8 esp32s3/i2s: Add CONFIG_ESP32S3_I2S_MAXINFLIGHT to Kconfig
Enable setting the number of in-flight buffers to be used by the
I2S peripheral on ESP32-S3 using Kconfig.
2024-07-30 01:44:57 +08:00
anjiahao
bc1083ac33 arm_backtrace_unwind:Make the backtrace search the entire stack as much as possible
also fixbacktrace crash when idle thread lr is random

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-07-29 22:19:56 +08:00
Eren Terzioglu
98f5d6adc5 esp32[s2|s3]: Add temperature sensor support 2024-07-27 14:12:44 -03:00
Eren Terzioglu
e467a16abe esp32[c3|c6|h2]: Add temperature sensor support 2024-07-27 14:12:44 -03:00
Henry Rovner
23bc78a5b7 bl808_wdt: Expand function headers 2024-07-27 22:59:23 +08:00
Henry Rovner
42eafcdfa5 risc-v/bl808: Add watchdog driver
This change implements a driver for the two watchdog timers on the BL808, and enables it as part of the timer config. The driver is based on the GP timer driver.
2024-07-27 22:59:23 +08:00
Filipe Cavalcanti
91dfd20eaf arch/xtensa: add support for brushed DC motor control
arch/xtensa: add support for capture driver on ESP32 and ESP32|S3|

Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed

Basic bring up ready. New Kconfig options for motor.

Good motor registration

Working on enabling pwm generators

Working on enabling pwm generators

Added fops functions

Success on PWM 50%

stable pwm operation for bdc

Added loopback option for testing

Improved rules on fsm

Working motor direction control

Testing new ISR for fault handling

Issues on fault ISR

Removed fault implementation (not working)

Added support for esp32s3

Documentation improvements

Added default motor spin direction

Added parameter change while running

Review fixes

arch/xtensa: add support for fault signal on motor control

Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed

Basic bring up ready. New Kconfig options for motor.

Good motor registration

Working on enabling pwm generators

Working on enabling pwm generators

Added fops functions

Success on PWM 50%

stable pwm operation for bdc

Added loopback option for testing

Improved rules on fsm

Working motor direction control

Testing new ISR for fault handling

Issues on fault ISR

Removed fault implementation (not working)

Added support for esp32s3

Documentation improvements

Added default motor spin direction

Added parameter change while running

Got responsive fault indicator

Working brakes - still need to work on starting isr

Fixed single-time ISR initializiation

Working soft brake on fault

Improved KConfig for BDC and BLDC

Kconfig fixed at board level
2024-07-27 12:08:51 +08:00
Huang Qi
d7f82fb14c Correct comment blocks
Fix wrong comment blocks in the following files:
- arch/arm/src/stm32f0l0g0/stm32_pwr.c
- include/nuttx/mtd/nand_config.h

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-27 03:11:39 +08:00
Huang Qi
3b70bf7ff0 samv7: Fix comment block in sam_rstc.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-27 03:11:39 +08:00
raiden00pl
e75c19ce58 arch/arm/{nrf53|nrf91}: enable fpu if CONFIG_ARCH_FPU=y
enable fpu if CONFIG_ARCH_FPU=y, the previous condition depended on CONFIG_ARCH_HAVE_FPU=y
2024-07-26 23:46:34 +08:00
buxiasen
f5021021ae up_backtrace: fix maybe backtrace the exiting thread
when the thread to backtrace is exiting, get_tcb and up_backtrace in
different critical section may cause try to dump invalid pointer, have
to ensure the nxsched_get_tcb and up_backtrace inside same critical
section procedure.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-07-26 12:03:43 +08:00
Yanfeng Liu
9e59b0b43b riscv/qemu: guard u16550 uses
This guards the uses for u16550 serial initialization, just in case
that no u16550 is configured.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-26 12:01:29 +08:00
Henry Rovner
049a6da098 risc-v/bl808: Add timer driver
This change implements a driver for the hardware timer blocks on the BL808, as well as a config with the timer example enabled.
2024-07-24 10:06:54 +08:00
nuttxs
a83a569652 arch/xtensa/esp32s3: Add qspi/spi_slave/lcd DMA request return value.
Optimize DMA initialization for duplicate calls.
2024-07-23 22:48:24 +08:00
Yanfeng Liu
3b9a346fe7 riscv/nsbi: unblock up_udelay
This fixes the always zero time in NuttSBI case as the `error` field
contains the correct timestamp. This in turn also fixes the block of
`up_udelay()` which further leads to boot failure of `canmv230:master`
config.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-22 23:46:43 +08:00
Inochi Amaoto
0ddcbe62ec arch/risc-v: does not clear IPI address in S mode
According to the riscv-aclint doc, writing 0 to SSWI address
has no effect. Remove this unnecessary write for S mode.

Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-18 22:59:29 +08:00
YAMAMOTO Takashi
985d395b02 esp32s3_textheap.c: fix a build error w/o CONFIG_ESP32S3_SPIRAM 2024-07-18 16:42:52 +08:00
nuttxs
de3737cd90 arch/xtensa/esp32s3: Deinitialize ESP32-S3 QSPI GDMA engine.
Correctly releasing channels after using QSPI is crucial
to prevent issues caused by multiple requests that may lead
to DMA channel resource conflicts.
2024-07-18 13:41:04 +08:00
chao an
7780cfc5a6 tricore/cmake: add support of cmake build for tricore
Toolchain Upstream:
https://github.com/EEESlab/tricore-gcc-toolchain-11.3.0

CMake command:
$ cmake -B build -DBOARD_CONFIG=tc397/nsh -GNinja
$ cmake --build build

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-18 13:40:49 +08:00
Inochi Amaoto
000b0ec4a1 arch/risc-v: make common up_allocate_heap weak symbol
The common `up_allocate_heap` is a strong symbol, which leads to
error when building with CONFIG_DEBUG_LINK_WHOLE_ARCHIVE. Make
`up_allocate_heap` weak function to mitigate this problem.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-18 13:40:37 +08:00
Lup Yuen Lee
bdf60d7966 risc-v/bl808, sg2000: Configure MMU to cache Kernel Text, Data and Heap (T-Head C906)
This PR configures the BL808 and SG2000 MMU (inside T-Head C906) to cache the the Kernel Text, Data and Heap.  We set the MMU Flags (Shareable, Bufferable and Cacheable) as explained in this article: https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906

This PR fixes the Slow Memory Access for NuttX Kernel in BL808 and SG2000: https://github.com/apache/nuttx/issues/12696

In the next PR, we will fix the Slow Memory Access for NuttX Apps, by caching the User Text and Data.

arch/risc-v/src/bl808/bl808_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for BL808 Kernel Text, Data and Heap

arch/risc-v/src/sg2000/sg2000_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for SG2000 Kernel Text, Data and Heap
2024-07-17 12:08:04 -03:00
Yanfeng Liu
d6c67c555f riscv/trap: fix sp restore logic
This fixes stack pointer restore logic to avoid parent stack corruption
by forked child in PROTECTED build.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-17 17:20:00 +08:00
Yanfeng Liu
08c4686f47 riscv/fork: fix tp for PROTECTED
This fixes `tp` value of forked child in PROTECTED build to support
vfork. Why? the optimized `dispatch_syscall` requires `tp` to hold
the task TCB since commit e6973c764c.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-17 17:20:00 +08:00
chao an
4db1169e6f arch/tricore: fix compiler warning on GCC toolchain
tc3xx/tc3xx_timerisr.c: In function ‘up_timer_initialize’:
tc3xx/tc3xx_timerisr.c:58:39: warning: passing argument 1 of ‘tricore_systimer_initialize’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
   58 |   lower = tricore_systimer_initialize(&MODULE_STM0, 192, SCU_FREQUENCY);
In file included from tc3xx/tc3xx_timerisr.c:31:
nuttx/arch/tricore/src/common/tricore_internal.h:252:35: note: expected ‘void *’ but argument is of type ‘volatile Ifx_STM *’ {aka ‘volatile struct _Ifx_STM *’}
  252 | tricore_systimer_initialize(void *tbase, int irq, uint64_t freq);
      |                             ~~~~~~^~~~~
tc3xx/tc3xx_serial.c:177:16: warning: initialization discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
  177 |   .uartbase  = &MODULE_ASCLIN0,
      |                ^
tc3xx/tc3xx_serial.c:178:16: warning: initialization discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
  178 |   .pins      = &g_uart0_pins,
      |                ^
common/tricore_trapcall.c: In function ‘tricore_trapcall’:
common/tricore_trapcall.c:66:3: warning: passing argument 4 of ‘_assert’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
   66 |   PANIC_WITH_REGS("Trap", CURRENT_REGS);
      |   ^~~~~~~~~~~~~~~
In file included from common/tricore_trapcall.c:29:
nuttx/include/assert.h:189:45: note: expected ‘void *’ but argument is of type ‘volatile uintptr_t *’ {aka ‘volatile long unsigned int *’}
  189 |              FAR const char *msg, FAR void *regs);

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-17 17:18:02 +08:00
chao an
8e20b8d862 arch/tricore: add support of tricore gcc toolchain
Toolchain Upstream:
https://github.com/EEESlab/tricore-gcc-toolchain-11.3.0

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-17 17:18:02 +08:00
zouboan
b817db86b8 zynq-mpsoc: add support for mio/emio 2024-07-16 18:50:52 -03:00
chao an
bc7791e079 arch/tricore: synchronize instruction/data following MTCR/MFCR
Some barrier are necessary to avoid compiler optimizations

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-16 21:13:13 +08:00
GC2020
8f243d3eb7 /rp2040 Rename the RP2040-specific PWM_MULTICHAN definition to avoid confusion with the global PWM_MULTICHAN 2024-07-16 20:09:10 +08:00
shizhenghui
fea727a050 arch/sim/Makefile: add openh264 & x264 include path
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
347864152d sim codec: add dependence to Kconfig
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
61f79757f7 v4l2m2m/sim encoder: move hostencoder to x264encoder
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
7248ba0293 sim decoder: update CMakeLists.txt
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
3675cfe585 v4l2m2m/sim decoder: rename hostdecoder to openh264dec
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
Eren Terzioglu
0df037855a esp32[c3]: Add mcuboot build script for esp32c3-legacy 2024-07-16 10:30:56 +08:00
Eren Terzioglu
a9082e0882 esp32[s2]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
c9f5ae5fa4 esp32[s3]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
024e95875a esp32: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
553b1f5f5e esp32[c3|c6|h2]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
adriendesp
baf52268cc arch/xmc4: Added pwm driver 2024-07-15 16:14:55 -03:00
Peter van der Perk
622b6d234a s32k1xx: FlexIO I2C master driver 2024-07-15 10:06:55 -03:00
Raman Gopalan
ef271b8fe2 at32uc3a0: Initial work for SimpleMachines' Mizar32-A 2024-07-15 20:46:41 +08:00
Yanfeng Liu
8bdc975abb riscv/cmake: fix Toolchain.cmake issue
This fixes the following issue when configuring canmv230:master
with Ubuntu stock toolchain and cmake 3.22:

```
CMake Error at .../arch/risc-v/src/cmake/Toolchain.cmake:218 (if):
  if given arguments:
    "STREQUAL" "GNU_RVG"
  Unknown arguments specified
```

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-15 19:41:03 +08:00
hujun5
a4fece3450 spin_lock: inline spin_lock
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
2024-07-15 02:29:30 +08:00
zouboan
ae8ce535f3 arm64/arm64_boot.c: Fix exception caused by accesses to ICC_SRE_EL3 when GICv3 was not implemented 2024-07-15 02:26:40 +08:00
Huang Qi
e047ab9c70 riscv: Initial support for debug trigger module
Implement up_debugpoint_add/up_debugpoint_remove for riscv.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-14 20:32:19 +08:00
Eren Terzioglu
c15c0d1a78 esp32[h2]: Add MCUBoot support 2024-07-14 11:38:29 +08:00
Eren Terzioglu
0f0c258fa2 esp32[c6]: Add MCUBoot support 2024-07-14 11:38:29 +08:00
zouboan
ea532cb11a arch/arm64: add initial support for ZYNQ MPSOC
arch/arm64: add initial support for ZYNQ MPSOC

arch/arm64: add initial support for ZYNQ MPSOC
2024-07-13 20:51:39 -03:00
Yanfeng Liu
211e2cd8b9 riscv/k230: revise canmv230:pnsh
This revises canm230:pnsh in a few ways:

- adjusting linker scripts structure,
- asserting PMP setting results,
- adjusting configs for both k230d and k230 devices.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-13 07:21:22 -03:00
Michal Lenc
5c48944e0b samv7: fix compile warning in PWM and UART drivers
The following warnings is fixed:

chip/sam_pwm.c:961:12: warning: unused variable 'regval' [-Wunused-variable]
  961 |   uint32_t regval;

chip/sam_serial.c: In function 'sam_dma_txavailable':
chip/sam_serial.c:2264:7: warning: unused variable 'rv' [-Wunused-variable]
 2264 |   int rv;

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-13 11:37:06 +02:00
simbit18
f12c4e05cc Fix Kconfig style
Remove spaces from Kconfig files
Add TABs
Replace help => ---help---
Remove extra TABs
2024-07-12 06:37:59 +08:00
chao an
d4024c8388 arch/armv8-r: update g_running_tasks before context switch
fix invalid running_task() in assertion logic

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-12 00:39:37 +08:00
simbit18
2f8560e838 tools/ci: enable avr32dev1 build
removed in the tools/ci/testlist/other.dat file the entries
 -avr32dev1:nsh
 -avr32dev1:ostest

avr32_bringup.c
Fix  Error: ./avr32_bringup.c:54:4: error: #warning "Not Implemented"

comment out directive '#warning'
/* #warning "Not Implemented" */

avr_doirq.c

fix avr32/avr_doirq.c:117: error: assignment discards qualifiers from pointer target type
  regs = g_current_regs; -> regs = (uint32_t *)g_current_regs;
2024-07-12 00:39:21 +08:00
chao an
95a9facf3a arch/armv8-r: new config to set SPIs Configuration to edge-triggered
Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-11 15:35:41 +08:00
Henry Rovner
091372069c risc-v/bl808: Add SPI driver
This commit implements a driver for SPI0 and SPI1 on the BL808 and introduces an accompanying example configuration.
2024-07-11 11:32:24 +08:00
chao an
b191153cdc arch/armv8-r: fix typos in config
replace ARMV7R to ARMV8R

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-10 18:41:13 -03:00
Michal Lenc
a91d40e0e8 samv7: fix CAN FD configuration
Larger RX/TX buffers might be required for both FD and FD_BSW modes.
Default bit timing values are also changed since the original ones
did not provide correct results for default SAMv7 board clock selection
(150 MHz clock frequency). The current values provide correct bit timing
with sample point as close to 87.5 %.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-10 11:33:03 -03:00
Michal Lenc
e16ee4dba3 can: enhance bit timing ioctl to set both nominal and data bit timing
This adds field type to canioc_bittiming_s structure that allows
to set/obtain bit timing for both CAN CC and CAN FD.
CANIOC_GET_BITTIMING is now bidirectional: user specifies type field
and gets other fields from the controller.

The commit also updates current CAN FD capable controllers using the
ioctl. The type is not checked for classical CAN only controllers
and nominal bit timing is returned regardless of type value.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-10 11:33:03 -03:00
Eero Nurkkala
48cf91a7be arm64/imx9: ccm: add default clk init
This adds enablers for setting various clocks to some default
values. Also, this provides helpers to grant nonsecure access
to a number of clocks. Bootloader may utilize these to make
the system boot in a deterministic manner.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-07-09 21:14:11 -03:00
xuxingliang
848eca04ca arch/arm64: allow to use custom idle
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-07-09 19:36:48 +08:00
xuxingliang
94387630c9 arch/arm64: remove not used idle trace
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-07-09 19:36:48 +08:00
Lwazi Dube
b881868f19 arch/arm/sama5: Fix typos in ohci driver comments. 2024-07-09 09:20:13 +08:00
Huang Qi
d0210c1174 riscv_tcbinfo: Fix register ordering for PC
X0 is always 0 but still should be transfered to the client, but it don't existed in thread context, use any other register for it, and its value will be omitted by gdb client.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-08 21:13:25 +08:00
chao an
cef9addbbb sim/cmake: enable garbage collection of unused input sections
enable --gc-sections for linker
enable -ffunction-sections -fdata-sections for compiler

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-06 11:31:40 +08:00
chao an
9915b80e30 arch/sim: add custom data section support
The link script of NuttX Simulator is generated through compilation
options. This PR will support configure special data sections in
kconfig to meet the support of 3rd party applications.

we need to follow the syntax of linker script. In 3rd-party applications, some data will be labeled as section:

| a.c:
| struct task_s a __attribute__((section(".data.custom.taska")));
| b.c:
| struct task_s b __attribute__((section(".data.custom.taskb")));

Data of the same type struct can be placed in a fixed location to reduce the overhead caused by searching:

|   .data           :
|   {
|     _custom_data_table_start = .;
|     KEEP(*(.data.custom.*))
|     _custom_data_table_end = .;
|   }

Such section declare can be configured via Kconfig in the PR:

| CONFIG_SIM_CUSTOM_DATA_SECTION=" .data : { _custom_data_table_start = .; KEEP(*(.data.custom.*)) _custom_data_table_end = .; } "

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-05 16:45:36 -03:00
Jukka Laitinen
b008653ac0 arch/arm64/src/imx9/imx9_lowputc.c: Fix an arithmetic sign error in divisor calculation
In the algorithm there is a subtraction (int - unsigned), which results (potentially overflowed)
unsigned.

Passing this to macro ABS and the assigning to int doesn't work ( unsigned is always >= 0 ).

Fix this by replacing (dangerous) ABS macro with stdlib's standard "int abs(int)"
and change the substraction to (int - int).

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-07-05 21:47:07 +08:00
Jukka Laitinen
31644ec0f5 arch/arm64/src/imx9: Add an mtd driver for NOR flash on FlexSPI interface
This is an initial FlexSPI SPI NOR MTD driver for IMX9

This supprts M25P SPI NOR on FlexSPI for now, and can later be extended to other
SPINOR devices if needed. The following configurations are needed to use this driver:
  CONFIG_IMX9_FLEXSPI_NOR=y
  CONFIG_MTD_M25P=y

In addition, board initialization logic needs to call the imx9_flexspi_nor_initialize
to receive a pointer to the mtd device.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Co-authored-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-07-05 21:46:47 +08:00
Jouni Ukkonen
31a6a4f5d0 imx9: Add flexspi support, ported from imxrt
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-07-05 21:46:47 +08:00
Henry Rovner
a83e7ced77 ox64: Add adc example config 2024-07-05 13:17:02 +08:00
Henry Rovner
8493273c2c risc-v/bl808: Add GPADC character driver
This commit implements a character driver for the general purpose ADC of the BL808, based on the hardware scanning functionality. The driver supports setting different conversion resolutions and the order of channels to be scanned via menuconfig.
2024-07-05 13:17:02 +08:00
Filipe Cavalcanti
0c63840b18 arch/risc-v: add support for capture driver on ESP32C6 and ESP32H2. 2024-07-04 18:24:50 -03:00
Daniel P. Carvalho
3e4a16d851 arch/arm/stm32: Fix EXTI lines definitions for STM32G47XX. 2024-07-04 18:23:51 -03:00
Michal Lenc
f1ef5daa92 samv7/sam_mcan.c: fix TSEG1, TSEG2 and SJW compile warnings for MCAN1
Following warnings were caused by incorrect naming of few defines.

chip/sam_mcan.c:415:7: warning: "MCAN1_NTSEG1" is not defined, evaluates to 0 [-Wundef]
  415 | #  if MCAN1_NTSEG1 > 63
      |       ^~~~~~~~~~~~
chip/sam_mcan.c:418:7: warning: "MCAN1_NTSEG2" is not defined, evaluates to 0 [-Wundef]
  418 | #  if MCAN1_NTSEG2 > 15
      |       ^~~~~~~~~~~~
chip/sam_mcan.c:421:7: warning: "MCAN1_NSJW" is not defined, evaluates to 0 [-Wundef]
  421 | #  if MCAN1_NSJW > 15

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-04 18:23:13 -03:00