tc3xx/tc3xx_timerisr.c: In function ‘up_timer_initialize’:
tc3xx/tc3xx_timerisr.c:58:39: warning: passing argument 1 of ‘tricore_systimer_initialize’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
58 | lower = tricore_systimer_initialize(&MODULE_STM0, 192, SCU_FREQUENCY);
In file included from tc3xx/tc3xx_timerisr.c:31:
nuttx/arch/tricore/src/common/tricore_internal.h:252:35: note: expected ‘void *’ but argument is of type ‘volatile Ifx_STM *’ {aka ‘volatile struct _Ifx_STM *’}
252 | tricore_systimer_initialize(void *tbase, int irq, uint64_t freq);
| ~~~~~~^~~~~
tc3xx/tc3xx_serial.c:177:16: warning: initialization discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
177 | .uartbase = &MODULE_ASCLIN0,
| ^
tc3xx/tc3xx_serial.c:178:16: warning: initialization discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
178 | .pins = &g_uart0_pins,
| ^
common/tricore_trapcall.c: In function ‘tricore_trapcall’:
common/tricore_trapcall.c:66:3: warning: passing argument 4 of ‘_assert’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
66 | PANIC_WITH_REGS("Trap", CURRENT_REGS);
| ^~~~~~~~~~~~~~~
In file included from common/tricore_trapcall.c:29:
nuttx/include/assert.h:189:45: note: expected ‘void *’ but argument is of type ‘volatile uintptr_t *’ {aka ‘volatile long unsigned int *’}
189 | FAR const char *msg, FAR void *regs);
Signed-off-by: chao an <anchao@lixiang.com>
This fixes the following issue when configuring canmv230:master
with Ubuntu stock toolchain and cmake 3.22:
```
CMake Error at .../arch/risc-v/src/cmake/Toolchain.cmake:218 (if):
if given arguments:
"STREQUAL" "GNU_RVG"
Unknown arguments specified
```
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This revises canm230:pnsh in a few ways:
- adjusting linker scripts structure,
- asserting PMP setting results,
- adjusting configs for both k230d and k230 devices.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
The following warnings is fixed:
chip/sam_pwm.c:961:12: warning: unused variable 'regval' [-Wunused-variable]
961 | uint32_t regval;
chip/sam_serial.c: In function 'sam_dma_txavailable':
chip/sam_serial.c:2264:7: warning: unused variable 'rv' [-Wunused-variable]
2264 | int rv;
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Larger RX/TX buffers might be required for both FD and FD_BSW modes.
Default bit timing values are also changed since the original ones
did not provide correct results for default SAMv7 board clock selection
(150 MHz clock frequency). The current values provide correct bit timing
with sample point as close to 87.5 %.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This adds field type to canioc_bittiming_s structure that allows
to set/obtain bit timing for both CAN CC and CAN FD.
CANIOC_GET_BITTIMING is now bidirectional: user specifies type field
and gets other fields from the controller.
The commit also updates current CAN FD capable controllers using the
ioctl. The type is not checked for classical CAN only controllers
and nominal bit timing is returned regardless of type value.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This adds enablers for setting various clocks to some default
values. Also, this provides helpers to grant nonsecure access
to a number of clocks. Bootloader may utilize these to make
the system boot in a deterministic manner.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
X0 is always 0 but still should be transfered to the client, but it don't existed in thread context, use any other register for it, and its value will be omitted by gdb client.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
The link script of NuttX Simulator is generated through compilation
options. This PR will support configure special data sections in
kconfig to meet the support of 3rd party applications.
we need to follow the syntax of linker script. In 3rd-party applications, some data will be labeled as section:
| a.c:
| struct task_s a __attribute__((section(".data.custom.taska")));
| b.c:
| struct task_s b __attribute__((section(".data.custom.taskb")));
Data of the same type struct can be placed in a fixed location to reduce the overhead caused by searching:
| .data :
| {
| _custom_data_table_start = .;
| KEEP(*(.data.custom.*))
| _custom_data_table_end = .;
| }
Such section declare can be configured via Kconfig in the PR:
| CONFIG_SIM_CUSTOM_DATA_SECTION=" .data : { _custom_data_table_start = .; KEEP(*(.data.custom.*)) _custom_data_table_end = .; } "
Signed-off-by: chao an <anchao@lixiang.com>
In the algorithm there is a subtraction (int - unsigned), which results (potentially overflowed)
unsigned.
Passing this to macro ABS and the assigning to int doesn't work ( unsigned is always >= 0 ).
Fix this by replacing (dangerous) ABS macro with stdlib's standard "int abs(int)"
and change the substraction to (int - int).
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This is an initial FlexSPI SPI NOR MTD driver for IMX9
This supprts M25P SPI NOR on FlexSPI for now, and can later be extended to other
SPINOR devices if needed. The following configurations are needed to use this driver:
CONFIG_IMX9_FLEXSPI_NOR=y
CONFIG_MTD_M25P=y
In addition, board initialization logic needs to call the imx9_flexspi_nor_initialize
to receive a pointer to the mtd device.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Co-authored-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
This commit implements a character driver for the general purpose ADC of the BL808, based on the hardware scanning functionality. The driver supports setting different conversion resolutions and the order of channels to be scanned via menuconfig.
Following warnings were caused by incorrect naming of few defines.
chip/sam_mcan.c:415:7: warning: "MCAN1_NTSEG1" is not defined, evaluates to 0 [-Wundef]
415 | # if MCAN1_NTSEG1 > 63
| ^~~~~~~~~~~~
chip/sam_mcan.c:418:7: warning: "MCAN1_NTSEG2" is not defined, evaluates to 0 [-Wundef]
418 | # if MCAN1_NTSEG2 > 15
| ^~~~~~~~~~~~
chip/sam_mcan.c:421:7: warning: "MCAN1_NSJW" is not defined, evaluates to 0 [-Wundef]
421 | # if MCAN1_NSJW > 15
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This compilation flag was added in the same way as done for esp32
in order to avoid unexpected behaviors when accessing registers
using struct bitfields.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.
This commit also removes deprecated code and makes this bootloader
configuration as default for esp32 targets and removes the need
for running 'make bootloader' command for it.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
Move and unify map_rom_segments function called when starting
Simple Boot and MCUboot compatible images.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
sometimes ubsan work with asan trigger a mistake report, make it
possible to export library with ubsan, and bypass runtime feature.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
This current driver does not handle well netpkts used in the
write buffers.
I learned about this document:
https://github.com/apache/nuttx/blob/master/Documentation/components/net/netdriver.rst
After I ported and contributed the original driver.
However from the document, I understand these types of drivers are
simpler to implement and I could simplify the driver and handle
correctly the TCP write buffers.
Add addrenv support for x86_64.
For now we support mapping on PT level, so PD, PDT and PML4 are static
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
use new MMU api to implement up_map_region().
The new implementation support maping over 0xffffffff but requires CONFIG_MM_PGALLOC=y
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
During the boot phase, when we transition from tee smp to ap smp, we can use a busy waitflag to wait for the completion of the initialization of ap's core0
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Only in the non-critical region， nuttx can the respond to the irq and not hold the lock
When returning from the irq, there is no need to check whether the lock needs to be restored
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
When the PSRAM is enabled, we should not allocate the TX/RX
buffers there, so we use kmm_calloc here, to make it into IRAM,
so the ethernet controller can read bytes from it.
Add support for XSAVE/XRSTOR to handle x86_64 procesor extended states.
Support for these instructions is required to support AVX instruction set
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Use 32bit operations for id field in intel64_cpu_s which is int type.
This fixes an error that appears when enabling some debug options:
`Error: operand size mismatch for `movq'``
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Intel64 can now boot application cores which is needed for SMP
IMPORTANT: CONFIG_BOARD_LOOPSPERMSEC must be properly configured,
otherwise AP boot sequence can fail due too short delays during the AP startup
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Add support for inter-processor signaling in x86_64 based on up_trigger_irq() interface.
Preparations for SMP.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
reduce the time consumed by function call
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Use GS base regsiter to store reference to CPU private data.
Then we can easily refer to private CPU data using the GS segment.
Required for SMP support.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
It turns out that the D0 core of the BL808 has an IRQ that represents all interrupt sources for the M0 core. This change uses this IRQ to access these sources, eliminating the need for IPC between M0 and D0.
fix missing reference to comm_region->tsc_khz and
fix 'defined but not used' warnings in arch/x86_64/intel64_rtc.c
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Hide --whole-archive behind Kconfig option for x86.
This option is not needed and breaks ELF modules build.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
on ACRN hypervisor obtaining frequency from CPUID seems to be broken,
so we have to specify this value from Kconfig.
If frequency autodetection is enabled but the returned data are
incorrect - crash early.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
- This PR adds the GPIO Driver for BL808 SoC. This will be used by the upcoming LED Driver for Ox64 Board.
- The BL808 GPIO Driver was derived from the NuttX Driver for BL602 GPIO
Co-Authored-By: Lup Yuen Lee <luppy@appkaki.com>
Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed
For now, IOB off-loading in the wireless driver was removed because
it is not compatible with SMP-enabled devices, which is valid for
ESP32-S3. The performance gain by keeping the IOB off-loading in
the wireless drivers is not exceeded by keeping the flat buffer
approach and enabling `CONFIG_SMP=y`.
This commit modifies the existing serial driver to add support for the remaining UARTs on the BL808. It also introduces support for setting baud rate, character length, stop bits, parity, flow control and which serial port acts as the console.
Use `nxsched_gettid` instead of `nxsched_getpid`. Previously each
kernel thread was modelled as a task, so the pid is the same of the
kthread id. Now, with shared kthread group (introduced by #12320),
the pid of all kthreads will be 0 by design in shared group.
This change implements a system for allowing the D0 core (which runs NuttX) to receive forwarded interrupts from the M0 core. This makes it possible for drivers that rely on interrupts to work with peripherals attached to the M0 core.
cpu0 cpu1:
user_main
signest_test
sched_unlock
nxsched_merge_pending
nxsched_add_readytorun
up_cpu_pause
arm_sigdeliver
enter_critical_section
Reason:
In the SMP, cpu0 is already in the critical section and waiting for cpu1 to enter the suspended state.
However, when cpu1 executes arm_sigdeliver, it is in the irq-disabled state but not in the critical section.
At this point, cpu1 is unable to respond to interrupts and
is continuously attempting to enter the critical section, resulting in a deadlock.
Resolve:
adjust the logic, do not entering the critical section when interrupt-disabled.
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
As suggested in PR:12530, changed the default names of ESP32S3WROOM chips to ESP32S3WROOM1N4,
ESP32S3WROOM2N16R8, ESP32S3WROOM2N32R8, ESP32S3MINI1N8.
Also regenerated all the defconfigs for board configurations.
Added a custom ESP32S3 module for custom flash configurations.
Declared ESP32S3_PSRAM_8M variable with prompt
we can use g_cpu_lockset to determine whether we are currently in the scheduling lock,
and all accesses and modifications to g_cpu_lockset, g_cpu_irqlock, g_cpu_irqset
are in the critical section, so we can directly operate on it.
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
- In some cases, an operational Ethernet MAC may have no PHY, for example
when the system has a direct RMII MAC-to-MAC link.
- New config option STM32H7_NO_PHY
- With this option, PHY-specific code in the ethernet driver is not built
- This option is inherently incompatible with autonegotiation and speed and
duplex settings must be compiled in
To simplify processing, the existed SBI function code is just
invoking the ecall and return the error value. This omits
potential return value in "a1", which is defined in SBI doc.
Add the "sbiret" struct so it can handle all the return value.
In addition, there are some minor improvement:
1. move the SBI related interface to a separate file to make it clean.
2. add all necessary SBI ecall interface macro until version 2.0.
3. add an utilty function to convert sbi error numner to standard
error number.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
This revises `getregXX` and `setregXX` for rv64ilp32 to overcome
the limitation of compiler generated addresses and reach devices
in a larger range.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This PR adds support for Milk-V Duo S 64-bit RISC-V SBC, based on SOPHGO SG2000 SoC (T-Head C906 Core). Most of the code is derived from NuttX for Ox64 BL808. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-sg2000
Modified Files:
`boards/Kconfig`: Added Milk-V Duo S board
`arch/risc-v/src/sg2000/sg2000_timerisr.c`: Fixed MTIMER_FREQ for sleep() to work correctly
New Files in boards/risc-v/sg2000/milkv_duos:
`src/sg2000_appinit.c`: Startup Code
`include/board.h`: Milk-V Duo S Definitions
`include/board_memorymap.h`: Memory Map
`src/etc/init.d/rc.sysinit`, `rcS`: Startup Script
`src/.gitignore`: Ignore the tmp filesystem
`scripts/ld.script`: Linker Script
`scripts/Make.defs`: Milk-V Duo S Makefile
`src/Makefile`: Milk-V Duo S Makefile
`Kconfig`: Milk-V Duo S Config
`configs/nsh/defconfig`: Build Config for `milkv_duos:nsh`
Updated Documentation:
`platforms/risc-v/sg2000/index.rst`: New page for SOPHGO SG2000 SoC
`platforms/risc-v/sg2000/boards/milkv_duos/index.rst`: Building and booting NuttX for Milk-V Duo S
This PR adds support for the SOPHGO SG2000 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for Milk-V Duo S SBC.
Most of the code was derived from NuttX for Ox64 BL808. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-sg2000
Modified Files in arch/risc-v:
`Kconfig`: Added ARCH_CHIP_SG2000 for SG2000 SoC
New Files in arch/risc-v:
`include/sg2000/chip.h`: SG2000 Definitions
`include/sg2000/irq.h`: External Interrupts
`src/sg2000/chip.h`: Interrupt Stack Macro
`src/sg2000/sg2000_allocateheap.c`: Kernel Heap
`src/sg2000/sg2000_head.S`: Linux Header and Boot Code
`src/sg2000/sg2000_irq.c`: Configure Interrupts
`src/sg2000/sg2000_irq_dispatch.c`: Dispatch Interrupts
`src/sg2000/sg2000_memorymap.h`: Memory Map
`src/sg2000/sg2000_mm_init.c`, `sg2000_mm_init.h`: Memory Mgmt
`src/sg2000/sg2000_pgalloc.c`: Page Allocator
`src/sg2000/sg2000_start.c`: Startup Code
`src/sg2000/sg2000_timerisr.c`: Timer Interrupt
`src/sg2000/hardware/sg2000_memorymap.h`: PLIC and UART Base Address
`src/sg2000/hardware/sg2000_plic.h`: PLIC Register Addresses
`src/sg2000/Kconfig`: SG2000 Config
`src/sg2000/Make.defs`: Makefile
There is no need to use kernel build for S-mode all the time. As cpu
scratch is supported for non kernel mode build, it is possible to use
flat build for S-mode.
Add flat build support for risc-v S mode.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
This applies uintreg_t in risc-v commons and fixes araised ci issues
for multiple devices. The FLAT build runs on qemu-rv64ilp32 target.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This adds support of rv64ilp32 toolchain available from Github repo
`ruyisdk/riscv-gnu-toolchain-rv64ilp32`. With this 32-bit nuttx can
be generated for RV64 devices.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
* arch/risc-v/src/common/Toolchain.defs
arch/xtensa/src/lx6/Toolchain.defs
arch/xtensa/src/lx7/Toolchain.defs
- Define SHMODULEFLAGS etc. for sotest/dynload
- Add --entry=__start to SHMODULEFLAGS
* boards/arm64/qemu/qemu-armv8a/scripts/Make.defs
boards/sim/sim/sim/scripts/Make.defs
- Define SHMODULEFLAGS etc. for sotest/dynload
For newer devices, IDF bootloader is not supported because the
devices are able to boot directly into NuttX or use MCUBoot to
enable OTA and security features.
This commit enables users to select the legacy bootloader (IDF
bootloader) in `menuconfig` directly. Please note, that this is a
legacy option intended to support devices already deployed and it
isn't recommended for new designs.
*Note:* ldmd2 is ldc2-wrapper, allow using dmd frontend flags.
This support may be extended to gdc (gnu) if nuttx developers demand it
or are interested in it.
Check return value of mpfs_board_pmp_setup() and
jump to mpfs_board_pmp_error() in case of error.
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
Add the address alignment to keep the constraint of ARMv7-M architecture same as RAM vector.
ARMv7-M architecture describes the vector table address alignment as following.
The Vector table must be naturally aligned to a power of two
whose alignment value is greater than or equal to (Number of Exceptions supported x 4),
with a minimum alignment of 128 bytes.
I wonder why the implementation of arm_vectors.c does not follow
this constraint of address alignment about ARMv7-M architecture.
Although RAM vector is taken care about it.
I think, as the result it was done by linker script on each board.
At our system, NuttX will be started by bootloader.
To fix the address of entry point(__start) I set the address of entry point to beginning of binary,
so the beginning of binary is not a vector table.
At this case, keeping the address alignment constraint of arm_vectors.c is needed.
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.
This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s2 targets and removes the need
for running 'make bootloader' command for it.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
Cache the next timeout value in the drivers instance and update the mtimecmp value once. This is advantageous as the opensbi ecall to set the timer is expensive in systems which don't have the supervisor mode timer extension.
This patch changes how user service calls are executed:
Instead of using the common interrupt logic, execute the user service
call directly.
Why? When a user makes a service call request, all of the service call
parameters are already loaded into the correct registers, thus it makes
no sense to first clobber them and then reload them, which is what the
old logic does. It is much more effective to run the system call directly.
During a user system call the interrupts must be re-enabled, which the
new logic does as soon as we know the exception is a user service call
request.
This patch does NOT change the behavior of reserved system calls (like
switch_context), only the user service call request is affected.
Also, convert the type to union; we don't need the list element once
the item has been popped from the free list (the linkage is never needed
when the item is in use).
This provides an alternate tickless scheduling method, which uses the riscv
mtimer as a timebase, allowing the time and timeh registers to used
throughout an application.
The exiting tickless method, using Litex's timer0 has been left in place, as
it is a more performant option, but currently has the potential issue
identified in #11189.
when repeatedly enabling and disabling string-controlled configurations,
the generated toolchain configuration may be incorrect.
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
Embedded flash can have user signature area on SAMv7. This is a 512
bytes large page whose data are not erased by asserting ERASE pin or by
software ERASE command.
This commit adds arch to board interface for this area. It is possible
to perform read, write and erase operation. SAMV7_USER_SIGNATURE option
has to be set in the configuration.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
By default U(S)ART clocks are enabled in sam_lowput.c but
configuration check from sam_config.h may override USART configuration
and prevent clocks from been enabled.
This commit fix inconsistency in U(S)ART pinmux and clock configuration
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
This is to fix issue in [this log](https://github.com/apache/nuttx/actions/runs/9173629303/job/25222879619):
```
Configuration/Tool: esp32c3-generic/twai esp32c6-devkitm/twai esp32c6-devkitc/twai esp32h2-devkit/twai
Error: common/espressif/esp_twai.c:242:7: error: variable 'ret' set but not used [-Werror=unused-but-set-variable]
```
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Search and replace ARCH_BOOT_EL3 with more generic
ARCH_ARM64_EXCEPTION_LEVEL that holds the EL level
in an integer variable.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This provides a capable bootloader that may be run from OCRAM.
The OCRAM contains regions that are always zero, so the linker
file avoids those with best effort.
iMX9 infrastructure expects:
- 0x20480000 (Start of OCRAM, AHAB)
- 0x2049a000 (NuttX or SPL)
- 0x204e0000 (ARM Trustzone, not used)
When started from SD-card, the offsets are:
- 0x1f000 with AHAB
- 0xa000 without AHAB
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Value 1021, when read from ICC_IAR0_EL1 means:
"The GIC returns this value in response to a read of ICC_IAR0_EL1 or ICC_HPPIR0_EL1 at EL3,
to indicate that the interrupt being acknowledged is one which is expected to be handled at
Non-secure EL1 or EL2. This INTID is only returned when the PE is executing at EL3 using
AArch64 state, or when the PE is executing in AArch32 state in Monitor mode."
When this happens:
- FIQ is fired on group0
- IRQ is pending at group1
So simply check and handle the interrupt. In short, this provides interrupt support for
EL3.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This provides means to run NuttX completely in EL3. This may
be useful with NuttX based bootloaders that are executed from
OCRAM. Instead of SPL/U-boot combo, NuttX may replace SPL
completely.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
By default, submodules are cloned with `--depth=1`. This continues
to be true if `DISABLE_GIT_DEPTH` environment variable is not
defined (and it is not defined by default). But, if defined the
submodules will be fully cloned (without the `--depth` parameter).
The original names are confusing; the symbols' addresses point to the start and end of the
sbi executable ram area. This may also reside in l2lim and not in ddr, depending on the
configuration, and this is defined in the linker script.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
We can save execution time by
inline arm64_fullcontextrestore and arm64_switchcontext
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commits replicates some changes on files that were originally
written for other Espressif SoCs and inspired new implementations.
Eventually, these new implementations were improved and this commit
replicates these changes on the original sources.
Avoid using static mutex and recursive mutex as the resource to be
acquired/release. Instead, create a specific lock for each call if
it does not exist.
It seems like a wrong copy-and-paste from esp32c3.
Actually, internal memory mapping varies among processors.
esp32s3: lightly tested with wamr aot
esp32s2: not tested (i have no hardware access)
The bc022f8cd8 introduces a static way to calculate idle stack
address for risc-v platform. However, it uses the reverse order
to access idle stack, which breaks boards with smp configuration.
Correct the idle stack order of g_cpux_idlestack.
Fixes: bc022f8cd8 ("arch/risc-v: unify idle stack calculation")
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
As all the board allocate idle stack from _ebss. The idle stack
layout is fix and can be computed directly by using _ebss. There
is no need to use g_cpux_idlestack array anymore, remove it.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
As the stack layout is unified, it is possible to
use a unify formula to calculate the top of idle
stack.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
chip/s698pm_cpustart.c: In function 's698pm_cpu_boot':
Error: chip/s698pm_cpustart.c:74:17: error: unused variable 'tcb' [-Werror=unused-variable]
struct tcb_s *tcb = this_task();
^~~
cc1: all warnings being treated as errors
make[1]: *** [Makefile:99: s698pm_cpustart.o] Error 1
make[1]: Target 'libarch.a' not remade because of errors.
make: *** [tools/LibTargets.mk:164: arch/sparc/src/libarch.a] Error 2
make: Target 'all' not remade because of errors.
/github/workspace/sources/nuttx/tools/testbuild.sh: line 370: /github/workspace/sources/nuttx/../nuttx/nuttx.manifest: No such file or directory
Normalize s698pm-dkit/smp
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Make channels synchronous (i.e. share the same timebase) with the help
of SAMV7_PWMx_CHy_SYNC defines. All the channels share the same
timebase of channel 0, so this channel must be defined too.
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
ESP32 SoC use a static allocated array as idle stack. To fit
the existed idle stack allocation, make idle stack allocated
from ebss for the whole esp32 series.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Optimal size of granule is 64B (the dcache line size).
We can use it now as we don't have max. 32 granules limitation anymore.
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
This adds SBI specfication v0.3 based `riscv_sbi_system_reset()` to
support SBI firmware based system reset in kernel mode.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
1. Adjust code to avoid PM wakelock->count less than or equal to 0.
2. Fix some document format issues.
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
Although almost all board support allocating idle stack after ebss,
bl602 have a different memory layout for idle stack. To unify them,
make idle stack allocated from ebss for bl602.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
NuttSBI have a simple ecall interface for the kernel, which make
it hard to add new SBI call for NuttSBI. So implement standard
ecall interface for NuttSBI and make life easier.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
With CONFIG_MMCSD_MULTIBLOCK_LIMIT not set. (No limit)
The DMA driver would overwrite the internal buffer.
By adding CONFIG_ARCH_HAVE_SDIO_PREFLIGHT and
CONFIG_FAT_DMAMEMORY we can insure alignment and
maximize performance using no CONFIG_MMCSD_MULTIBLOCK_LIMIT
Using user allocated buffers for DMA transfers is not safe for two reasons:
- User space memory is virtual memory, DMA needs physical memory
- User memory buffer alignment cannot be guaranteed -> cache line ops
are not safe
Add a simple allocator for DMA safe memory. It will provide contiguous
blocks of memory with D-Cache line size alignment.
NOTE: The optimal granule size is the D-Cache line size (64), but due
to restrictions in the granule allocator this would result in a maximum
block size of 2K only, thus use 256B granules instead givin 8K max block
size.
Once the granule allocator is fixed this limitation can be removed.
Option CONFIG_SENSORS_QENCODER might be configured even if SAMv7 qencoder
over timer counter is not used (for example encoder over GPIO is selected
with CONFIG_SAMV7_GPIO_ENC). This can cause compile warnings, also build
of sam_qencoder.c file is unnecessary in that case.
New hidden option CONFIG_SAMV7_QENCODER is added and automatically
selected if at least one timer counter is enabled for qencoder. Build
is triggered on this option.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
PWMx_CHy_LONLY options have been added to Kconfig, too.
If LONLY is selected, it's not possible to use complementary outputs.
If LONLY is not selected, it's possible to use H or complementary
output. If configured correctly with cpol and dcpol attributes,
a H-like behaviour can be achieved. May be useful when you run out
of free MCU pins.
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
The qemu-rv use a small init code for M mode in kernel build.
It is hard-coding and is difficult to change. Due to the fact,
introduce a already mature SBI implement (e.g OpenSBI) to
replace existing code is a better choice.
This patch introduce some change for qemu-rv:
1. use SSTC to provide time interrupt in kernel build
2. remove uncessary M mode trap.
For simplicity, this patch does not add support for booting
nuttx for any core, but force boot core to start core 0 and
let core 0 do the initialization.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
SSTC extension allows nuttx to implement S-mode timer directly,
which is useful for starting at S-mode.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
As `up_get_intstackbase` supports per cpu stack base, fix
the report value with the cpu specific one.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
It is misleading to allocate stack from static array and heap,
make all stack allocated from heap area.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
according to manual:
The FPU is not affected by any security configuration.
Thus, it appears as not present in PERIPHID[n].PERM
register located in the SPU
This patch adds definitions to support user space device mappings
that allows devices like frame buffer to be accessible from user
space in kernel mode.
The are mainly two changes:
- in `mm/`:
added vm_map_region(), vm_unmap_region() for drivers to do
device mapping easily.
- in `arch/`:
extended ARCH_SHM_NPAGES as user-space mapping region size.
decoupled ARCH_SHM_MAXREGIONS from region size calculations and
limit its usage only for SysV shm purposes.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This patch adds a way to configure PLL frequencies. The configuration is
given by board logic.
These values should only be modified by the bootloader, but we don't have
that yet so the flag is never activated.
The frequency LUT idea is not necessary as the PLL output can be calculated
by the CPU. It is better to do this as the clocks are set by the SPL (2nd
stage program loader) which means the NuttX payload would not have access
to such a LUT anyhow.
The mask PLL_DIV_RDIV_MASK is also fixed, as that was simply wrong.
Also add call to imx9_clockconfig (although it does not do anything yet).
In some special chipsets, multiple CPUs may be bundled in one hardware
thread cluster, which results in hartid and cpuindex not being exactly
the same. The new option will decouple Scratch-based Per-CPU storage
with S-Mode to distinguish the real cpu index.
Signed-off-by: chao an <anchao@lixiang.com>
RISC-V provided fetch-and-op style atomic primitives as they scale
to highly parallel systems better than LR/SC or CAS. A simple
microarchitecture can implement AMOs using the LR/SC primitives,
provided the implementation can guarantee the AMO eventually
completes. More complex implementations might also implement AMOs
at memory controllers, and can optimize away fetching the original
value when the destination is x0.
Signed-off-by: chao an <anchao@lixiang.com>
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Most of the functions used to describe the SoCs capabilities are
available for all Espressif's chips. This commit uses this set of
common functions and remove outdated functions that perform the
same operations in a chip level.
1. pm configuration demonstrates the use of power management present on the ESP32-S3.
2. You can use the pmconfig command to test the power management, for details look at
``Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst``
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
acpi_init() must be called early during boot, some system components may be
unavailable at this stage, so debug messages won't work
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
This driver supports both eDMA3 and eDMA4 (also referred to as DMA0 / DMA1
in some contexts..)
The IP blocks are almost identical, with sufficiently minor differences
to use them via a unified driver. The price is a great amount of code
obfuscation in the hardware description layer.
This fixes names of program entry and linker script files so that to
support building kernel mode apps using CMake and export package.
flat and protected mode should be the same as before.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
rsdp memory may be not mapped when provided from multiboot2 header.
For some reason the previous code worked on some machines.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
add simple ACPI parser for intel64.
For now RSDP signature can be found in BIOS legacy region or can be provided by multiboot2
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
In file included from common/addrenv.h:33,
from common/riscv_initialstate.c:36:
common/riscv_initialstate.c: In function 'up_initial_state':
common/riscv_internal.h:136:16: warning: declaration of 'regval' shadows a previous local [-Wshadow]
136 | uintptr_t regval; \
| ^~~~~~
common/riscv_initialstate.c:74:12: note: in expansion of macro 'READ_CSR'
74 | regval = READ_CSR(CSR_VLENB);
| ^~~~~~~~
common/riscv_initialstate.c:63:13: note: shadowed declaration is here
63 | uintptr_t regval;
| ^~~~~~
Signed-off-by: chao an <anchao@lixiang.com>
LLVM supports (to various degrees) a number of experimental extensions.
All experimental extensions have experimental- as a prefix. There is
explicitly no compatibility promised between versions of the toolchain,
and regular users are strongly advised not to make use of experimental
extensions before they reach ratification.
Fix compile error:
riscv64-unknown-elf-clang: error: invalid arch name 'rv64gcv_zfh_zvfh', requires '-menable-experimental-extensions' for experimental extension 'zvfh'
Signed-off-by: chao an <anchao@lixiang.com>
- Add ARCH_KVMA_MAPPING to guard kernel mapping.
- Set dependency from MM_KMAP to ARCH_KVMA_MAPPING, as per commit
70de321de3.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
icr is tested below with macros like GPIO_INT_LOWLEVEL et al. Those macros
are shifted left by GPIO_INTCFG_SHIFT, so the temporary icr variable
should not be shifted right.
The SAMV7's qencoder driver now supports the GETINDEX ioctl call
which does not reset the internal Timer/Counter and returns
the current position, position of the last index and the number
of captured indexes to a struct qe_index_s pointer. Because the
SAMV7's timers are 16bit, the extension to 32 bits must be done.
Select CONFIG_SAMV7_QENCODER_ENABLE_GETINDEX in the Kconfig to
enable this functionality.
This driver does not obey the instructions given in the ATSAMV7
2023 datasheet because the recommended trigger resets the internal
counter which is not desired. Instead, a capture into capture A
and capture B registers is used. This way if an event happens
(the rising edge of the index signal), the current counter's value
is captured.
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.
This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s3 targets and removes the need
for running 'make bootloader' command for it.
Other related fix, but not directly to Simple Boot:
- Instrumentation is required to run from IRAM to support it during
initialization. `is_eco0` function also needs to run from IRAM.
- `rtc.data` section placement was fixed.
- Provide arch-defined interfaces for efuses, in order to decouple
board config level from arch-defined values.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
Currently Simple Boot image have fixed 2 ROM segments and
2 RAM segments, then the parsing iterator must stop when all
ROM segments are found.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
- Add missing include guard
- Add missing C++ guard
- Fix the initialization ordering in IOMUX_PADCFG macro. Why ? Becaused of:
imx9_iomuxc.h:54:3: error: designator order for field 'iomux_padcfg_s::dsyreg' does not match declaration order in 'iomux_padcfg_s'
54 | }
|
The original assumption was that the interrupt numbers are divided
so that 16 pins from 1 port are handled by a single interrupt source.
So source 0 would handle pins 0-15 and source 1 would handle pins 16-31.
This assumption is wrong, each pin has two sources, thus there are two
interrupt lines for each pin.
The driver uses source 0, and leaves source 1 disabled.
According to the qemu source code, hw/arm/virt.c.
The secure memory of the ARM Virt board is [0xe000000~0xf000000]
and the non-secure memory is configured as [0x40000000~0xffffffff].
We made the following adjustments based on the above virt board configuration
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Using CSR name depends on compiler support heavily, but CSR
encoding does not have this problem. It also make it easy to
add new CSR support even if the compiler does not support.
Unify CSR access by using the CSR encoding macro.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
This patch adds more debug related CSR definitions
to arch/risc-v/include/csr.h.
These definitions are from the RISC-V Debug Specification
Version 1.0 rc1 (https://github.com/riscv/riscv-debug-spec).
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Extracting global variable information using scripts:
kasan_global.py:
1. Extract the global variable information provided by the -- param asan globals=1 option
2. Generate shadow regions for global variable out of bounds detection
Makefile:
1. Implement multiple links, embed the shadow area into the program, and call it by the Kasan module
Signed-off-by: W-M-R <mike_0528@163.com>
RTC data was not being correctly placed on RTC's memory data due to
linker issues. Also, the image's RTC memory segment was not being
properly parsed by the bootloader.
This is a high resolution PWM driver, utilizing one 16-bit Flex-IO timer for
generating PWM period and the rest of the timers to generate PWM duty cycles.
This means that the period has to be the same for every PWM generated from one
FLEXIO block, but this way we can get 16-bit resolution for the PWM signals.
For a typical IMX9 HW there are 8 timers for each Flex-IO block, which means
that by using this driver one can get 7 PWM outputs from one block.
This driver can be later extended to have configuration options to use all
8 channels per flex-io by either using 8+8 -bit timer (less resolution) or by
using an external trigger from an LPIT.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This commit implements the common RMT driver (already available for
the other Espressif's xtensa-based devices) for ESP32.
This allows us to have a proper separation between the lower and
upper-half drivers and use the 'ws2812' example to drive WS2812 RGB
LEDs.
1.
In file included from chip/stm32_rtc.c:31:
chip/stm32_rtc.c: In function 'rtchw_set_alrmar':
chip/stm32_rtc.c:761:11: warning: format '%x' expects argument of type 'unsigned int',
but argument 3 has type 'uint32_t' {aka 'volatile long unsigned int'} [-Wformat=]
761 | rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
| ^~~~~~~~~~~~~~~~~~
chip/stm32_rtc.c:761:25: note: format string is defined here
761 | rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
| ~~~^
| |
| unsigned int
| %08lx
2.
arm-none-eabi-ld: staging/libdrivers.a(userled_lower.o): in function `userled_setled':
drivers/leds/userled_lower.c💯 undefined reference to `board_userled'
Regression:
stm32h7/linum-stm32h753bi: add support to leds
Signed-off-by: chao an <anchao@lixiang.com>
