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18813 Commits

Author SHA1 Message Date
Xiang Xiao
c96c96a399 drivers: Merge the common driver initialization into one place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-13 11:24:48 -03:00
Xiang Xiao
ea614090cd arch/risc-v: Change hex number to low case in csr.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-13 10:17:25 +02:00
Xiang Xiao
f94093bc2e arch/ceva: Move the idle stack initialization to up_initial_state 
to follow other arch's implementation

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-13 00:28:05 +02:00
Xiang Xiao
1a7f49eeb3 arch/z[80|16]: Move up_getsp declaration to arch.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 19:21:59 +02:00
Gustavo Henrique Nihei
7ede285cfe xtensa/esp32s3: Add support for RT-Timer based on Systimer peripheral 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-12 15:27:30 +02:00
Gustavo Henrique Nihei
86b18bd6e9 xtensa/esp32s3: Move code documentation to the correct place 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-12 11:53:14 +08:00
Gustavo Henrique Nihei
a4db4031c9 xtensa/esp32s3: Stall Systimer when core 1 is temporarily stalled 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-12 11:53:14 +08:00
Xiang Xiao
39fb09738d arch: Move [arm|xtensa]_intstack_[alloc|top] to common header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-11 23:08:07 +02:00
Xiang Xiao
17d1a48fc9 arch: Remove up_puts prototype from up_inernal.h 
since it's defined in include/nuttx/arch.h now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-11 23:08:07 +02:00
Jukka Laitinen
d9607f71d2 Revert "arch/risc-v: Correct FPU register save area in riscv_copystate" 
This reverts commit 86358bff3bc814efb564a4427b4bcd6c3c91dbf0.
 2022-03-11 23:43:41 +08:00
Petro Karashchenko
fc9e2d272e arch/arm/arm[-a|-r]: fix typos in comments 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-11 11:08:01 +08:00
Gustavo Henrique Nihei
c8796c1bc2 xtensa/esp32s3: Move SPI RAM configuration out of Peripheral menu 
Menu for configuration of SPI RAM was wrongly placed inside the menu
for peripheral selection.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-11 11:05:24 +08:00
Abdelatif Guettouche
f0a5777a26 xtensa_swint.c: Restore the coprocessor state at the end for consistency. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-11 02:23:09 +02:00
Abdelatif Guettouche
7c57739d1d xtensa_exit.c: Co-processor state is restored as part of the 
SYS_Restore_context call, no need to call it separately.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-11 02:23:09 +02:00
Abdelatif Guettouche
71ba4a6b76 arch/xtensa: Use the software interrupt when saving context too. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-11 02:23:09 +02:00
Abdelatif Guettouche
329db99e51 arch/xtensa: Use rsync around manipulating interrupt registers and 
replace `isync` by `rsync` in other places.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-11 02:23:09 +02:00
Jukka Laitinen
81a19c1ce8 arch/riscv/src/mpfs: Make cleaner pinmux configurations for USB 
Mux USB IO pins one-by-one using package specific pinmux definitions. This avoids accidentally overwriting IO settings for other pins.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-03-11 00:22:43 +02:00
Xiang Xiao
c0f3ac97bc arch/risc-v: Update opensbi to 4998a712b2ab504eff306110879ee05af6050177 
include theis commit:
commit 6ad8917b7e27e5e80fb9268492b9111b17ed2024
Author: Petro Karashchenko <petro.karashchenko@gmail.com>
Date:   Fri Jan 28 09:13:23 2022 +0200

    lib: fix compilation when strings.h is included

    In a systems that provide strings.h and it is included
    together with sbi_bitops.h the compilation error appears.
    The ffs() and fls() are provided by strings.h

    Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
    Reviewed-by: Anup Patel <anup@brainfault.org>

and fix this warning:
Error: include/sbi/sbi_bitops.h:47:19: declaration of 'ffs' shadows a built-in function
 static inline int ffs(int x)
                   ^~~

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-10 19:46:01 +02:00
Xiang Xiao
29cb85ba17 arch/stm32: Fix compiler warning 
chip/stm32_i2s.c:1949:12: error: conflicting types for built-in function 'roundf'; expected 'float(float)' [-Werror=builtin-declaration-mismatch]
 1949 | static int roundf(float num)
      |            ^~~~~~

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-10 19:46:01 +02:00
Xiang Xiao
a07dc2363e c5471/c5471_irq.c: Fix error: '__builtin_memcpy' forming offset [4, 31] is out of the bounds [0, 4] of object '_svectors' with type 'int' 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-10 19:46:01 +02:00
Huang Qi
8267a76186 arch/risc-v: Implement SYS_save_context in swint 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-10 16:11:14 +08:00
Huang Qi
7022c630fe arch/risc-v: Correct FPU register save area in riscv_copystate 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-10 16:11:14 +08:00
Alan C. Assis
dc1b6776b9 xtensa/esp32s3: Add SPI RAM/PSRAM Support 2022-03-09 19:22:56 +02:00
Huang Qi
69cfe8d626 arch/arm: Support setjmp/longjmp for all socs 
After check the official specification of ARM ISA
and Thumb ISA, the arch_setjmp_thumb.S are written
by arm unified assembly language,
so it easy to make it works for ARM and thumb ISA.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-09 17:13:21 +02:00
Eero Nurkkala
a21a396bd8 risc-v/mpfs: usb: apply review fixes 
PR#5688 review fixes are in this patch. The PR was already
merged so the fixes are addresses here as a separate patch.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-03-09 10:26:56 +02:00
chao.an
ba2cb65a91 arch/sim: add all symbols support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-09 10:16:54 +02:00
Huang Qi
c6e636a871 arch/risc-v: Save/Load float register in setjmp 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-09 10:15:54 +02:00
Huang Qi
8dedf1d9af arch/risc-v: Correct handling of QPFPU and DPFPU 
If QPFPU enabled we will never enter the expected QPFPU branch since
option QPFPU depend on DPFPU.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-09 10:15:54 +02:00
Gustavo Henrique Nihei
4a29fa903b xtensa/esp32s3: Enable SMP support 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-09 10:42:50 +08:00
Richard Tucker
4888be37e3 arch/arm/src/sam34/sam_dmac.c: Fix compilation error 2022-03-09 10:18:32 +08:00
Gustavo Henrique Nihei
140dc248db xtensa/esp32s2: Add support for Main System Watchdog Timers 
Support for RTC Watchdog Timer is currently in place, but not yet
functional due to not yet implemented RTC driver.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-08 22:24:07 -03:00
Eero Nurkkala
4b2fbab998 risc-v/mpfs: usb: fix an unused variable warning 
Fix an unused variable warning if the CONFIG_HAVE_USBTRACE
(and USB_DEBUG) aren't set.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-03-08 23:00:31 +08:00
Gustavo Henrique Nihei
bd7ee0d675 xtensa/esp32s2: Sync IRQ management API with ESP32 and ESP32-S3 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-08 11:36:32 -03:00
Huang Qi
bfedbf1c05 arm/imx6: Enable setjmp test in ostest 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-08 21:00:29 +08:00
Huang Qi
cfff115f21 arm: Move setjmp to common place 
Since some Cortex A core supports thumb mode also,
thus they can share same implementation.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-08 21:00:29 +08:00
Eero Nurkkala
8c1ab129ac risc-v/mpfs: add USB device driver 
This adds a simple USB device driver for the mpfs. However,
this driver is still at its early phase. Only limited testing
with CDC/ACM has been conducted.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-03-08 16:49:29 +08:00
zhuyanlin
634d337394 riscv/xtensa: corrent dumpstate xcp size 
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-03-08 10:14:04 +02:00
chao.an
a14ed02571 sim/syscall: add syscall note support in the flat build 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-07 23:58:28 +08:00
zhuyanlin
981282696f xtensa:backtrace: fix backtrace last buffer error in some scene 
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-03-07 10:21:37 +01:00
Abdelatif Guettouche
fa0e5da18e xtensa/xtensa_user_handler.S: Store EXCCAUSE and EXCVADDR into the user 
frame. The user frame is passed them to xtensa_user that actually uses
EXCVADDR.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-04 11:19:06 +02:00
Juha Niskanen
779665c704 arch/arm/src/stm32l4: STM32L4+ might need flash data cache corruption workaround 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2022-03-04 14:00:20 +08:00
Oleg Evseev
625d230d28 arch/arm/src/stm32f7/stm32_can.c: fix CAN3 receiving 
by fixing filter initialization.

STM32F7 CAN3 works in single peripheral configuration and there is only 14 filter banks: 0-13. Previously not available 14 indexed filter (CAN_NFILTERS/2) was wrongly used for for receiving to FIFO. Now zero indexed filter is correctly used instead.
 2022-03-03 14:31:37 -03:00
Abdelatif Guettouche
c820085a23 arch/xtensa/esp32s3: Add encrypted support for SPI FLASH. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-03 19:57:59 +08:00
Abdelatif Guettouche
9d5b13cd0e xtensa/esp32s3: Add SPI-Flash support. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-03 19:57:59 +08:00
Huang Qi
e383439dda risc-v: Replace all inline assembly with macro 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-03 19:55:54 +08:00
Huang Qi
35330a798b risc-v: Implement READ_AND_SET_CSR for CSR operate 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-03 19:55:54 +08:00
zhuyanlin
5af1b671b6 armv7-a/armv7-r:cache: modify hardcode in cache set/way operation 
Some chip not use the default cache size & way , read from
CCSIDR instead of hardcode.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-03-03 14:11:31 +08:00
Gustavo Henrique Nihei
16030f713e xtensa/esp32s3: Add support for Free-running Timer 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-03 10:58:53 +08:00
Gustavo Henrique Nihei
3b7a6ae311 xtensa/esp32s3: Add support for Tickless kernel using Systimer 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-02 18:08:44 +01:00
ligd
fe6aa4a874 sim: add loop thread to handle dev loops 
For some dev loops will call sem_wait/sem_trywait

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-02 20:29:52 +09:00