If a board.h provides BOARD_SIM_CLKDIV2_FREQ it will configure the
SIM_CLKDIV2 based on the additional provided
BOARD_SIM_CLKDIV2_USBFRAC and BOARD_SIM_CLKDIV2_USBDIV
The reason for doing this globaly is that the output the
SIM_CLKDIV2 divisor may be also used for other IP blocks in
future configurations (as is done for SIM_CLKDIV3)
A board.h file can now specify the:
1) BOARD_SOPT2_PLLFLLSEL to select the output of the SIM_SOPT2 MUX
from:
MCGFLLCLK
MCGPLLCLK
USB1PFD
IRC48MHZ
2) If it defines BOARD_SIM_CLKDIV3_FREQ then it must define
BOARD_SIM_CLKDIV3_PLLFLLFRAC and BOARD_SIM_CLKDIV3_PLLFLLDIV
which wil be used to cpnfigure SIM_CLKDIV3 [PLLFLLFRAC, PLLFLLDIV]
Allow for complete MCG_C2 definition from the boart.h file
Moved #ifdef out of code by setting default values for
Allow for individule bit setting in MCG_C2 for
BOARD_EXTCLOCK_MCG_C2
BOARD_MCG_C2_FCFTRIM
BOARD_MCG_C2_LOCRE0
Added range and sanity checking
The High Gain bit in MCG_C1 was preventing teensy from booting
except after a programming session. The second change doesn't appear
to change any functionality, but complies with restrictions in the k20
family reference manual on FEI -> FBE clock transiions.
