Commit Graph

4 Commits

Author SHA1 Message Date
David Sidrane
d31214aa25 stm32h7:ADC STM32_RCC_D3CCIPR_ADCSEL->STM32_RCC_D3CCIPR_ADCSRC 2023-12-07 03:50:40 -08:00
raiden00pl
ae6067fb29 boards/stm32h7: HCLK and ACLK are delivered from SYSCLK not CPUCLK 2023-08-14 23:40:46 +08:00
Alexander Lunev
73867b9759 boards/arm/stm32h7/stm32h745i-disco: supported external SDRAM
Supported external SDRAM (MT48LC4M32B2B5-6AIT:L) on STM32H745I-DISCO dev board.
Though MT48LC4M32B2B5-6AIT:L SDRAM itself provides 32-bit data bus, STM32H745I-DISCO board
routes only DQ[15:0] bits. Thus only half of the memory can be accessed: the accessible memory
configuration is only 1 Meg x 16 x 4 banks instead of 1 Meg x 32 x 4 banks.
Thus the accessible memory size is 8 MBytes.

Testing:
nsh> ramtest -a 0xD0000000 -s 8388608
RAMTest: Marching ones: d0000000 8388608
RAMTest: Marching zeroes: d0000000 8388608
RAMTest: Pattern test: d0000000 8388608 55555555 aaaaaaaa
RAMTest: Pattern test: d0000000 8388608 66666666 99999999
RAMTest: Pattern test: d0000000 8388608 33333333 cccccccc
RAMTest: Address-in-address test: d0000000 8388608
nsh>
2023-08-12 18:18:23 +08:00
raiden00pl
f43c7e99be boards/stm32h7: Add stm32h745i-disco board 2023-07-12 11:30:57 -03:00