Commit Graph

1727 Commits

Author SHA1 Message Date
ouyangxiangzhen
733a68002c arch/riscv: Fixed hardware timer warps-around issue
This commit fixed the issue where the hardware timer wraps around and causes the system to halt.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-09-14 00:07:13 +08:00
hujun5
908df725ad arch: use up_current_regs/up_set_current_regs replace CURRENT_REGS
reason:
1 On different architectures, we can utilize more optimized strategies
  to implement up_current_regs/up_set_current_regs.
eg. use interrupt registersor percpu registers.

code size
before
    text    data     bss     dec     hex filename
 262848   49985   63893  376726   5bf96 nuttx

after
       text    data     bss     dec     hex filename
 262844   49985   63893  376722   5bf92 nuttx

size change -4

Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-13 23:18:58 +08:00
liaoao
512a496467 riscv_mtimer: modify riscv_mtimer_current to reduce precision lost
Signed-off-by: liaoao <liaoao@xiaomi.com>
2024-09-13 08:55:00 +08:00
Martin Vajnar
1fa4e61230 espressif: Add Quadrature Encoder driver (using PCNT)
Signed-off-by: Martin Vajnar <martin.vajnar@gmail.com>
Co-authored-by: Pavel Pisa <pisa@fel.cvut.cz>
2024-09-13 01:49:28 +08:00
ligd
6a2c03732f clock: Replace all ts and tick conversion functions
Using the ts/tick conversion functions provided in clock.h

Do this caused we want speed up the time calculation, so change:
clock_time2ticks, clock_ticks2time, clock_timespec_add,
clock_timespec_compare, clock_timespec_subtract... to MACRO

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-12 18:14:39 +08:00
Stuart Ianna
779d4af3e9 arch/risc-v/src/litex: Claim all pending PLIC interrupts.
Attempt to service all interrupts pending in the PLIC's claim register. Ideally, this is more efficient than switching context for each interrupt received.
2024-09-12 15:06:04 +08:00
Stuart Ianna
29ee9aacb3 arch/risc-v/common: provide architecture specific perfmon bindings.
Provides two implementations:
 - CSR_CYCLE: Cores which implement hardware performance monitoring.
 - CSR_TIME: Uses the machine time registers.

Using the up_perf_xx bindings directory is more efficient than performing a nanosecond conversion on every gettime event.
2024-09-12 15:04:02 +08:00
Huang Qi
fc5a029e44 riscv: Unify the extended context save/restore
This patch unifies the extended context save/restore for RISC-V,
allowing the customized context save/restore to be used, for example,
the extended context in rv32m1.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-09-11 19:50:07 +08:00
Tiago Medicci Serrano
f063e47c28 espressif: Update external libraries to fix GPIO interrupt bug
This commit updates the HAL version used by NuttX to fix the bug
reported in https://github.com/apache/nuttx/issues/13303
2024-09-11 09:05:45 +08:00
hujun5
1aab457b4c sched:add parameters to restore_critical_section
reason:
In SMP, when a context switch occurs, restore_critical_section is executed.
To reduce the time taken for context switching, we directly pass the required
parameters to restore_critical_section instead of acquiring them repeatedly.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-10 23:14:09 +08:00
Stuart Ianna
f69a62583c arch/risc-v/src/litex: Update parameter to match new register typedef.
This silences the warning produced after the uintreg_t definitions was introduced in 8ebc3aa9e8.
2024-09-10 14:03:16 +08:00
Stuart Ianna
f96370700e arch/risc-v/src/litex/litex_serial: Fix build warning after inline spinlock change.
Resolves regression introduced in a4fece3450.
2024-09-10 14:03:16 +08:00
meijian
a7224cf35a net/netstatistics: add tx/rx bytes statistics for dev
We can see them in ifconfig:

ap> ifconfig
wlan0   Link encap:Ethernet HWaddr 42:64:7f:b3:12:03 at UP mtu 1500
        inet addr:10.0.1.2 DRaddr:10.0.1.1 Mask:255.255.255.0
        inet6 DRaddr: ::

        RX: Received Fragment Errors   Bytes
            00000b9b 00000000 00000000 21daf5
            IPv4     IPv6     ARP      Dropped
            00000a33 00000137 00000031 00000000
        TX: Queued   Sent     Errors   Timeouts Bytes
            00000ac4 00000ac4 00000000 00000000 1a2103
        Total Errors: 00000000

Signed-off-by: meijian <meijian@xiaomi.com>
2024-09-10 11:36:03 +08:00
hujun5
608b59e401 smp: enable smp_call in all smp arch
reason:
In subsequent implementations, we will replace up_cpu_pause with smp_call.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-06 07:11:38 +09:00
hujun5
198630a809 sched: use this_task replace nxsched_self
reason:
We can reduce a function call to improve performance.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-05 09:33:50 -03:00
fangxinyong
7b05a550dc sched: replace up_cpu_index with this_cpu
Make this_cpu is arch independent and up_cpu_index do that.
In AMP mode, up_cpu_index() may return the index of the physical core.

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
2024-09-05 12:09:24 +08:00
hujun5
433f159c06 arch: remove unused up_cpu_pausereq waiting
reason:
After the up_cpu_pause call completes, it guarantees that other CPUs have fully stopped.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-05 07:15:54 +09:00
Yanfeng Liu
7bd857c9f1 Revert "arch/riscv: unify in-kernel syscall"
This reverts commit 6986cd4105 as it breaks critical section as in
https://github.com/apache/nuttx/pull/12864#issuecomment-2325779041
2024-09-04 09:47:49 -03:00
Tiago Medicci Serrano
c72c66fff8 espressif: Fix deadlock in RT timer caused by critical section
This commit fixes a deadlock in `esp32s3-devkit:sta_softap`
defconfig: `spin_lock_irqsave` was being used to enter a critical
section that calls `nxsem_post`. In this case, it's recommended
to use `[enter|leave]_critical_section` to avoid deadlocks when a
context switch may happen, for instance.
2024-08-30 17:00:51 -03:00
Tiago Medicci Serrano
a916de0e14 espressif: Update HAL library reference to include debug assert
During the board bringup, the new HAL reference includes an assert
to check if the critical section flags is being stored as expected.
2024-08-30 21:41:47 +08:00
yangsong8
5a39e83c05 usbdev: extend the usb req len to size_t
Some USB controllers can receive or send multiple data packets then
generate one interrupt. This mechanism can reduce the number of data
copies. Extend req buf to accommodate this.

Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
2024-08-30 01:32:02 +08:00
Lup Yuen Lee
4c35bde3ba risc-v/bl808: Configure MMU to cache User Text, Data and Heap
This PR configures the BL808 MMU to cache the the User Text, Data and Heap. We enable the T-Head MMU Flags for Shareable, Bufferable and Cacheable, as explained in the previous PR: https://github.com/apache/nuttx/pull/13199

This PR fixes the Slow Memory Access for NuttX Apps on Ox64 BL808 SBC: https://github.com/apache/nuttx/issues/12696. With this fix, Ox64 NuttX CoreMark jumps from 19 to 1,104. (Close to Buildroot Linux CoreMark)

Modified Files:

`arch/risc-v/Kconfig`: Enabled `ARCH_MMU_EXT_THEAD` for BL808 SoC.
2024-08-28 13:47:41 +08:00
Lup Yuen Lee
b14dc8f8ae risc-v/mmu: Configure T-Head MMU to cache User Text, Data and Heap
This PR configures the T-Head MMU to cache the the User Text, Data and Heap. We enable the MMU Flags for Shareable, Bufferable and Cacheable, as explained in this article: https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906

This PR fixes the Slow Memory Access for NuttX Apps on BL808 and SG2000 SoCs: https://github.com/apache/nuttx/issues/12696. With this fix, SG2000 NuttX CoreMark jumps from 21 to 2,423. (Close to SG2000 Debian CoreMark)

We introduce a Kconfig Option: `ARCH_MMU_EXT_THEAD` ("System Type > Enable T-Head MMU extension support"). Enabling this Kconfig Option will configure the T-Head MMU to cache the User Text, Data and Heap.

This PR enables the MMU cache for only SG2000 SoC (Milk-V Duo S SBC). The next PR will apply the same settings to BL808 SoC (Pine64 Ox64 SBC).

Modified Files:

`arch/risc-v/Kconfig`: Added Kconfig Option `ARCH_MMU_EXT_THEAD` that will configure the T-Head MMU. Enabled `ARCH_MMU_EXT_THEAD` for SG2000 SoC.

`arch/risc-v/src/common/riscv_mmu.h`: Set the T-Head MMU Flags (Shareable, Bufferable and Cacheable) for User Text, Data and Heap, if `ARCH_MMU_EXT_THEAD` is enabled

`arch/risc-v/src/common/riscv_addrenv.c`: Extended the MMU Flags from 32 bits to 64 bits, to accommodate the T-Head MMU Flags

`arch/risc-v/src/common/riscv_exception.c`: Extended the MMU Flags from 32 bits to 64 bit, to accommodate the T-Head MMU Flags. This code is enabled only for MMU Paging (`CONFIG_PAGING`).
2024-08-27 19:54:58 -04:00
hujun5
1d6a099180 irq: remove restore_critical_section in irq
Only in the non-critical region, nuttx can the respond to the irq and not hold the lock
When returning from the irq, there is no need to check whether the lock needs to be released
we also need keep restore_critical_section in svc call

test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-08-25 21:14:19 +08:00
Petro Karashchenko
d499ac9d58 nuttx: fix multiple 'FAR', 'CODE' and style issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Petro Karashchenko
7b18f9d19f nuttx: add missing 'FAR' and fix style issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Petro Karashchenko
f40b09cbc9 style: remove redundant spaces
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Yanfeng Liu
634ee5b1f6 board/maix-bit: add cmake support
This adds initial CMake support for `maix-bit` device.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-24 11:08:25 +08:00
Matheus Catarino
93b520f7b0 swift6 embedded support 2024-08-23 09:02:20 +08:00
chenrun1
8e1a042eef nuttx/atomic.h:Fix missing type declarations at compile time
Summary:
  1.Modify the conditions for entering different include header files
  2.Added pre-definition for _Atomic _Bool when it is missing
  3.Added nuttx for stdatomic implementation. When toolchain does not support atomic, use lib/stdatomic to implement it

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-22 01:44:29 +08:00
Tiago Medicci Serrano
568917bfd2 espressif: Fix MCUboot build on RISC-V and unify linker script
This commit fixes building MCUboot on Espressif's RISC-V SoCs and
unify the associated linker scripts to make improve readability.
2024-08-21 23:28:45 +08:00
Tiago Medicci Serrano
5680e9d5a4 espressif: Update internal libraries reference
Update internal reference to get the most updated Espressif's
libraries. Those libraries are based on branch `release/v5.1` of
the ESP-IDF and include `v5.1.4` version of it.
2024-08-21 23:28:45 +08:00
hujun5
4cb419866f arch: inline up_testset in arm arm64 riscv xtensa
test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-08-21 01:45:10 +08:00
Filipe Cavalcanti
4d4d8a6ca5 arch/risc-v/esp32c3: fix AP password memcpy typo 2024-08-20 00:50:26 +02:00
Yanfeng Liu
3166c6d9c6 riscv/qemu-rv: add RPTUN cmake
This adds cmake support for RPTUN.
2024-08-19 19:53:03 +08:00
xuxin19
9fdd299d32 cmake:split the archive process to avoid parameter problems
refer to:https://cmake.org/cmake/help/latest/variable/CMAKE_LANG_ARCHIVE_APPEND.html

this will solve the problem of too long parameters
when executing ar in cygwin environment such as msys.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-18 23:26:01 +08:00
Yanfeng Liu
b9fde453ce riscv/qemu-rv: add RPTUN support
This adds initial RPTUN support for qemu-rv and rv-virt device.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-18 19:55:27 +08:00
Yanfeng Liu
2af5ad174f riscv/qemu-rv: add RPTUN Kconfig
This add RPTUN related Kconfigs for qemu-rv chip.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-18 19:55:27 +08:00
Eren Terzioglu
e11a53bec9 esp32[c3|c6|h2]: Add adjustable SPI clock speed 2024-08-17 13:43:58 +08:00
Tiago Medicci
69a8e2697f espressif: Fix default pins for SPI bus 2 on ESP32-[C3|C6|H2]
Fix the correct pin number for the SPI 2 bus on ESP32-C3, ESP32-C6
and ESP32-H2.
2024-08-17 13:43:58 +08:00
Eren Terzioglu
61dff51a33 esp32[c3|c6|h2]: Fix SPI clock issue 2024-08-17 13:43:58 +08:00
chenxiaoyi
7ce5241f0e types.h: fix windows build error
Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt.h(605,39): error C2371: 'wint_t': redefinition; different basic types
Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt.h(606,39): error C2371: 'wctype_t': redefinition; different basic types

Co-authored-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
Co-authored-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-14 22:36:57 +08:00
Yanfeng Liu
41dba46c1d arch/riscv: fix IRQ_SOFT for non-SMP
This fixes software interrupt number for non-SMP cases

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-14 20:59:52 +08:00
Yanfeng Liu
f5b2fc371e riscv/qemu-rv: use cluster PLIC/CLINT configs
This uses cluster speficic PLIC, CLINT and ACLINT devices in NuttX.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-12 20:43:05 +08:00
Yanfeng Liu
6db85498a2 riscv/qemu-rv: add cluster PLIC/CLINT configs
This adds cluster specific configs for PLIC, CLINT and ACLINT
devices.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-12 20:43:05 +08:00
yanghuatao
fecc5091af toolchain/ghs: Fix SP_DSB warnings
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
          argument to macro is empty
    SP_DMB();
           ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
          argument to macro is empty
    SP_DMB();
           ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 296: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-11 14:28:12 -03:00
Yanfeng Liu
47b0414eab arch/riscv: add cluster local hartid
Some multicore RV chips (mpfs, jh7110 etc) have hart clusters
and globally numbered mhartids. Clusters with single hart or
SMP support can be managed by one NuttX instance. Currently
NuttX expects to use cluster-local ids.

This allows us to get local ids by offsetting mhartids with a
base value.

Note that there are chips (e.g. k230) that use cluster-local
ids directly, so this is not needed for them.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-12 00:10:13 +08:00
Yanfeng Liu
46f4a24d59 riscv/qemu: add CMake for PROTECTED
This adds CMake support for PROTECTED build mode on rv-virt target.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-09 23:43:31 +08:00
Yanfeng Liu
01c37f7012 riscv/rv32m1: fix build issue
This exports `return_from_exception` symbol to fix build issue with
unified in-kernel syscall.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 21:25:59 +08:00
Yanfeng Liu
6986cd4105 arch/riscv: unify in-kernel syscall
This generalizes the in-kernel syscall approach from KERNEL mode to
all build modes so that to unify in-kernel syscall invocations.  As
a result, machine mode ECALL and the supervisor folder are no longer
needed.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 21:25:59 +08:00