When supporting high-priority interrupts, updating the
g_running_tasks within a high-priority interrupt may be
cause problems. The g_running_tasks should only be updated
when it is determined that a task context switch has occurred.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
In the init phase of the OS, arch_get_current_tcb return NULL. Enable
the memory backatrace default will crash in backtrace function.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
1. add lib_fork api in libs/libc, we need a fork() api to implement the
fork relative method, such as pthread_atfork
2. rename the assembly fork entry function name to up_fork(), and rename
the up_fork() to arch specific name, such as
sim_fork()/arm_fork()/mips_fork() etc.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
If -fstack-protector-all is enabled, gcc linker will need GCC
SSP(Stack Smashing Protector) support, Since the implement of SSP
is related to the OS, most of embedded toolchain does not provide
ssp support, so an error will be reported when linking:
enable CONFIG_LTO_FULL && CONFIG_STACK_CANARIES
arm-none-eabi/bin/ld: cannot find -lssp_nonshared: No such file or directory
arm-none-eabi/bin/ld: cannot find -lssp: No such file or directory
https://github.com/gcc-mirror/gcc/blob/master/gcc/gcc.cc#L983-L985
Since nuttx has already implemented SSP related hook functions,
so in this PR, we filter out this option in the link phase to ensure that
the implementation of lssp/lssp_nonshared will not be referenced
Signed-off-by: chao an <anchao@xiaomi.com>
1. as we can use fork to implement vfork, so we rename the vfork to
fork, and use the fork method as the base to implement vfork method
2. create the vfork function as a libc function based on fork
function
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Fix goldfish build toolchain math library error:
/mnt/yang/vela_Goldfish/nuttx/include/libcxx/cmath:454:9: error: 'nexttowardf' has not been declared in '::'
454 | using ::nexttowardf;
| ^~~~~~~~~~~
/mnt/yang/vela_Goldfish/nuttx/include/libcxx/cmath:472:9: error: 'acosl' has not been declared in '::'
472 | using ::acosl;
| ^~~~~
/mnt/yang/vela_Goldfish/nuttx/include/libcxx/cmath:473:9: error: 'asinl' has not been declared in '::'
473 | using ::asinl;
| ^~~~~
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
Summary:
- I noticed that arm64_gic_raise_sgi() is not implemented for
GICv2 which is used for SMP + hypervisor such as qemu + kvm.
- This commit fixes this issue
Impact:
- None
Testing:
- Tested with qemu-7.1 + kvm (linux) and qemu-7.1 + hvf (macOS)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that pcsi version can not be obtained with qemu + kvm.
- Also, pci_detect hangs with qemu + hvf.
- This commit fixes this issue by using hvc (hypervisor call).
Impact:
- None
Testing:
- Tested with qemu-7.1 + kvm (linux) and qemu-7.1 + hvf (macOS)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- During testing with qemu + kvm, I noticed that nuttx hangs
when setting cntfrq_el0. With qemu + kvm, it starts from
EL1 because we can not specify virtualization=on
- However, I noticed that it works without setting cntfrq_el0
- This commit fixes this issue
Impact:
- None
Testing:
- Tested with qemu-7.1 (both with kvm and without kvm)
- NOTE: to work with kvm, GICv2 must be used.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
In SMP mode, the fpu owner may switch from core0 to core1,
so it is necessary to force saving the FPU context when a
context switch occurs.
This PR fixed the crash issue mentioned in #8799.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Summary:
- I noticed that ./tools/configure.sh fvp-armv8r:nsh_smp shows
warning: (ARCH_CHIP_FVP_R52 && ARCH_CHIP_FVP_R82) selects ARMV8R_HAVE_GICv3 which has unmet direct dependencies (ARCH_ARM && ARCH_ARMV8R)
- I think ARMV8R_HAVE_GICv3 is only used for aarch32.
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with nsh_smp on FVP
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
armv8r and armv8a have different process affinity,
and sgi affinity needs to be able to adapt all of them.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Summary
For ARM64, it need to set IRQ type(EDGE or LEVEL). it's specific
for ARM64 PPI or SPI.
The change add arm64_gic_irq_trigger to set IRQ type
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary
add up_affinity_irq/up_trigger_irq/up_prioritize_irq for gicv3
these interface is necessary for some drivers
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
GICR_PWRR is a IMPLEMENTATION-DEFINED register for gc700/gc600, which
is following gic v3 and v4.
Please check GICR_PWRR define at TRM of GIC600/GIC700 for more detail
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
The compiler will optimize boot_early_memset to memset,
but memset in libc cannot be used before MMU is enabled.
Therefore, assembly language is used to implement the
initialization of bss to avoid this problem.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
When the MMU/MPU of core0 is enabled while those of other cores are not,
it is unsafe to operate the idle stack simultaneously. The idle stack
of other cores will be flushed by the contents in the cache of core0,
therefore it is necessary to initialize the idle stack and let each
core handle it on its own.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
to avoid the infinite recusive dispatch:
*0 myhandler (signo=27, info=0xf3e38b9c, context=0x0) at ltp/testcases/open_posix_testsuite/conformance/interfaces/sigqueue/7-1.c:39
*1 0x58f1c39e in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:167
*2 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*3 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:115
*4 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:435
*5 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*6 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*7 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*8 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:115
*9 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:435
*10 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*11 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*12 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*13 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:115
*14 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:435
*15 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*16 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*17 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*18 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:115
*19 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:435
*20 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*21 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*22 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*23 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:115
*24 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:435
*25 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*26 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*27 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*28 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:115
*29 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:435
*30 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*31 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Currently only Port UART0 is supported for Allwinner A64. This PR adds support for all UART Ports: UART1 to UART4. (Except R-UART, which is a special low-power UART)
This is required for the upcoming LTE Modem Driver (Quectel EG25-G) for PINE64 PinePhone, which uses UART3. [(Details here)](https://lupyuen.github.io/articles/lte2)
The code was adapted from the NuttX UART Driver for Allwinner A1X: [`a1x_serial.c`](https://github.com/apache/nuttx/blob/master/arch/arm/src/a1x/a1x_serial.c)
`arch/arm64/src/a64/a64_serial.c`: Added ports UART1 to UART4, based on [`a1x_serial.c`](https://github.com/apache/nuttx/blob/master/arch/arm/src/a1x/a1x_serial.c)
`arch/arm64/src/a64/a64_serial.h`: Added IRQs for UART1 to UART4. Moved UART Base Addresses to `a64_memorymap.h`
`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added UART Base Addresses for UART0 to UART4
`arch/arm64/src/a64/Kconfig`: Added UART1 to UART4 to Allwinner A64 Peripheral Selection menu
`boards/arm64/a64/pinephone/configs/lcd/defconfig`, `lvgl/defconfig`, `nsh/defconfig`, `sensor/defconfig`: Fixed `UART1_SERIAL_CONSOLE` to `UART0_SERIAL_CONSOLE`
compile error log:
common/arm64_arch_timer.c: In function 'arm64_tick_max_delay':
common/arm64_arch_timer.c:178:12: error: conversion from 'long unsigned int' to 'clock_t' {aka 'unsigned int'} changes value from '18446744073709551615' to '4294967295' [-Werror=overflow]
178 | *ticks = UINT64_MAX;
| ^~~~~~~~~~
Signed-off-by: hujun5 <hujun5@xiaomi.com>
At present, the serial drivers qemu_serial.c and serial_pl011.c on the fvp-v8r and qemu platforms in arm64 are duplicated
and need to be merged. The plan is to place them under the drivers\serial directory to create a common code module,
so that both fvp-v8r and qemu can use the same code.
In the future, if new platforms use pl011 serial ports, they can also be directly reused
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Summary:
Keeping this option out of depend on any common serial.
Using the option, need to implement xxx_lowputc.S/c.
You can also logging the booting message through rewriting
fake arm64_lowputc with other debug method (eg semihosting,
ARM debug channel etc).
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
1. arm64/makefile: preprocess link script to make configure more flexibly
2. arm64/EXTRA_LIBS: link all staging library
Signed-off-by: chao an <anchao@xiaomi.com>
in SMP, signal processing cannot be nested, we use xcp.sigdeliver to identify whether there is currently a signal being processed, but this state does not match the actual situation
One possible scenario is that signal processing has already been completed, but an interrupt occurs, resulting in xcp.sigdeliver not being correctly set to NULL,
At this point, a new signal arrives, which can only be placed in the queue and cannot be processed immediately
Our solution is that signal processing and signal complete status are set in the same critical section, which can ensure status synchronization
Signed-off-by: hujun5 <hujun5@xiaomi.com>
In the interrupt context, we should first save the interrupt context and modify the interrupt register
to execute the signal processing program immediately after exiting the current interrupt
Signed-off-by: hujun5 <hujun5@xiaomi.com>
1. Get the value of sp from dump regs when an exception occurs,
to avoid getting the value of fp from up_getsp and causing
incomplete stack printing.
2. Determine which stack the value belongs to based on the value
of SP to avoid false reports of stack overflow
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
CURRENT_REGS may change during assert handling, so pass
in the 'regs' parameter at the entry point of _assert.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
In smp when cpu0 calls up_cpu_resume to release the cpu1 lock, another locked cpu1 did not execute immediately,
and soon cpu0 called up_cpu_resume again, now cpu1 unable to respond to the interrupt at this time, resulting in a deadlock.
Our solution is to restore cpu1 execution from asynchronous to synchronous to ensure that cpu1 is restored.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Summary:
To reduce the count of FPU context switching will result at a
performance improve with system. it need to balance between
the using of FPU and counts of FPU trap
the PR submit a base method to see performance counts for
the FPU with NuttX procfs
Please read README.txt at chapter of FPU Support and Performance
for more information
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
