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56 Commits

Author SHA1 Message Date
Alexander Oryshchenko
dd4fc9f5c3 arch/arm/src/stm32: Make STM32 usable with an external RTC. drivers/timers/ds3231.c: Correct some debug statments. 2018-01-24 06:55:14 -06:00
Gregory Nutt
d958cec7a4 Cosmetic changes from review of last PR 2017-06-15 06:58:55 -06:00
Leif Jakob
4a79547fb8 multiple fixes for stm32f1xx RTC clock 
- compile issues because of missing RTC_MAGIC #defines
- missing functionality based on RTC_MAGIC in RTC based on stm32_rtcounter.c
- IRQ setup from up_rtc_initialize was later reset in up_irqinitialize
- write access to backup registers without enabling access to backup domain
- possible races in set/cancel alarm
tested with STM32F103C8 only
device now wakes up from forced STANDBY mode by alarm
 2017-06-14 22:36:40 +02:00
David Cabecinhas
08e92abb0b ARM: Remove redundant interrupt stack coloring 2017-03-16 19:13:39 +08:00
Mark Schulte
b3222bbc8a irq_dispatch: Add argument pointer to irq_dispatch 
Provide a user defined callback context for irq's, such that when
registering a callback users can provide a pointer that will get
passed back when the isr is called.
 2017-02-27 06:27:56 -06:00
Gregory Nutt
14de4b99f8 Simplify some computations 2016-07-23 08:13:25 -06:00
Paul A. Patience
a4d5845887 efm32, lcp43, stm32, stm32l4: disable interrupts with NVIC_IRQ_CLEAR 2016-06-28 15:12:39 -04:00
Gregory Nutt
0d3ecb3ddd Fix another victim of the mass name changes: xyz_errmonitor->xyz_dbgmonitor 2016-06-17 07:00:33 -06:00
Gregory Nutt
0c8c7fecf0 Add _ to the beginning of all debug macros to avoid name collisions 2016-06-16 12:33:32 -06:00
Gregory Nutt
c4e6f50eac Centralize definitions associated with CONFIG_DEBUG_IRQ 2016-06-15 08:35:22 -06:00
Gregory Nutt
a1469a3e95 Add CONFIG_DEBUG_ERROR. Change names of *dbg() * *err() 2016-06-11 15:50:49 -06:00
Gregory Nutt
e99301d7c2 Rename *lldbg to *llerr 2016-06-11 14:55:27 -06:00
Gregory Nutt
1cdc746726 Rename CONFIG_DEBUG to CONFIG_DEBUG_FEATURES 2016-06-11 14:14:08 -06:00
Aleksandr Vyhovanec
29ab0fb991 STM32: Add support for the IAR compiler 2016-04-02 06:58:55 -06:00
Gregory Nutt
51be83aa3a ARM: Fix missing header file. Update comments in all *_irq.c files. 2016-03-09 15:08:58 -06:00
Gregory Nutt
4d4f54a789 Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
Gregory Nutt
666cc280f4 Rename irqenable() to up_irq_enable(); rename irqdisable() to up_irq_disable() 2016-02-14 16:54:09 -06:00
Gregory Nutt
83bc1c97c3 Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore() 2016-02-14 16:11:25 -06:00
Gregory Nutt
70e502adb0 Replace irqsave() with enter_critical_section(); replace irqrestore() with leave_critical_section() 2016-02-13 19:11:09 -06:00
Gregory Nutt
dfec6a0dd0 Rename CONFIG_ARMV7M_MPU to CONFIG_ARM_MPU so that we can reuse the configuration settings for the ARMV7R MPU 2015-12-14 13:56:21 -06:00
Paul A. Patience
52454cf79b Fix typo 2015-11-11 13:06:15 -05:00
Gregory Nutt
beb060d422 Yet more spacing issues 2015-10-07 20:24:19 -06:00
Gregory Nutt
53f6fd6e66 STM32: Correct some spacing issues 2015-10-07 13:45:15 -06:00
Gregory Nutt
da6c5aabdf All ARMV7-M IRQ setup: Always set the NVIC vector table address. This is needed in cases where the code is running with a bootload and when the code is running from RAM. It is also needed by the logic of up_ramvec_initialize() which gets the vector base address from the NVIC. Suggested by Pavel Pisa 2015-08-21 08:42:24 -06:00
Gregory Nutt
7eb5e7f9ec STM32F746G-DISCO: Getting closer to a build 2015-07-17 11:47:16 -06:00
Gregory Nutt
ae15c6963c Make some file section headers more consistent with standard 2015-04-08 08:04:12 -06:00
Gregory Nutt
30b141e2c8 Remove CONFIG_DEBUG_STACK. Adding CONFIG_STACK_COLORATION makes this configuration option pointless 2015-01-24 06:49:51 -06:00
Gregory Nutt
e8f266001d Add CONFIG_STACK_COLORATION that does the same thing as CONFIG_DEBUG_STACK but without enabling debug. From David Sidrane 2015-01-24 06:03:39 -06:00
Gregory Nutt
6455f60c60 Remove os_internal.h it has been replace by several new header files under sched/. There have been some sneak inclusion paths via os_internal.h, so expect a few compilation errors for some architectures 2014-08-08 18:39:28 -06:00
Gregory Nutt
1061e67f14 Fix error in last ARMv7-M up_disable_irq checkin 2014-01-15 15:26:32 -06:00
Gregory Nutt
e43f86071d Fix all Cortex-M3/4 implementations of up_disable_irq(). They were doing nothing. Thanks to Manuel Stühn for the tip. 2014-01-15 09:56:30 -06:00
Gregory Nutt
4de5e40669 Individual IRQs are not longer disabled on each interrupt. See ChangeLog for detailed explanation 2014-01-15 08:09:19 -06:00
Gregory Nutt
29c43b0b24 Fixes a few more high priority, nested interrupt logic 2013-12-23 11:13:56 -06:00
Gregory Nutt
1705b3f894 Fix some missing parameters in macros 2013-12-22 16:29:36 -06:00
Gregory Nutt
3855ce04e8 Beginning of high priority nested interrupt support for the ARMv7-M family 2013-12-21 11:03:38 -06:00
Gregory Nutt
b8085906b9 Extend stack debug logic to include IDLE and interrupt stacks. Also color the heap as well. Based on suggestions from David Sidrane 2013-11-01 11:16:51 -06:00
Gregory Nutt
8b317e9ea3 Standard configuration variables used to enable interupt controller debug; SAMA5: Correct handling of spurious interrupts 2013-08-03 08:22:37 -06:00
Gregory Nutt
3aa94411be Remove up_assert_code 2013-04-25 15:19:59 -06:00
patacongo
65fb38bbcf Add support for ram vectors to the ARMv7-M architecture 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5756 42af7a65-404d-4744-a932-0658087f49c3
 2013-03-18 21:10:08 +00:00
patacongo
23082b88cc More files for the Cortex-M0/NUC120 port 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5659 42af7a65-404d-4744-a932-0658087f49c3
 2013-02-18 20:24:20 +00:00
patacongo
896e32f73d Removed stm32_internal.h; Changes for clean compile of STM32F3Discovery configuration with SPI and USB 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5630 42af7a65-404d-4744-a932-0658087f49c3
 2013-02-09 15:03:49 +00:00
patacongo
a001227981 Use of BASEPRI to control ARM interrupts is now functional 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5548 42af7a65-404d-4744-a932-0658087f49c3
 2013-01-22 16:09:10 +00:00
patacongo
30d1159097 More logic to use BASEPRI to control interrupts -- still doesn't work 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5547 42af7a65-404d-4744-a932-0658087f49c3
 2013-01-22 14:37:17 +00:00
patacongo
5ab31d456e Add option to use BASEPRI instead of PRIMASK to disable interrupts in all ARMv7-M architectures 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5546 42af7a65-404d-4744-a932-0658087f49c3
 2013-01-22 01:25:40 +00:00
patacongo
5347c159fb Add LPC43 interrrupt control logic 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4905 42af7a65-404d-4744-a932-0658087f49c3
 2012-07-04 19:34:11 +00:00
patacongo
d1db9fe5e0 Interrupt priority fix + new LM3S header files 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4792 42af7a65-404d-4744-a932-0658087f49c3
 2012-06-01 13:22:27 +00:00
patacongo
f93b962f28 Name change: Change Cortex-M3 naming to ARMv7-M naming so support Cortex-M4 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3846 42af7a65-404d-4744-a932-0658087f49c3
 2011-08-05 21:57:49 +00:00
patacongo
7bb3b4c8a1 current_regs should be volatile; add support for nested interrupts; enable interrupts during syscall processing 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3475 42af7a65-404d-4744-a932-0658087f49c3
 2011-04-06 23:01:06 +00:00
patacongo
a864ab2137 Attach mem mgmt fault handle if MPU is enabled 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3471 42af7a65-404d-4744-a932-0658087f49c3
 2011-04-06 01:51:07 +00:00
patacongo
198db02acd Add stubs for AVR32 IRQ controls 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2988 42af7a65-404d-4744-a932-0658087f49c3
 2010-10-09 22:02:25 +00:00