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1920 Commits

Author SHA1 Message Date
Gregory Nutt
b065b1f5df STM32 Serial: Fix some incorrect conditional compilation 2017-09-23 10:58:50 -06:00
David Sidrane
a3364b5bd9 Merged in david_s5/nuttx/master_stm32_f4_i2c (pull request #490) 
stm32:stm32f40xxx I2C ensure proper isr handling

Injecting data errors that causes a STOP to be perceived by the
   driver, will continually re-enter the isr with SB not set and BTF
   and RxNE set.  This changes allows the interrupts to
   be cleared and  propagates a I2C_SR1_TIMEOUT to the waiting task.

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-21 20:02:05 +00:00
Gregory Nutt
882adb2c82 drivers/video/fb.c: Fix a typo introduced in previous commit. 2017-09-17 14:07:08 -06:00
Rajan Gill
fd9f67c647 STM32 Tickless: The attached patch removes the restriction to 16bit counts when a 32bit timer is used for the new tickless on the stm32. As it is now, the restriction is very limiting, especially if one wants high granularity and large achievable intervals and has the hardware (namely the 32bit timers) available. 2017-09-16 08:20:07 -06:00
Gregory Nutt
13006ecca9 STM32/STM32 F7: Fix some errors found by Coverity. 2017-09-13 13:05:13 -06:00
Rajan Gill
15784ca46f STM32 Tickless: Fixes compilation error when timer info/debug messages are enabled. 2017-09-13 07:14:13 -06:00
David Sidrane
2bbe389897 stm32:Fix coding standard error 2017-09-12 14:16:46 -10:00
David Sidrane
ef411578d5 stm32:stm32 alt I2C ensure proper error handling. 
Injecting data errors would cause the driver to
  continually reenter the isr with BERR an RxNE.
  This fix allows the error to be cleared and
  propagated to the waiting task.
 2017-09-12 14:16:45 -10:00
David Sidrane
617c91b373 stm32:stm32f40xxx I2C ensure proper error handling. 
Injecting data errors would cause the driver to
  continually reenter the isr with BERR an RxNE.
  This fix allows the error to be cleared and
  propagated to the waiting task.
 2017-09-12 14:16:45 -10:00
Mateusz Szafoni
2ffc2ab875 Merged in raiden00/nuttx (pull request #480) 
Master

* smps.c: fix error messages

* stm32f33xxx_hrtim.h: fix definition

* stm32_hrtim: fix pclk calculation

* stm32_hrtim.c: cosmetics

* smps.h: cosmetics

* add upper-half driver for high power LED driver (powerled)

* stm32f334-disco: beginning of lower half driver for high power LED (powerled)

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-10 17:43:20 +00:00
Gregory Nutt
3ca3674cca Update/fix last commit: On some STM32's, the CSR regiser is 18 vs. 16 bits wide. Need to use 32-bit register accesses. 2017-09-08 14:21:24 -06:00
Oleg Evseev
3596c75d78 STM32: Add logic for enabling wakeup pins. 2017-09-08 13:23:08 -06:00
Mateusz Szafoni
23edfe2557 Merged in raiden00/nuttx (pull request #477) 
Master

* stm32f33xxx_hrtim.h: add some comments

* stm32_hrtim: add burst mode configuration, rename some definitions

* smps.h: add private data to the smps_s structure

* stm32_hrtim: cosmetics

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-03 18:46:41 +00:00
Gregory Nutt
5f67fc8f1b RTC alarms: getalarmdatetime functions are private and should be declared static. 2017-09-03 12:20:13 -06:00
Gregory Nutt
789e204141 Correct naming of fields in struct alm_rdalarm_s. Should not be the same as the corresponding fields of struct alm_setalarm_s. The whole purpose of that naming convention is to keep the field names unique. 2017-09-03 09:51:47 -06:00
Gregory Nutt
9021e1caeb Port Boris Astardzhiev RTC change for STM32L4 to STM32 2017-09-03 08:39:03 -06:00
Mateusz Szafoni
daac3bd7f8 Merged in raiden00/nuttx (pull request #476) 
Master

* stm32_dac.c: fix compilation when DMA disabled for channel

* smps.h: update some comments

* smps.c: more sanity checks

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-02 19:52:21 +00:00
Juha Niskanen
4025205772 STM32L4 DAC: add option for routing DAC output to ADC 
Actually write something to the DAC DMA buffer.

Change-Id: I1b2516ac26fb17f5242611b56be8926c5f40c2c7
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2017-09-01 10:00:46 +03:00
Gregory Nutt
91d473b816 Revert "stm32 FLASH allow non blocking operation on constrained devices" 
This reverts commit ad2ef95ddf.
 2017-08-31 15:14:26 -06:00
David Sidrane
9fc283526a Merged in david_s5/nuttx/master_stm32_flash (pull request #474) 
stm32 FLASH allow non blocking operation on constrained devices

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-08-31 18:04:07 +00:00
Sergey Ustinov
8c35b2ddca Add the set counter function for stm32 timers 2017-08-31 11:54:00 -06:00
David Sidrane
ad2ef95ddf stm32 FLASH allow non blocking operation on constrained devices 
On a very memory constrained device with a single task. The
   sem_wait and sem_post operations can be disabled, to save space.
   The default is blocking enabled.
 2017-08-31 07:47:37 -10:00
Sergei Ustinov
795650a2fb I'm worried about the stm32_tim_getcounter funtion. It returns always 32 bits. But major stm32 timers have 16 bits counters. I think, it's not a good idea to return the memory behind the TIMx_CNT register. This changes adds the register size checking. 2017-08-31 11:45:28 -06:00
raiden00pl
85c48de040 stm32_hrtim: add DMA configuration 2017-08-28 17:44:14 +02:00
Juha Niskanen
a2dc88e075 STM32, STM32L4, STM32F7 ADC: fix channel 18 sample time 2017-08-28 07:05:33 -06:00
raiden00pl
5695a55569 stm32_dac.c: support external triggering for DMA transfer 2017-08-27 18:25:55 +02:00
Mateusz Szafoni
ea35f31f73 Merged in raiden00/nuttx (pull request #469) 
Master

* stm32f0/Kconfig: remove references to HRTIM

* STM32F33: missing SYSCFG CFGR3 definitions

* stm32_hrtim.h: remove redundant definitions

* stm32_hrtim.c: fix DAC triggers configuration

* stm32_hritm.c: warning message when default value selected

* stm32_hrtim.c: missing master timer logic

* stm32_hrtim.c: add more assertions

* stm32_dac.c: fix conditional

* stm32_dac.c: conditional logic for timer triggering

* stm32_dac.c: fix TSEL configuration when HRTIM

* stm32_dac.c: unnecessary condition

* stm32_dac.c: DMA request remapping

* stm32_dac.c: fix commpilation errors

* stm32_dac.c: add DMA buffers initialization logic

* stm32_hrtim.c: enable DAC triggering

* analog/comp.c: fix compilation errors when poll disabled

* stm32_hrtim.c: remove doubled assertions

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-08-27 12:49:53 +00:00
Gregory Nutt
dc8f3778a9 drivers/sensors: Fix more naming of configurations to be compliant for two more drivers. Still a few more to go. 2017-08-24 10:26:53 -06:00
raiden00pl
a5997cb186 stm32_dac: add support for HRTIM triggering 2017-08-21 19:46:18 +02:00
raiden00pl
a5f3a5848d stm32_dac.c typo 2017-08-21 18:59:21 +02:00
raiden00pl
db7a94288f stm32f33xxx_dma.h: typos 2017-08-21 18:50:07 +02:00
raiden00pl
b460f2bca1 stm32f10xxx_dma.h: fix DAC names and remove STM32F33 section 2017-08-21 18:50:07 +02:00
raiden00pl
104ff2b5d8 stm32_dac: separate dma buffer configuration for channels 2017-08-21 18:50:07 +02:00
Mateusz Szafoni
ccd421b158 stm32_dac.c edited online with Bitbucket 2017-08-20 18:47:44 +00:00
raiden00pl
04743f3e77 stm32_dac: change name convention. Previous naming was confusing 2017-08-20 20:19:53 +02:00
raiden00pl
a8e8862ef9 stm32_dac.c: fix some configuration logic. When STM32_NDAC is greather than 1, then second channel is always DAC1OUT2. 2017-08-20 19:02:56 +02:00
raiden00pl
1479fd6075 stm32_comp: add default INM configuration and some missing COMP1,3,5,7 code 2017-08-20 10:45:55 +02:00
raiden00pl
30ebd32ab4 stm32f33xxx_pinmap.h: missing define 2017-08-20 10:45:55 +02:00
raiden00pl
241c42447f stm32f33xxx_comp.h: typos 2017-08-20 10:45:55 +02:00
raiden00pl
01c98df18c STM32F33: remove redundant DAC file 2017-08-20 10:45:55 +02:00
Juha Niskanen
a9343ca12b stm32/stm32f0: Fix some funny shifts in DAC header files. 2017-08-14 06:28:09 -06:00
Gregory Nutt
f6f4856cc6 Eliminate some warnings found in build testing. 2017-08-13 12:24:48 -06:00
Gregory Nutt
4b6f0149ec Eliminate a warning found in build testing. 2017-08-12 11:14:11 -06:00
Jeff
4cbde22992 I'm working on bringing up USB full-speed support on STM32F405.  My board does not include a USB power switch, VBus sensing, over current detection, or ID pin. 
This commit add a config STM32_OTGFS_VBUS_ CONTROL which lets us selectively disable VBus sensing and control.  I also sneaked in a change to disable the configgpio call for the ID pin, which is only used in OTG mode which isn't supported yet.  The only pins that need to be initialized should be OTGFS_DP and OTGFS_DM.

These changes let a USB mouse enumerate on my platform if it's plugged in on power-up.  Plugging, unplugging, clicking, or moving the mouse cause NSH to stop responding.  Because I'm using the ramlog, I don't have useful debug messaging yet, so there's a lot more work I have to do to troubleshoot it or get my JTAG debugging set up, but these patches shouldn't hurt anything.  I'm hoping my issue is something simple I overlooked in configuration.

I'm planning to add similar changes for the OTGHS peripheral (using integrated full speed phy) but I still need to test those changes before submitting patches.
 2017-08-07 10:24:31 -06:00
Juha Niskanen (Haltian)
20dc5ad3b4 STM32L1: add base address for TIM11 
STM32L4 PWR: correct PWR_SR2 REGLPS and REGLPF bits, add port I registers.  Also remove duplicate section from Kconfig
 2017-07-31 07:32:43 -06:00
Jeff
a420c0f369 To use an external oscillator module (not just a crystal) with the STM32F4, one needs to enable the HSEBYP bit in the RCC_CR register. This change allows an integrator to define STM32_RCC_CR_HSEBYP in their board.h file if they want this configuration. 2017-07-30 06:22:30 -06:00
raiden00pl
f6c1d59531 stm32_hrtim: add slave timers private data, fix some bad definitions, some asserions 2017-07-22 15:14:59 +02:00
Gregory Nutt
79e5d2b7b6 STM32 TIM3/4 are always 16-bits; never 32-bits. Noted by Eetu Nevalainen. 2017-07-10 13:56:06 -06:00
Gregory Nutt
76587b2c6f STM32 Kconfig: 'unfold' some of the dependencies to provide better long term configuration support. This also effective reverts the recent 15b85738e7 2017-07-06 10:34:54 -06:00
Gregory Nutt
47be509d79 Rename CONFIG_STM32_STM32F40XX to CONFIG_STM32_STM32FXXXX since it is used by F4 parts other than F40x 2017-07-06 10:20:14 -06:00
gwenhael.goavec
15b85738e7 In arch/arm/src/stm32/Kconfig when the CPU is a STM32F4, some STM32_HAVE_xx with xx = {OTGFS, TIM3, TIM4, SPI3, I2S3, I2C3} are selected by default. But for F410 these peripherals are absent. This change add tests to check if the target CPU is an F410 or not and selects according to the situation. This also adds a select for STM32_HAVE_DAC1 present on this STM32 flavor. 2017-07-06 09:52:21 -06:00
Eetu Nevalainen
21dcc8cbc7 stm32f40xxx_rtcc ISR register and write protection fix 2017-07-03 11:06:07 -06:00
Gregory Nutt
1c5ec07414 arch/: Remove dangling space at the end of lines. 2017-06-28 13:16:48 -06:00
Gregory Nutt
aa1708e7c0 6LoWPAN: Update README; fix duplicate and bad memcpy in loopback driver. 2017-06-26 10:53:57 -06:00
raiden00pl
715d6fa9ff stm32f33xxx_rcc: cleanup + move hrtim clock source selection 2017-06-26 18:30:10 +02:00
raiden00pl
aead2b2afd stm32f33xxx_rcc.h: fix typo 2017-06-26 18:26:59 +02:00
Sebastien Lorquet
0bf4893b2c STM32: Allow clock frequencies > 168 Mhz on stm32f427/429. We need to enable the power overdrive for this case. This patch allows the required bits to be set in proper sequence. It also modifies the local register access operations to allow more than 16-bit registers. 2017-06-20 11:56:54 -06:00
Gregory Nutt
47ad81b3e5 Trivial spelling fix 2017-06-20 08:02:42 -06:00
raiden00pl
c29c4e2ec2 stm32_hrtim: remove unneeded definitions 2017-06-18 18:08:25 +02:00
raiden00pl
4e0f45f252 stm32_hrtim: fix initialization bug, minor changes 2017-06-18 18:06:37 +02:00
raiden00pl
cd30545cd9 stm32_hrtim: ADC triggering and DAC synch events 2017-06-18 15:26:39 +02:00
raiden00pl
96e639262a stm32_hrtim: add hrtim ops 2017-06-18 11:01:36 +02:00
raiden00pl
797e286cb0 stm32_hrtim: timers mode configuration 2017-06-18 09:28:05 +02:00
raiden00pl
dfeffefa69 stm32_hrtim: typo 2017-06-18 08:02:15 +02:00
Gregory Nutt
0024840f7d Trivial, cosmetic changes from review of last PR 2017-06-17 14:44:11 -06:00
raiden00pl
b48a86ee33 Merge remote-tracking branch 'upstream/master' 2017-06-17 22:18:03 +02:00
raiden00pl
4d9d3c4a9c stm32_hrtim: cosmetics 2017-06-17 22:12:56 +02:00
raiden00pl
5e3360b8b9 stm32_hrtim: faults and events configuration 2017-06-17 21:56:11 +02:00
David Sidrane
c79d4d1988 stm32:flash add CONFIG_STM32_STM32F469 to list defining OPTCR1 2017-06-16 14:16:32 -10:00
Gregory Nutt
5245cbc6f5 STM32 SPI/I2S: Back out a bad pin mapping change from 4ab2a3661e. Try to staighten out some I2C3 and SPI3 pin configuration stuff. 2017-06-16 09:34:22 -06:00
Sebastien Lorquet
4d9be9bc20 STM32 F4 FLASH: Enable/disable the flash write protection on any sector. I have verified it to work on the stm32f427. 2017-06-16 08:46:57 -06:00
raiden00pl
bd7bee5db0 stm32_hrtim: structures for deadtime and chopper, cosmetics 2017-06-16 11:36:23 +02:00
raiden00pl
268c6d0b7d stm32_hrtim: outputs enable, period and compare functions, cosmetics 2017-06-15 16:45:21 +02:00
Gregory Nutt
d958cec7a4 Cosmetic changes from review of last PR 2017-06-15 06:58:55 -06:00
raiden00pl
96d40dec40 stm32_hrtim: cosmetic 2017-06-15 11:20:40 +02:00
Leif Jakob
4a79547fb8 multiple fixes for stm32f1xx RTC clock 
- compile issues because of missing RTC_MAGIC #defines
- missing functionality based on RTC_MAGIC in RTC based on stm32_rtcounter.c
- IRQ setup from up_rtc_initialize was later reset in up_irqinitialize
- write access to backup registers without enabling access to backup domain
- possible races in set/cancel alarm
tested with STM32F103C8 only
device now wakes up from forced STANDBY mode by alarm
 2017-06-14 22:36:40 +02:00
Gregory Nutt
e379491d13 STM32/STM32L4: Review of last commit -- Eliminate possible underflow 2017-06-13 07:05:46 -06:00
JM
7903a8a46c stm32/stm32l4 PWM: While attempting to output a 70 MHz square wave from the timer output of a STM32 clocked at 140 MHz (which works fine in baremetal C), I stumbled on what I believe to be an error in arch/arm/src/stm32/stm32_pwm.c. Line 1304 we are told that 
reload = timclk / info->frequency;

which I belive to be incorrect, it should be

reload = timclk / info->frequency - 1;

since starting to count from 0, if I want to output half of the TIM clock, I must count to 1 and not to 2.

Surely enough, the original code did output 140/3=47 MHz, while this correction does allow the output up to 70 MHz.

I am not sure this affects most users generating slow PWM (e.g. PX4) but for frequencies
close to the PCLK, indeed the difference becomes significant.
 2017-06-13 06:01:13 -06:00
raiden00pl
f6ba4642a3 stm32_hrtim: GPIOs configuration + EEV and FAULT strucutres 2017-06-12 18:45:58 +02:00
raiden00pl
de8cd6c870 stm32_hrtim: add character driver 2017-06-11 20:51:23 +02:00
Gregory Nutt
fe813545e8 STM32F33: Forgot to add new files that were a part of the last patch before committing. 2017-06-11 11:00:29 -06:00
Mateusz Szafoni
437ad3ccb2 STM32F33: Fix hrtim definitions, Add beginning of HRTIM driver 2017-06-11 10:49:20 -06:00
Juha Niskanen
0c9abbfe67 STM32L4: Add IWDG peripheral. This is the same as for STM32 except that prescale and reload can be 
changed after watchdog has been started, as this seems to work on L4.
 2017-05-23 07:02:36 -06:00
Gregory Nutt
7ffbb704d6 This is based on a patch by Taras Drozdovsky. Basically, the delay that was added during the integration of the CDC/ACM host driver was interfering with streaming audio. That delay was put there to prevent build endpoints from hogging the system bandwidth. So what do we do? Do we hog the bandwidth or do we insert arbitrarity delays. I think both ideas such. 2017-05-21 14:28:29 -06:00
Taras Drozdovsky
4ab2a3661e STM32F4: add cs43l22 audio driver and i2s driver 2017-05-21 14:14:09 -06:00
Juha Niskanen
819a6e049e stm32_i2c: make private symbols static 2017-05-19 07:16:01 -06:00
Gregory Nutt
989195cec8 STM32 Ethernet: Last patch breaks every board that does not use the KSZ80801 PHY. 2017-05-17 15:36:57 -06:00
Gregory Nutt
aac3a3df8e STM32 Ethernet: Should not stm32_phyintenable() return a failure if it could not enable the PHY interrupt? 2017-05-17 10:07:09 -06:00
Sebastien Lorquet
2c6ea23aee STM32 Ethernet: Add support for KSZ8081 PHY interrupts. 2017-05-17 10:04:49 -06:00
Jussi Kivilinna
9169ff6a15 stm32_serial: fix freezing serial port. Serial interrupt enable/disable functions do not disable interrupts and can freeze device when serial interrupt is received while execution is at those functions. 
Trivially triggered with two or more threads write to regular syslog stream and to emergency stream. In this case, freeze happens because of mismatch of priv->ie (TXEIE == 0) and actually enabled interrupts in USART registers (TXEIE == 1), which leads to unhandled TXE interrupt
and causes interrupt storm for USART.
 2017-05-17 06:50:46 -06:00
Lederhilger Martin
b8e7d5c455 I had the problem that the transmit FIFO size (= actual elements in FIFO) was slowly increasing over time, and was full after a few hours. 
The reason was that the code hit the line "canerr("ERROR: No available mailbox\n");" in stm32_cansend, so can_xmit thinks it has sent the packet to the hardware, but actually has not. Therefore the transmit interrupt never happens which would call can_txdone, and so the size of the FIFO size does not decrease.

The reason why the code actually hit the mentioned line above, is because stm32can_txready uses a different (incomplete) condition than stm32can_send to determine if the mailbox can be used for sending, and thus can_xmit forwards the packet to stm32can_send. stm32can_txready considered mailboxes OK for sending if the mailbox was empty, but did not consider that mailboxes may not yet be used if the request completed bit is set - stm32can_txinterrupt has to process these mailboxes first.

Note that I have also modified stm32can_txinterrupt - I removed the if condition, because the CAN controller retries to send the packet until it succeeds. Also if the condition would not evaluate to true, can_txdone would not be called and the FIFO size would not decrease also.
 2017-05-16 07:47:18 -06:00
Gwenhael Goavec-Merou
02535be36a STM32F410. Add support for STM32Fr10. STM32F410 is a version of STM32F4 with 32 KB of RAM and 62 or 128 KB of flash. 2017-05-13 08:40:09 -06:00
Alan Carvalho de Assis
853d332b6c Move CAN subsystem to its own directory and put device drivers there 
Signed-off-by: Alan Carvalho de Assis <acassis@gmail.com>
 2017-05-12 11:48:47 -03:00
Gregory Nutt
0de294a586 Fix lots of occurrences of 'the the', 'the there', 'the these', 'the then', 'the they. 2017-05-11 13:35:56 -06:00
David Sidrane
014b69e120 removed stray paren. 2017-05-08 22:56:05 +00:00
David Sidrane
8406b40baa Merged in david_s5/nuttx-16/david_s5/stm32serial-dma-buffer-round-off-not-up-1494258804216 (pull request #357) 
stm32:Serial DMA buffer round off not up

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-05-08 20:32:44 +00:00
Gregory Nutt
aa11d637a8 STM32 TIM: Add method to get timer width. Freerun timer: Use timer width to get the correct clock rollover point. 2017-05-08 12:33:15 -06:00
David Sidrane
546e7acb99 stm32:Serial DMA buffer round off not up 2017-05-08 15:54:03 +00:00
David Sidrane
b8ef079951 stm32:stm32_serial Forgot the -1 on mask 2017-05-08 03:43:36 +00:00
David Sidrane
b62ef579c8 stm32: serial Allow configuring Rx DMA buffer size 2017-05-06 05:16:21 -10:00
Gregory Nutt
b0e880b04c Revert "STM32 I2C: More backward tests of CONFIG_I2C_POLLED. Needs to be reviewed." 
This reverts commit 1e054a2d3b.
 2017-05-03 18:26:24 -06:00
Gregory Nutt
11c14470c3 Merge remote-tracking branch 'origin/master' into photon 2017-05-03 17:36:52 -06:00
Gregory Nutt
1e054a2d3b STM32 I2C: More backward tests of CONFIG_I2C_POLLED. Needs to be reviewed. 2017-05-03 17:33:35 -06:00
David Sidrane
9b5ac56409 Fixed typo and backward ifdef 2017-05-03 23:10:48 +00:00
Gregory Nutt
e94865a317 Merge remote-tracking branch 'origin/master' into photon 2017-05-02 08:49:19 -06:00
Mateusz Szafoni
1feaae7222 Merged in raiden00/nuttx (pull request #338) 
OPAMP support for STM32F33XX
 2017-05-02 13:57:56 +00:00
Gregory Nutt
e43b86dbd0 Merge remote-tracking branch 'origin/master' into photon 2017-04-30 17:42:37 -06:00
Gregory Nutt
0597eb5587 Fix a typo introduced in last commit. 2017-04-30 12:41:19 -06:00
Gregory Nutt
c172d7cf63 EFM32, STM32, and STM32 F7 I2C: Update to use the standard parameter passing to interrupt handlers. 2017-04-30 11:56:06 -06:00
raiden00pl
e4d47d61cc STM32F33: Add OPAMP support 2017-04-30 11:05:34 +02:00
Gregory Nutt
a7901f5c4c Merge remote-tracking branch 'origin/master' into photon 2017-04-29 12:35:01 -06:00
Gregory Nutt
f175af3cd3 More missed enum spi_dev_e forward references. 2017-04-29 08:29:01 -06:00
Sebastien Lorquet
c56c6f7ccc ARM arch changes 2017-04-28 18:23:29 +02:00
Juha Niskanen
707d1e67fc STM32, STM32F7, STM32L4: Remove incorrect comment about STM32L1 LSE/RTC/LCD 2017-04-27 07:18:36 -06:00
Simon Piriou
6bb2db8c15 bcmf: enable DMA for SDIO transfers 2017-04-26 17:23:53 +02:00
Simon Piriou
3bf5044306 stm32: cleanup stm32_sdio.c 2017-04-24 20:01:41 +02:00
Gregory Nutt
62966d915c Merge remote-tracking branch 'origin/master' into photon 2017-04-23 10:16:54 -06:00
Gregory Nutt
79256573e1 net: network drver now retains Ethernet MAC address in a union so that other link layer addresses may be used in a MULTILINK environment. 2017-04-22 11:10:30 -06:00
Gregory Nutt
d8e4cbcfd5 Merge remote-tracking branch 'spiriou/wlan_dev' into photon 2017-04-22 08:26:40 -06:00
Jussi Kivilinna
325ba1a803 clock: add clock_resynchronize and use subseconds RTC 
Add clock_resynchronize for better synchronization of CLOCK_REALTIME and CLOCK_MONOTONIC to match RTC after resume from low-power state.

Add up_rtc_getdatetime_with_subseconds under CONFIG_ARCH_HAVE_RTC_SUBSECONDS to allow initializing (and resynchronizing) system clock with subseconds accuracy RTC.
 2017-04-21 08:45:57 -06:00
Juha Niskanen
9d0ecedf7d Add support for STM32L152CC, STM32L152RC and STM32L152VC. Update some bits and comments for other STM32L1 parts in chip.h 2017-04-20 06:30:26 -06:00
Juha Niskanen
e631ee4582 STM32 L1: stm32l15xx_rcc: Allow board to configure HSE clock in bypass-mode. Allows using MCO output from ST-link chip (on Nucleo and Discovery boards) as HSE input. 2017-04-20 06:28:01 -06:00
David Sidrane
4844011b9c stm32:stm32_serial fixed warning 2017-04-18 11:51:56 -10:00
Gregory Nutt
04ebdbb336 Move: CONFIG_ADC_NO_START_CONV from drivers/adc/Kconfig to arch/arm/src/stm32[f7]/Kconfig as STM32[F7]_ADC_NO_START_CONV. Refresh all configurations with any reference to CONFIG_ADC_NO_START_CONV. 2017-04-18 07:16:35 -06:00
phreakuencies
eac049222c STM32: Provide TIM5 definition for STM32F429 2017-04-15 12:10:42 -06:00
Gregory Nutt
78bc1aa6bc Argument of network device IOCTL should be unsigned long, just as will all other IOCTL methods. 2017-04-15 09:33:27 -06:00
Simon Piriou
11d3db5c35 photon: add sdpcm + thread support for wlan 2017-04-15 11:39:13 +02:00
Alan Carvalho de Assis
a58823c449 STM32XX: Fix Pending Register definition 2017-04-11 06:45:45 -06:00
Gregory Nutt
ebd2416f9d stm32 COMP: Logic in stm32_comp.h must be configured on CONFIG_STM32_COMP or otherwise it causes an error via #error on every platform without COMP support. 2017-04-09 11:47:57 -06:00
Jussi Kivilinna
e3b3e57e56 RTC: add interface for check if RTC time has been set 
New interface allows checking if RTC time has been set.  This allows to application to detect if RTC has valid time (after
reset) or should application attempt to get real time by other means (for example, by launching ntpclient or GPS).
 2017-04-06 09:53:11 -06:00
Alan Carvalho de Assis
95941b4908 STM32: Fix SYSCFG_CFGR1_I2C_PBXFMP_SHIFT value 2017-04-06 08:35:33 -06:00
Simon Piriou
e5c4a28c3a photon: wlan support 2017-04-05 21:55:21 +02:00
Juha Niskanen
3e6b92d5fa tm32: stm32l15xxx_rcc: configure medium performance voltage range and zero wait-state when allowed by SYSCLK setting 
Zero wait-state for flash can be configured when:
 Range 1 and SYSCLK <= 16 Mhz
 Range 2 and SYSCLK <= 8 Mhz
 Range 3 and SYSCLK <= 4.2 Mhz

Medium performance voltage range (1.5V) can be configured when SYSCLK is up to 16 Mhz and PLLVCO up to 48 Mhz.
 2017-04-05 07:41:25 -06:00
Juha Niskanen
bff341fdfc stm32: stm32l15xx_rcc: add support for using MSI as system clock 2017-04-05 07:41:24 -06:00
Juha Niskanen
9a29b9a327 stm32: stm32_flash: add EEPROM writing for STM32L15XX 2017-04-04 07:38:49 -06:00
no1wudi
8fbd8b9e6f STM32:add I2C3 SDA pin mapping for STM32F411 2017-04-04 11:57:45 +08:00
no1wudi
730b674b01 STM32:add I2C3 SDA pin mapping for STM32F411 2017-04-04 11:50:58 +08:00
Juha Niskanen
3a6bd901e4 stm32: fix IWDG and WWDG debug mode stop for STM32L15XX 2017-04-03 07:45:09 -06:00
Gregory Nutt
fb42844788 STM32: Fix a comment 2017-04-02 12:32:20 -06:00
Gregory Nutt
7b789f57ac Review of previous commit 2017-03-30 12:28:40 -06:00
Konstantin Berezenko
95cbbf552b Change STM32 tickless to use only one timer 2017-03-30 10:40:05 -07:00
Juha Niskanen
5577f58458 STM32 RNG: Fix semaphore initial value and disable priority inheritance 2017-03-29 07:12:19 -06:00
Gregory Nutt
92da8068ed Merge branch 'master' of bitbucket.org:nuttx/nuttx 2017-03-26 06:57:35 -06:00
raiden00pl
f3367233b6 stm32_comp.c: typo 2017-03-26 09:36:53 +02:00
raiden00pl
c1090164f5 stm32/Kconfig: update COMP and OPAMP definitions 2017-03-26 09:34:17 +02:00
raiden00pl
6594c65a77 stm32_comp.c: cosmetic 2017-03-26 09:30:23 +02:00
Gregory Nutt
7d57a2b2bd Trivial changes from review of last PR. 2017-03-25 10:38:41 -06:00
raiden00pl
a806aedb13 STM32F33: Support for COMP character driver 2017-03-25 16:57:43 +01:00
Alexander Oryshchenko
61ff3c6b84 I needed to use DS3231, I remember that in past it worked ok, but now for stm32f4xx is used another driver (chip specific, stm32f40xxx_i2c.c) and DS3231 driver doesn't work. After investigating a problem I found that I2C driver (isr routine) has a few places there it sends stop bit even if not all messages are managed. So, e.g., removing stm32_i2c_sendstop (#1744) and adding stm32_i2c_sendstart after data reading helps to make DS3231 working. Verified by David Sidrane. 2017-03-24 06:44:33 -06:00
Aleksandr Vyhovanec
82a84a8d98 Merged nuttx/nuttx into master 2017-03-24 11:40:09 +03:00
no1wudi
4c6680df99 Merged in no1wudi/nuttx (pull request #291) 
fix compile error when disabled the flash data cache corruption for stm32 f1xx

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-03-24 00:58:26 +00:00
no1wudi
fd76a3db05 fix spacing 2017-03-24 08:52:46 +08:00
no1wudi
5797e84893 Merged nuttx/nuttx into master 2017-03-24 08:40:40 +08:00
David Sidrane
66910577be stm322_flash:missing unlock on F1 HSI off path 2017-03-23 14:22:45 -10:00
David Sidrane
7e3bec635b stm32_i2c_alt:Move def of regval to top func def per CS 2017-03-23 11:50:37 -10:00
David Sidrane
d25f8710d2 stm32f40xxx_i2c:Duplicate non CS dev of regval 2017-03-23 11:37:12 -10:00
David Sidrane
f5cf22d871 stm32_i2c_alt:Duplicate non CS dev of regval 2017-03-23 11:36:44 -10:00
David Sidrane
c2a1b719be stm32_flash:Need conditinal on non F4 targets 2017-03-23 11:33:32 -10:00
rg
9353ca6039 STM32 I2C: Do not allow CONFIG_I2C_POLLED and CONFIG_I2C_DMA 2017-03-23 11:24:18 -06:00
Aleksandr Vyhovanec
06af125e45 The interrupt occurs over the counter overflow 2017-03-23 17:34:45 +03:00
no1wudi
45f5d30e2e fix compile error when disabled the flash data cache corruption for stm32 f1xx 2017-03-23 13:38:26 +08:00
Gregory Nutt
3fb0a00c35 Small changes from review of last PR. Plus spacing and typo fix. 2017-03-22 17:32:52 -06:00
Gregory Nutt
947acd6c1a Small changes from review of last PR 2017-03-22 15:53:12 -06:00
José Roberto de Souza
b9b4f184a7 stm32: Add workaround for flash data cache corruption on read-while-write 
This is a know hardware issue on some STM32 see the errata of your model
and if you make use of both memory banks you should enable it.
 2017-03-22 13:14:19 -07:00
José Roberto de Souza
09f70c462d stm32: Make up_progmem thread safe 
Writing to a flash sector while starting the erase of other sector
have a undefined behavior so lets add a semaphore and syncronize
access to Flash registers.

But for the semaphore to work it needs to be initialized so each
board needs call stm32_flash_initialize() on initialization, so
to avoid runtime problems it is only using semaphore and making
it thread safe if initialized, after all boards starts to call
stm32_flash_initialize() we can remove the boolean and the check.
 2017-03-22 13:14:15 -07:00
José Roberto de Souza
80f56e75f9 stm32: Fix erase sector number for microcontrolers with more than 11 sectors 
Erase a sector from the second bank cause the bit 4 of SNB being set
but never unsed, so trying to erase a sector from the first bank
was acually eraseing a sector from the second bank.
 2017-03-22 12:42:20 -07:00
rg
82a5dfddb4 The attached .patch implements DMA support for the stm32f4 I2C. Max and I have verified that it works on our systems. 2017-03-21 16:44:11 -06:00
no1wudi
7d6ee0f222 fix a typo 2017-03-20 09:50:27 +08:00
Gregory Nutt
e8a30890f2 Cosmetic changes from review of last PR. 2017-03-19 13:05:31 -06:00
raiden00pl
651b8360c6 STM32F33: Add COMP support 2017-03-19 18:36:44 +01:00
raiden00pl
c760d00158 stm32f33xx_comp.h: fix typos 2017-03-19 18:27:31 +01:00
raiden00pl
fd42900dcc STM32F33: Add ADC support 2017-03-18 16:34:24 +01:00
raiden00pl
49e4e62aab STM32F33: Move DMA logic to a separate files 2017-03-18 16:31:06 +01:00
David Cabecinhas
08e92abb0b ARM: Remove redundant interrupt stack coloring 2017-03-16 19:13:39 +08:00
Simon Piriou
bf9391a1fe photon: porting wlan device 2017-03-14 21:13:36 +01:00
David Cabecinhas
86400a252d ARM: Fix off-by-one interrupt stack allocation in 8-byte aligned architectures 2017-03-14 20:01:45 +08:00
Gregory Nutt
4d33f26717 Update some comments 2017-03-12 12:33:44 -06:00
Gregory Nutt
d9cdb6c383 STM32; OTG host implementations of stm32_in_transfer() must obey the polling interval for the case of isochronous and itnerrupt endpoints. 2017-03-12 08:39:30 -06:00
Gregory Nutt
98a98a0c8b Minor change for consistency with a previous commit. 2017-03-12 07:20:10 -06:00
Gregory Nutt
9b11187b2a STM32 OTG HS: A little research reveals that only the F2 RCC initialization set the OTGHSULPIEN bit and Photon is the only F2 board configuration that uses OTG . Therefore, we can simplify the conditional logic of the last PR. Negative logic was used (#ifndef BOARD_DISABLE_USBOTG_HSULPI) to prevent bad settings in other configurations. But give these facts, the preferred positive logic now makes more sense (#ifdef BOARD_ENABLE_USBOTG_HSULPI). 2017-03-11 18:00:38 -06:00
Gregory Nutt
e0f7b9582a STM32: Review of last STM32 F2 PR. Progate changes to STM32 F4 and F7 OTGHS. Rename some configs/photon/src files. Naming can be either photon_ or stm32_ but must be consistent. 2017-03-11 16:31:11 -06:00
Simon Piriou
70d8f0189d stm32f20xxx: add BOARD_DISABLE_USBOTG_HSULPI flag 2017-03-11 18:15:18 +01:00
Gregory Nutt
aadf6c6e16 STM32 F33: Fix another error in ADC base address usage. 2017-03-10 17:49:32 -06:00
Gregory Nutt
852b189910 STM32 F33 ADC: Correct bad definitions of base addresses; Fix naming collision by changing colliding STM32_ADC12_BASE to STM32_ADC12_CMN_BASE 2017-03-10 17:46:19 -06:00
Gregory Nutt
24816cb08b All STM32 host drivers. In IN endpoint retry, delay for a clock tick to give some breathing space for the CPU. EXPERIMENTAL change. 2017-03-10 10:25:43 -06:00
David Sidrane
acaebb361b STM32, STM32 F7, and STM32 L4: Clone Freddie Chopin's I2C change to similar STM32 I2C drivers. 
Save elapsed time before handling I2C in stm32_i2c_sem_waitstop()
   This patch follows the same logic as in previous fix to
   stm32_i2c_sem_waitdone().
   It is possible that a context switch occurs after I2C registers are read
   but before elapsed time is saved in stm32_i2c_sem_waitstop(). It is then
   possible that the registers were read only once with "elapsed time"
   equal 0. When scheduler resumes this thread it is quite possible that
   now "elapsed time" will be well above timeout threshold. In that case
   the function returns and reports a timeout, even though the registers
   were not read "recently".
   Fix this by inverting the order of operations in the loop - save elapsed
   time before reading registers. This way a context switch anywhere in the
   loop will not cause an erroneous "timeout" error.
 2017-03-10 05:07:39 -10:00
Freddie Chopin
3cd66af889 ave elapsed time before handling I2C in stm32_i2c_sem_waitstop() 
This patch follows the same logic as in previous fix to
stm32_i2c_sem_waitdone().

It is possible that a context switch occurs after I2C registers are read
but before elapsed time is saved in stm32_i2c_sem_waitstop(). It is then
possible that the registers were read only once with "elapsed time"
equal 0. When scheduler resumes this thread it is quite possible that
now "elapsed time" will be well above timeout threshold. In that case
the function returns and reports a timeout, even though the registers
were not read "recently".

Fix this by inverting the order of operations in the loop - save elapsed
time before reading registers. This way a context switch anywhere in the
loop will not cause an erroneous "timeout" error.
 2017-03-10 07:35:10 -06:00
Gregory Nutt
9cd3f7f80a STM32, STM32 F7, STM32 L4: OTG host drivers: Do not do data toggle if interrupt transfer is NAKed. Sugested by webbbn@gmail.com 2017-03-09 15:07:31 -06:00
Simon Piriou
6768831851 Merged in spiriou/nuttx (pull request #257) 
STM32F2: add USB OTG HS support for stm32f20xxx cores

Approved-by: Gregory Nutt
 2017-03-09 20:06:12 +00:00
Gregory Nutt
04297d1b0f Update some comments 2017-03-09 13:57:37 -06:00
Gregory Nutt
a3b4475474 STM32, STM32 F7, and STM32 L4: Back out part of 3331e9c49a. Returning immediately int he case of a NAK makes the Mass Storage Class driver unreliable. The retry/timeout logic is necessary. This implementation tries to implement a compromise: If a NAK is received after some data is received, then the partial data received is returned as with 3331e9c49a. If if a NAK is received with no data, then no longer returns the NAK error immediately but retries until data is received or a timeout occurs. Initial testing indicates that this fixes the issues the MSC. However, I hae concerns that if multiple sectors are read in one transfer, there could be NAKs between sectors as well and, in that case, then change will still cause failures. 2017-03-09 13:49:25 -06:00
Simon Piriou
31aef4a9c0 STM32F2: add USB OTG HS support for stm32f20xxx cores 2017-03-09 20:30:32 +01:00
Gregory Nutt
ee5ae3a57d STM32, STM32 F7, and STM32 L4: Clone Freddie Chopin's I2C change to similar STM32 I2C drivers. 2017-03-09 07:37:52 -06:00
Freddie Chopin
5a6d95dd9f ave elapsed time before handling I2C in stm32_i2c_sem_waitdone() 
It is possible that a context switch occurs after stm32_i2c_isr() call
but before elapsed time is saved in stm32_i2c_sem_waitdone(). It is then
possible that the handling code was executed only once with "elapsed
time" equal 0. When scheduler resumes this thread it is quite possible
that now "elapsed time" will be well above timeout threshold. In that
case the function returns and reports a timeout, even though the
handling code was not executed "recently".

Fix this by inverting the order of operations in the loop - save elapsed
time before handling I2C. This way a context switch anywhere in the loop
will not cause an erroneous "timeout" error.
 2017-03-09 07:29:12 -06:00
Gregory Nutt
0631c1aafa STM32 OTGFS, STM32 L4 and F7: Adapt Janne Rosberg's patch to STM32 OTGHS host to OTGFS host, and to similar implements for L4 and F7. 2017-03-07 07:17:24 -06:00
Janne Rosberg
3331e9c49a STM32 OTGHS host: stm32_in_transfer() fails and returns NAK if a short transfer is received. This causes problems from class drivers like CDC/ACM where short packets are expected. In those protocols, any transfer may be terminated by sending short or NUL packet. 2017-03-07 06:58:59 -06:00
Gregory Nutt
d3408809e4 sendfile(): Fix error introduced with commit ff73be870e. Noted by Maciej Wójcik 2017-03-05 11:50:34 -06:00
raiden00pl
e9884216c5 stm32f33xxx: Add HRTIM header file 2017-03-05 18:10:59 +01:00
raiden00pl
46d62b1e09 stm32f33xxx: Add ADC header file 2017-03-04 19:40:14 +01:00
raiden00pl
b866ea0dd0 stm32f33xxx_memorymap.h: Add COMP and OPAMP base adress 2017-03-04 19:36:56 +01:00