## Summary
A lot of linker scripts were listed twice, once for unix, once for windows.
This PR cleans up the logic so they're only listed once.
## Impact
Any opportunity to use a single source of truth and reduce lines of code is a win!
## Testing
CI will test all build
Summary:
- Apply the same style as sabre-6quad
Impact:
- None
- NOTE: esp32c3-devkit still remains old style because of link errors
Testing:
- Build only
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
since the related code was removed by:
commit 4d5a964f29
Author: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
Date: Tue Feb 23 18:04:13 2021 +0800
net: unify socket into file descriptor
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
The image must be placed into:
boards/risc-v/mpfs/icicle/include/boot_romfsimg.h
The image is mounted by mpfs_bringup, which is run by the application
itself, or by board_late_initialize() in the case when
CONFIG_BOARD_LATE_INITIALIZE is defined, e.g. with CONFIG_BUILD_KERNEL
NOTE: THIS ONLY WORKS WHEN KERNEL RUNS IN M-MODE FOR NOW
This frees the PMP for other use, e.g. HART memory separation.
The page tables are statically allocated, 1 per level.
This feature is now behind CONFIG_MPFS_USE_MMU_AS_MPU, because
only the MPFS target supports this (others are not tested).
If the MMU is used for memory separation within a HART, the PMP must
still be configured to allow user access to the memory mapped for the
HART, because PMP *rekoves* access by default. At this point all of
the user memory as well as the kernel RAM are opened.
A more flexible solution for PMP configuration will follow.
The old implementation used the default ld.script for the kernel side
which did not obey the memory.ld limits whatsoever.
Also, provide the user space addresses from the linker script to get rid
of the pre-processor macros that define (incorrect) default values for
the user space composition.
Some of the configuration options have changed, so update this
config file accordingly.
In this example config, the following hart configuration takes
place:
hart1: 0xafb00000 (Another NuttX)
hart2: unused
hart3: 0x80200000 (u-boot and Linux kernel)
hart4: 0x80200000 (u-boot and Linux kernel)
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
There is no such section. Instead, place the object mpfs_head.o at the start of
the text.
Put mpfs_head.o directly into the arch library; there is no need to define
it separately in HEAD_ASRC.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Add the rest of the OpenSBI code to .text.sbi -section. They belong
to there. This frees up some space in the very limited eNVM.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
RAM is expected to start from 0x08000000, not from
0x80000000 in this case. DDR starts from 0x80000000.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Polarfire Icicle board has only (128K - 256) bytes for the bootloader
in the non-volatile eNVM. This space is barely enough for running NuttX.
If OpenSBI is selected, it will be placed in DDR. This all means the
nuttx.bin file grows into gigabyte size, filling the unused space (ddr -
envm) with zeroes.
The memory layout is as follows:
MEMORY
{
ddr (rx) : ORIGIN = 0x80000000, LENGTH = 4M
envm (rx) : ORIGIN = 0x20220100, LENGTH = 128K - 256
l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k
l2zerodevice (rwx) : ORIGIN = 0x0A000000, LENGTH = 512k
}
OpenSBI library is used as a separate binary, which is stored into
eMMC or SD-card. It is then loaded into its precise location in DDR.
Thus, we separate OpenSBI from NuttX and end up with two images
by utilizing the objcopy options:
--only-section=sectionpattern (-j in short)
--remove-section=sectionpattern (-R in short)
This is only valid when CONFIG_MPFS_OPENSBI is set.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Summary:
- I noticed that most of nsh commands are disabled by default
due to the recent changes for CONFIG_MM_SMALL=y in apps.
- This commit re-enables some nsh commands.
Impact:
- None
Testing:
- Tested with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Add a pinmap header for mpfs to be able to configure MSSIO GPIOs
This also adds Kconfigs for some different chip/package types of the PolarFire SOC
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This fixes problems with DDR training sequence on aries m100pfs board
- Set LIBERO_SETTING_RPC_ODT_* to 6, which matches 40 ohm. Originally it was 120 ohm (2)
- Set BCLKSCLK_OFFSET value to 5, which matches icicle board setting
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Update the cache settings for the Aries m100pfsevp board. This
assigns scratchpad ways for this board as well, as seen in the
commit 491ae6c.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
