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17617 Commits

Author SHA1 Message Date
Xiang Xiao
2335b69120 arch: Allocate the space from the beginning in up_stack_frame 
arch: Allocate the space from the beginning in up_stack_frame

and modify the affected portion:
1.Correct the stack dump and check
2.Allocate tls_info_s by up_stack_frame too
3.Move the stack fork allocation from arch to sched

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-16 12:41:41 +09:00
Xiang Xiao
8640d82ce0 arch: Rename g_intstackbase to g_intstacktop 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-16 12:41:41 +09:00
David Sidrane
3feb3a247d stm32:Serial DMA config USART{4578} -> UART{4578} 2021-04-15 21:26:32 -05:00
raiden00pl
82ce1de7cd stm32/stm32_foc: remove the debug message before the calibration start 
For unknown reasons this message may interferre with the calibration
procedure and result in invalid calibariton data.
We leave only a message informing about the end of the the calibration.
The problem was observed for STM32G4 + IHM16M1.
 2021-04-15 06:37:15 -05:00
raiden00pl
13f62d15cc stm32/stm32_foc: do not enable PWM outputs that are not in use 2021-04-15 06:37:15 -05:00
YAMAMOTO Takashi
3806803a7a arch/xtensa/src/esp32/esp32_user.c: Implement L16SI emulation 
I don't know why this was not necessary before.
Probably I was just lucky about the combination of configs.
Or maybe some of recent changes happened to make the compiler
to use the instruction.

```
400d38f0 <mm_givesemaphore>:
400d38f0:       004136          entry   a1, 32
400d38f3:       228c            beqz.n  a2, 400d38f9 <mm_givesemaphore+0x9>
400d38f5:       0228            l32i.n  a2, a2, 0
400d38f7:       52cc            bnez.n  a2, 400d3900 <mm_givesemaphore+0x10>
400d38f9:       fea0b2          movi    a11, 254
400d38fc:       000306          j       400d390c <mm_givesemaphore+0x1c>
400d38ff:       00              .byte 00
400d3900:       019232          l16si   a3, a2, 2
400d3903:       feebe5          call8   400d27c0 <getpid>
400d3906:       0813a7          beq     a3, a10, 400d3912 <mm_givesemaphore+0x22>
400d3909:       05a1b2          movi    a11, 0x105
400d390c:       f241a1          l32r    a10, 400d0210 <_stext+0x1f0>
400d390f:       ff23e5          call8   400d2b4c <_assert>
400d3912:       1288            l32i.n  a8, a2, 4
400d3914:       0828a6          blti    a8, 2, 400d3920 <mm_givesemaphore+0x30>
400d3917:       880b            addi.n  a8, a8, -1
400d3919:       1289            s32i.n  a8, a2, 4
400d391b:       000606          j       400d3937 <mm_givesemaphore+0x47>
400d391e:       00              .byte 00
400d391f:       00              .byte 00
400d3920:       ffaf82          movi    a8, -1
400d3923:       015282          s16i    a8, a2, 2
400d3926:       00a082          movi    a8, 0
400d3929:       016282          s32i    a8, a2, 4
400d392c:       02ad            mov.n   a10, a2
400d392e:       feb125          call8   400d2440 <sem_post>
400d3931:       19a1b2          movi    a11, 0x119
400d3934:       fd4a96          bltz    a10, 400d390c <mm_givesemaphore+0x1c>
400d3937:       f01d            retw.n
400d3939:       000000          ill
```
 2021-04-15 12:18:52 +01:00
YAMAMOTO Takashi
a28de1d681 arch/xtensa/src/esp32/esp32_user.c: Fix S16I/L16LU emulation 
I misunderstood how imm8 is used to calculate the address.
 2021-04-15 12:18:52 +01:00
Anthony Merlino
b1f637a6ea stm32h7: Don't automatically select HSI48 as it may depend on USBSEL. 
Add preprocessor logic that can catch the condition where the board is selecting the HSI48 as the USBSEL source, but the HSI48 isn't enabled.
 2021-04-15 02:00:37 -07:00
Anthony Merlino
4c8d70dd2e stm32h7: Initialize CSI and HSI48 clocks as needed based on enabled peripherals. 2021-04-15 02:00:37 -07:00
YAMAMOTO Takashi
51490bad55 modlib: Implement sh_addralign handling 
I've seen a module with 16 bytes .rodata alignment for xmm operations.
It was getting SEGV on sim/Linux because of the alignment issue.
The same module binary seems working fine after applying this patch.

Also, tested on sim/macOS and esp32 on qemu,
using a module with an artificially large alignment. (64 bytes)
 2021-04-14 21:17:07 -05:00
jturnsek
33b071ecb9 MIMXRT1064-EVK support 2021-04-14 14:57:26 -07:00
raiden00pl
ad8c09d0a1 stm32: include support for TIMERS_V3 2021-04-14 10:53:50 -04:00
raiden00pl
7c11397469 stm32: add definitions for TIMERS_V3. All credit goes to Nathan Hartman (hartmannathan) 2021-04-14 10:53:50 -04:00
raiden00pl
6d69600905 stm32/Kconfig: move configuration common for G4 under STM32_STM32G4XXX option 2021-04-14 10:53:50 -04:00
Marco Krahl
8456f3615e drivers/1wire: Moves header and adjusts include paths 
Moves header to 1wire include sub directory.
Moves over common crc definitions to new interface.

Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
 2021-04-14 02:49:28 -05:00
raiden00pl
beebb57445 stm32g4xx: add support for FOC 2021-04-13 14:38:28 -05:00
raiden00pl
835b129c94 stm32g4xx: add DBGMCU definitions 2021-04-13 14:38:28 -05:00
Anthony Merlino
9c8c2b0db2 Separate CLOCK_TIMEKEEPING and SCHED_TICKLESS. 2021-04-13 11:42:31 -05:00
raiden00pl
c90a6bdf2b stm32/Kconfig: enable ADCx DMA support if DMAMUX enabled 2021-04-13 12:08:17 -03:00
raiden00pl
bf04ef9a3c stm32g4: add support for DMA (DMAMUX) 2021-04-13 12:08:17 -03:00
raiden00pl
fbb7e95ebf stm32g4xxxx_dmamux.h: rename defs to match other chips and add DMAMAP defs 2021-04-13 09:20:18 -05:00
raiden00pl
a735252d78 stm32h7,stm32g0: fix typos in DMAMUX 2021-04-13 09:20:18 -05:00
raiden00pl
62001bff3b stm32g4xx: add support for PWM 2021-04-13 09:19:52 -05:00
raiden00pl
4c741bc9a5 stm32/Kconfig: G4 chips use TIMERS_V2 2021-04-13 09:19:52 -05:00
raiden00pl
ff2ae3e894 stm32g4xx: add support for ADC 2021-04-13 09:29:09 -03:00
Alin Jerpelea
20d315abfe NuttX: Falker Atomacao Agrícola Ltda: update licenses to Apache 
Falker Atomacao Agrícola Ltda has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-13 05:28:28 -05:00
Anthony Merlino
1a5a7a1b63 stm32h7: Allow OTGHS to use internal FS PHY 2021-04-12 23:21:34 -05:00
Jukka Laitinen
3f6bb76e01 arch/arm/src/stm32f7/stm32_allocateheap.c: Fix MPU alignments 
Change the logic for allocating user heap for PROTECTED_BUILD:
- Don't rely on SRAM1_END alignment
- Make better use of MPU subregions when allocating the heap
- Don't duplicate the calculation of user heap start in kernel heap
  allocation; use the previous calculation directly

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-04-12 23:20:18 -05:00
Jukka Laitinen
ea36c2c7ea Remove MPU_RASR_S bit from stm32f7 MPU user mode intsram configration 
For some reason, setting the "shareable" bit makes the SRAM not writable

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-04-12 23:20:18 -05:00
Xiang Xiao
3f9908f7d1 Remove the unnecessary math.h inclusion 
or move from header file to source file since math.h doesn't always exist

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-12 22:58:23 -04:00
Anthony Merlino
2b46a0fdde stm32h7: Adds guards around stm32_iocompensation. 2021-04-12 15:08:52 -07:00
Anthony Merlino
a45b8cc17c stm32h7: Add support for IO compensation. 2021-04-12 15:08:52 -07:00
jturnsek
bbe875876d Modified FlexSPI driver 2021-04-12 17:22:14 -03:00
jturnsek
7453e76d98 FlexSPI NOR driver 2021-04-12 11:35:44 -03:00
Dong Heng
31854ca135 riscv/esp32c3: Fix heap end address 2021-04-12 01:36:11 -05:00
Masayuki Ishikawa
7ce1033aa2 arch: k210: Fix interrupt stack corruption in SMP mode 
Summary:
- I noticed that stack corruption happens due to recent refactoring
- This commit fixes this issue

Impact:
- SMP only

Testing:
- Tested with maix-bit:smp (QMU and dev board)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-04-11 13:00:40 -05:00
Alan Carvalho
ac5fb7d701 esp32: Fix GPIO Pull-Up/Pull-Down using RTC GPIO 
Some ESP32 GPIO pins (2, 4, 12, 13, 25, 27, 32) weren't accepting
pull-up/pull-down resistors. These pins are RTC GPIO pins and need
to have pull-up/pull-down configured in the RTC registers.

Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-04-11 14:36:02 +01:00
raiden00pl
cf645fc9ba arch/arm/src/stm32/stm32_foc.c: add modifications to support STM32F1 
- generalize DBGMCU for PWM timer
- use ADC common data only if coupled ADC present
- rename some ADC definitions that collide with stm32_adc.h
 2021-04-11 03:52:21 -05:00
raiden00pl
021a89569d arch/arm/src/stm32: introduce DBGMCU IP core versions 2021-04-11 03:52:21 -05:00
raiden00pl
3caf26fe3e arch/arm/src/stm32/stm32_adc.c: support adc_inj_startconv also for STM32F1 2021-04-11 03:52:21 -05:00
Anthony Merlino
2aa2b7669f stm32f7 tickless: Fix handling of overflow for different width timers. 2021-04-10 23:38:16 -05:00
Anthony Merlino
f979dd72c1 stm32/stm32f7 tickless: Fix clearing and checking of interrupts. 2021-04-10 23:38:16 -05:00
Anthony Merlino
dd00c6427e stm32 tickless: Fixes printf warnings 2021-04-10 23:38:16 -05:00
Xiang Xiao
3f67c67aaf arch: Fix the stack boundary calculation and check 
All supported arch uses a push-down stack:
The stack grows toward lower addresses in memory. The stack pointer
register points to the lowest, valid working address (the "top" of
the stack). Items on the stack are referenced as positive(include zero)
word offsets from sp.
Which means that for stack in the [begin, begin + size):
1.The initial SP point to begin + size
2.push equals sub and then store
3.pop equals load and then add

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-10 08:39:54 -07:00
Alin Jerpelea
7424683d29 arch: lpc17xx_40xx: Mixed Case Identifier fix 
Fix for Mixed Case Identifier reported by nxstyle.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-10 06:46:32 -05:00
Alin Jerpelea
6f5537eae2 arch: lpc2378: Fix for Mixed Case Identifier errors 
Fix for Mixed Case Identifier errors reported by nxstyle tool

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-10 06:46:32 -05:00
Alin Jerpelea
08612337f6 NuttX: nxstyle fixes 
nxstyle fixes to pass CI.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-10 06:42:19 -05:00
Alin Jerpelea
eac1d28aae NuttX: Janne Rosberg: update licenses to Apache 
Janne Rosberg has submitted the ICLA and we can migrate the licenses
 to Apache.

David Sidrane has submitted the ICLA and we can migrate the licenses
 to Apache.

Ivan Ucherdzhiev has submitted the ICLA and we can migrate the licenses
 to Apache.

Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-10 06:42:19 -05:00
Alin Jerpelea
a2813b142f NuttX: Jose Pablo Carballo: update licenses to Apache 
Jose Pablo Carballo has submitted the ICLA and we can migrate the licenses
 to Apache.

Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-10 06:42:19 -05:00
Alin Jerpelea
231b8518b7 NuttX: Ken Pettit: update licenses to Apache 
Ken Pettit has submitted the ICLA and we can migrate the licenses
 to Apache.

Sebastien Lorquet has submitted the ICLA and we can migrate the licenses
 to Apache.

Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-10 06:42:19 -05:00
Xiang Xiao
0fdde5be26 arch/esp32: Fix error: Mixed case identifier found 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-10 12:00:06 +01:00
Alin Jerpelea
3c939c42fb arch: x86: Mixed Case Identifier fix 
Fix for Mixed Case Identifier reported by nxstyle tool

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-09 08:04:41 -05:00
Alin Jerpelea
3b576758f1 arch: z80: nxstyle fixes 
Fix for TABs and Mixed Case identifiers reported by nxstyle

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-09 08:04:41 -05:00
chenwen
4ca34ac5b5 risc-v/esp32c3: Fix the issue of getting wrong Wi-Fi password 2021-04-09 03:44:29 -05:00
Anthony Merlino
d37275f348 stm32f7: Freeze tickless timer during debug halt. 2021-04-08 23:38:00 -05:00
Gustavo Henrique Nihei
4d4250fcca xtensa/esp32: Improve SPI polling to use the entire HW buffer 2021-04-08 23:36:28 -05:00
chenwen
a41d37cffd arch/risc-v/src/common/riscv_initialize.c: Add telnet_initialize to riscv's up_initialize 2021-04-08 23:18:32 -05:00
Alin Jerpelea
e1d8b62209 arch: lpc43xx: spifilib_fam_standard_cmd.c: fix nxstyle errors 
fix errors reported by nxstyle tool

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-08 22:49:09 -05:00
Alin Jerpelea
42d17dcaf4 arch: lpc43xx: Mixed Case Identifier fix 
Fix for Mixed Case Identifier reported by nxstyle tool.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-08 22:48:46 -05:00
Alin Jerpelea
602d384325 arch: tms570: fix Mixed Case Identifier 
Fix Mixed Case Identifier reported by nxstyle tool

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-08 22:48:46 -05:00
Alin Jerpelea
37b314f29f LICENSE: add 3rd party license for Texas Instruments Incorporated 
Add 3rd party licenses for Texas Instruments Incorporated to the LICENSE file.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-08 22:48:46 -05:00
Alin Jerpelea
12aebdf1a6 LICENSE: add 3rd party license for Infineon Technologies AG 
Add 3rd party licenses for Infineon Technologies AG to the LICENSE file.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-08 22:48:46 -05:00
Alin Jerpelea
8dcd16d5a6 arch: arm: nxstyle fixes 
Fixes for nxstyle warnigs

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-08 22:48:46 -05:00
Alin Jerpelea
d2e7ea05c6 NuttX: typo fix 
Yype fix for Public Functions reported by nxstyle

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-08 22:48:46 -05:00
Alin Jerpelea
628d8ca9e1 arch: mips: nxstyle fixes 
fixes for errors reported by nxstyle

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-08 11:41:02 -03:00
Xiang Xiao
27425f3035 arch/z80: Remove the temporary file ez80_serial.c.SAVE 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-08 11:07:12 +02:00
Masayuki Ishikawa
445770a600 arch: sim: Refactor signal handling 
Summary:
- This commit refactors signal handling logic

Impact:
- None

Testing:
- Tested with sim:smp and sim:ostest

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-04-08 01:59:31 -05:00
Matias N
ab206687bb Replace wrong inclusion of sys/errno.h (toolchain provided) with errno.h 2021-04-07 21:27:06 -05:00
Alin Jerpelea
cb2ecefbf1 arch: xtensa: fix nxstyle errors 
Fix for errors reported by nxstyle tool

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-07 21:21:51 -05:00
Alin Jerpelea
bc5f0092f1 arch: x86: fix Mixed Case errors 
Fix for Mixed Case errors reported by the nxstyle tool

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-07 21:21:51 -05:00
Gregory Nutt
a9e2195e65 Remove unused 'running' field from freerun lower half drivers. 
That field is never used and, in most cases, is never initialized correctly.

This should have no impact to anything with the possible exception of free-running drivers.

Verified using CI builds only.
 2021-04-07 20:35:50 -03:00
Matias N
d88b5aac97 esp32: move common XTAL and RUN_IRAM configs to ESP32 KConfig 2021-04-07 21:45:48 +01:00
Alin Jerpelea
2c4e9e7664 arch: x86_64: fix Mixed Case errors 
Fix for Mixed Case errors reported by nxstyle tool

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-07 10:48:26 -05:00
Alin Jerpelea
72fb895d41 arch: x86_64: fix nxstyle errors 
Fix for errors reported by nxstyle tool

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-07 10:48:26 -05:00
Alin Jerpelea
abdc60e72f arch: samXX: Gregory Nutt: update licenses to Apache 
Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-07 06:43:20 -05:00
Alin Jerpelea
9be2db897d arch: sam: move references from License header 
for compliance references should be moved after the license header

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-07 06:43:20 -05:00
Alin Jerpelea
74cde4f9bf arch: armv7-r: Gregory Nutt: update licenses to Apache 
Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-07 06:43:20 -05:00
Alin Jerpelea
68cd957c62 arch: armv7-r: move references from License header 
for compliance references should be moved after the license header

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-07 06:43:20 -05:00
Alin Jerpelea
ce08e0ca6c arch: armv7-a: move references from License header 
for compliance references should be moved after the license header

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-07 06:43:20 -05:00
Xiang Xiao
bfbe705e3f arch/arm: Fix nxstyle warning 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-07 16:18:27 +09:00
Xiang Xiao
eeb8931c04 arch/arm: align arm vector related code with armv7-a 
commit 3c30c8b90b
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date:   Tue Apr 6 15:47:27 2021 +0800

    arch/arm: Remove g_irqtmp, g_undeftmp and g_aborttmp

    to avoid multiple CPU access them concurrently in SMP case

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-07 16:18:27 +09:00
Xiang Xiao
0779f34390 arch/arm: Add PSR_ prefix to the mode state like armv7-a 
no real function change

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-07 16:18:27 +09:00
Anthony Merlino
01fabe6c67 stm32h7: Actually use the AXI SRAM as the main heap as the documentation describes. 
The comments at the top of the file say this:
```
This will be automatically registered
 * - AXI SRAM is a 512kb memory area. This will be automatically registered
 *      with the system heap in up_allocate_heap, all the other memory
 *      regions will be registered in arm_addregion().
```

but the implementation was using SRAM123 instead. Furthermore, arm_addregion then re-adds SRAM123 again.
 2021-04-06 22:47:20 -05:00
Anthony Merlino
d69cd4ba03 stm32h7: Adds stm32_dbgmcu.h to match stm32f7 port. 2021-04-06 22:44:07 -05:00
Anthony Merlino
3a10f88bdf stm32h7: Fixes bug in stm32_sdmmc.c where DCACHE guards were blocking a needed variable. 2021-04-06 22:43:27 -05:00
Anthony Merlino
068e71d0c6 stm32h7: Expose flash lock, unlock, and write protect functions to boards. 2021-04-06 22:42:52 -05:00
Anthony Merlino
8c73ea68d6 stm32f7: Remove the one and only reference to STM32_BOARD_HCLK. 2021-04-06 22:42:06 -05:00
Xiang Xiao
a7f7796db1 arch/arm: Change all spsr_cxsf to spsr 
unify the SPSR register usage

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-07 06:44:37 +09:00
Alin Jerpelea
72041911ce NuttX: Marco Krahl: update licenses to Apache 
Marco Krahl has submitted the ICLA and we can migrate the licenses
 to Apache.

Gregory Nutt, S.A has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-06 12:50:41 -05:00
Sara Souza
0926e7c578 risc-v/esp32-c3: Fixes gargabe UART issue, refactors serial driver, changes default pins of UART 1 and fixes low baud rate issue. 2021-04-06 11:44:06 -03:00
Xiang Xiao
3c30c8b90b arch/arm: Remove g_irqtmp, g_undeftmp and g_aborttmp 
to avoid multiple CPU access them concurrently in SMP case

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-06 22:45:51 +09:00
Xiang Xiao
822bb3ff78 arch/armv7-r: Add FIQ stack CONFIG_ARCH_INTERRUPTSTACK > 7 
just like what has done on armv7-a

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-06 22:45:51 +09:00
Fotis Panagiotopoulos
1dee243e29 syslog: Added multi device support in syslog_device. 2021-04-06 07:32:23 -05:00
Xiang Xiao
7d3266461b arch/armv7-a: Remove the special process of the nest level 
it shouldn't need anymore

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-06 17:07:46 +09:00
Anthony Merlino
b21cb3308a Fixes race condition in event wait logic of SDMMC driver. 
This change makes it so that the timeout is set as part of the SDIO_WAITENABLE call instead of the SDIO_EVENTWAIT call. By doing so, you eliminate all opportunity for a race condition.

stm32h7:sdmmc Check if busy ended early
 2021-04-05 23:08:45 -05:00
Xiang Xiao
807d4490da arch/arm: Minor style fix 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-05 13:19:20 -07:00
Xiang Xiao
39fc9325cf arch/arm: Replace "b lr" or "mov pc, lr" with "bx lr" 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-05 05:50:14 -07:00
Xiang Xiao
be50a24e3d arch/arm: Clear .bss section after copying .data section 
to avoid batch copy(32 bytes) overwrite the zeroed .bss section

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-05 05:48:20 -07:00
Xiang Xiao
d1e06b4c09 arch/arm: Call arm_lowputc after SP setup 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-05 05:48:20 -07:00
Xiang Xiao
dd1d980c3a arch/sim: Move setjmp/longjmp to libc/machine/sim 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-05 09:00:42 -03:00