Commit Graph

51983 Commits

Author SHA1 Message Date
guoshichao
8c37c3841b libs/libc/wchar: add fgetwc implementation
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2023-12-17 01:39:06 -08:00
Yanfeng Liu
75d0c2946d risc-v: Initial support for CanMV-k230 board and K230 chip
The code is mainly derived from the NuttX qemu-rv/rv-virt codebase.

Major changes:

- boards/Kconfig:       add new BOARD_K230_CANMV
- arch/risc-v/Kconfig:  add new CHIP_K230 chip and ARCH_RV_MMIO_BITS
- arch/risc-v/src/common/riscv_mtimer.c: use ARCH_RV_MMIO_BITS to
                        select MMIO access width

New additions:

- arch/risc-v/include/k230/: k230 SoC definitions
- arch/risc-v/src/k230/:     k230 SoC sources
- boards/risc-v/k230/canmv230/:  CanMV-K230 board sources and configs
- Documentation/platforms/risc-v/k230/: simple doc

Note that only FLAT build works for canmv230 now.

This PR has changes in RiscV common layer thus may affect other RiscV ports
It changes the mtime/mtimecmp access control from using config ARCH_RV64 to
newly intorduced config ARCH_RV_MMIO_BITS.

Original design uses ARCH_RV64 to select 64bit MMIO in riscv_mtimer.c, this
can't cope with the situation with K230 --- it has ARCH_RV64 but only can do
32bit MMIO. So a new ARCH_RV_MMIO_BITS config has been introduced. Its value
depicts the MMIO width in bits. The MMIO_BITS defaults to 32/64 for RV32/
RV64 respectively. This allows the macro to replace current use of ARCH_RV64
in riscv_mtimer.c.

The new MMIO_BITS config is a derived one, and for RiscV chips with
equal CPU and MMIO widths there is no need to explicitly set it as the
default rule will do that. Only chips with different CPU and MMIO widths
need set it in Kconfig.

So by design this change should be safe but RiscV ports should be checked.

"ostest" verification has been done for:

- canmv230/nsh
- rv-vivt/nsh
- rv-virt/nsh64

configuration generation and manual check of derived RV_MMIO_BITS has been
done for:

- star64/nsh
- arty_a7/nsh
- bl602evb/nsh

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2023-12-17 01:10:57 -08:00
raiden00pl
751bc1528a cmake: restore old behavior for savedefconfig
savedefconfig shouldn't overwrite the original defconfig, but only create a new
defconfig in the current directory. Otherwise, creating new configs based on
existing ones becomes irritating, because every time we use savedefconfig,
the original configuration is overwritten which is not the excepted behavior
2023-12-16 07:12:08 -08:00
Zhe Weng
5aeb15469a netdev/ipv6: Move xxx_ipv6multicast from arch to common code
The `xxx_ipv6multicast` function in each driver is not adapted to
multiple IPv6 addresses yet, and they're redundant, so try to take them
into common code.

Change:
1. Add MAC `g_ipv6_ethallnodes` and `g_ipv6_ethallrouters` in
   `icmpv6_devinit` and call them in `netdev_register`
2. Add multicast MAC for Neighbor Solicitation when adding any IPv6
   address, and remove them when IPv6 address is removed
3. Select `NET_MCASTGROUP` when `NET_ICMPv6` because now we need
   `d_addmac` when we have ICMPv6

Note:
We want modules outside net stack to call functions like
`netdev_ipv6_add` and never touch the related MAC address, so these MAC
functions are added as internal functions to `net/netdev/netdev.h`

Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
2023-12-16 05:26:16 -08:00
Petteri Aimonen
06e5b661ed tcp: Recover from iob shortage with TCP_WRITE_BUFFERS
When CONFIG_NET_TCP_WRITE_BUFFERS is enabled, iobs are used for
both queuing data from application, and for assembling packets
for sending. If there is a system-wide shortage of iobs, it could
happen that there is not enough free space to form any packets
to send. The buffers allocated for TCP data also can't be released
until the packet is sent.

Normally this should be avoided by setting suitable values for
CONFIG_IOB_NBUFFERS and CONFIG_IOB_THROTTLE. The default values
are ok for light usage, but can run out when using multiple
simultaneous TCP streams.

Before this commit, iob shortage would cause TCP connections to
get stuck and eventually timeout. With this change, TCP stack
sends smaller packets, eventually freeing some buffers from the
write queue.
2023-12-15 20:12:13 -08:00
Lee Lup Yuen
87c1b81857 boards/riscv: Add support for PINE64 Ox64 BL808 SBC
This PR adds support for PINE64 Ox64 64-bit RISC-V SBC, based on Bouffalo Lab BL808 SoC (T-Head C906 Core). Most of the code is derived from NuttX for Star64 JH7110. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64

### Modified Files

`boards/Kconfig`: Added Ox64 board

### New Files in boards/risc-v/bl808/ox64

`src/bl808_appinit.c`: Startup Code

`include/board.h`: Ox64 Definitions

`include/board_memorymap.h`: Memory Map

`src/etc/init.d/rc.sysinit`, `rcS`: Startup Script

`src/.gitignore`: Ignore the tmp filesystem

`scripts/ld.script`: Linker Script

`scripts/Make.defs`: Ox64 Makefile

`src/Makefile`: Ox64 Makefile

`Kconfig`: Ox64 Config

`configs/nsh/defconfig`: Build Config for `ox64:nsh`

### Updated Documentation

`platforms/risc-v/bl808/index.rst`: New page for Bouffalo Lab BL808 SoC

`platforms/risc-v/bl808/boards/ox64/index.rst`: Building and booting NuttX for Ox64

`platforms/risc-v/jh7110/boards/star64/index.rst`: Fix typo
2023-12-15 18:52:16 -08:00
liqinhui
98e3615b60 net/netdev: Modify the logic for setting the IFF_RUNNING status of interfaces.
Refer to the logic of the `netif_carrier_on` on linux.
https://github.com/torvalds/linux/blob/master/net/sched/sch_generic.c#L575

Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2023-12-15 18:24:23 -08:00
Ville Juven
986a79b231 mpfs_pmpcfg: Move PMPCFG registers to common location 2023-12-15 18:22:26 -08:00
Ville Juven
baea0012e7 mpfs_usb.c: Use kernel memory instead of user memory for DMA
DMA directly to user (virtual) memory won't work, as the DMA engine(s)
don't do address translations, i.e. they require a physical address.

Using kernel heap is fine as it is mapped vaddr=paddr. Also, the USB DMA
engine does not have any alignment requirements.
2023-12-15 18:21:03 -08:00
Ville Juven
fbd8a2127a mpfs_ethernet.c: Remove DMA_ENABLE hack
The hack just opens the entire SoC memory unconditionally, which is not
a good idea.

Test features can be used ad-hoc, they don't need to be supported by the
build.
2023-12-15 18:20:34 -08:00
yuanyongjian
9483729328 syslog/ramlog.c:Syslog add BIOC_FLUSH supports clearing log cache
Signed-off-by: yuanyongjian <yuanyongjian@xiaomi.com>
2023-12-14 20:50:44 -08:00
Xiang Xiao
a0813b808f syslog/ramlog: Replace mutex with spinlock
and optimize the critical section usage
1.Remove the unnecessary critical section in ramlog_readnotify
2.Move the enter/leave critical section out of ramlog_pollnotify loop
3.Move the critical section of ramlog_addchar to caller

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-12-14 20:50:44 -08:00
yuanyongjian
046dd38c55 syslog/ramlog: Syslog supports multi-readers.
Signed-off-by: yuanyongjian <yuanyongjian@xiaomi.com>
2023-12-14 20:50:44 -08:00
yuanyongjian
0da8755fbc syslog/ramlog:Add tags to distinguish between hot start and cold start
Signed-off-by: yuanyongjian <yuanyongjian@xiaomi.com>
2023-12-14 20:50:44 -08:00
Xiang Xiao
e920883458 syslog/ramlog: Prepare to support the multiple reader
1.Remove RAMLOG_OVERWRITE option and related code
2.Broadcast the readability to all reader and poller

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-12-14 20:50:44 -08:00
liqinhui
6a8c638d57 qemu/wifi: Add the virtual wifi function on the emulator.
-The qemu wifi fucntion only supports the STA mode and the following
 operations:
 wapi mode wlan0 2
 wapi scan wlan0
 wapi psk wlan0 password 3
 wapi essid wlan0 wifi_name 1
 wapi show wlan0
 wapi disconnect wlan0
-Eanble the virtual wifi function with the MACRO `CONFIG_DRIVERS_WIFI_SIM`.

Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2023-12-14 20:22:12 -08:00
simbit18
c494ce4a96 Update kconfig2html.c
Fix nuttx coding style
2023-12-14 20:02:52 -08:00
Ville Juven
e03599d9ae libs/log2ceil: Move implementation of log2ceil to a common place
Move log2ceil from riscv_pmp to libc. Also, implement log2floor for
completeness.

These are the run-time alternative to the compile-time macros.
2023-12-14 08:46:12 -08:00
Ville Juven
90d73153fb riscv/arch_elf: Check for _HI20 relocation validity
As pointed out in #11322 there is a hardware design issue in RISC-V that
affects RV64 relocations. The problem is with how address bits are loaded
into registers via lui / auipc and sign extension.

If the hi20 relocation value happens to have its 32-bit sign bit set, i.e.
value is 0x80000000 (but not negative! i.e. negative in 64-bit format) the
relocation will fail, as the address is erroneously sign extended:

0x00000000_80000000 becomes 0xffffffff_80000000 which is not correct.

Also, make sure the correct opcode is used with PCREL_HI20, it expects
AUIPC (not LUI). The C compiler will never emit such code but when hand-
writing assembly code this can happen.
2023-12-14 06:54:17 -08:00
Masayuki Ishikawa
80ca3e9308 boards: rv-virt: Add virtio-sound
Summary:
- Add virtio-sound to the following configs
  netnsh, netnsh_smp, netnsh64, netnsh64_smp

Impact:
- None

Testing:
- nxplayer works on qemu-8.2.0-rc3 (ubuntu-20.04 amd64)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-12-14 20:01:25 +08:00
Masayuki Ishikawa
659c9e7f4b boards: qemu-armv8a: Add virtio-sound
Summary:
- Add virtio-sound to the following configs
  netnsh, netnsh_smp, netnsh_hv, netnsh_smp_hv

Impact:
- None

Testing:
- nxplayer works on qemu-8.2.0-rc3 (ubuntu-20.04 amd64, macOS13.6 M1/MBP)
- NOTE: raspi3b+ (ubuntu-20.04 server) has a noise issue

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-12-14 20:01:25 +08:00
Peter van der Perk
7730201689 imxrt: Extend FlexIO support to 117x 2023-12-14 03:59:36 -08:00
zhanghongyu
68a6f1090c libcxx.cmake: remove useless code
removes test code that was accidentally incorporated earlier.

Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2023-12-14 03:02:15 -08:00
GD32-MCU
9a2569882e fix bug in gd32f4xx_serial.c, add romfsimg.h, gd32f4xx_reset and improve gd32f4xx_gpio.c for f470z board, add board decription for f470
add gd32f470 picture
2023-12-13 23:27:23 -08:00
jianglianfang
5f631e2b2b virtio-gpu: convert virito-gpu fb_register to virtio_gpu_fb_register
Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
2023-12-13 09:05:17 -08:00
simbit18
9d50d180b1 Fix nuttx coding style
Remove spaces
Remove extra */
2023-12-13 17:29:08 +01:00
Petteri Aimonen
c3a234fe99 ipv6: Fix source address with many addresses in same network
Previously ipv6 multi-address support decided packet source
address based on its destination. This doesn't work if NuttX
device has multiple addresses within same subnet.

Instead when a packet is a response to existing connection,
the source address should be based on the destination address
used in the received packet.
2023-12-13 06:13:25 -08:00
liqinhui
73ceb049af virtio-net: Support for setting MAC addresses of the virtio-net interfaces.
Refers to https://docs.oasis-open.org/virtio/virtio/v1.2/cs01/virtio-v1.2-cs01.html#x1-2230004
A driver SHOULD negotiate VIRTIO_NET_F_MAC if the device offers it.
If the driver negotiates the VIRTIO_NET_F_MAC feature, the driver MUST
set the physical address of the NIC to mac. Otherwise, it SHOULD use a
locally-administered MAC address.

Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2023-12-13 05:00:59 -08:00
liqinhui
681b84b15d openamp: Add the virtio_negotiate_features interface for virtio-net.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2023-12-13 05:00:59 -08:00
chenwen@espressif.com
62a6a0ab4d xtensa/esp32s3: Tasks use SPIRAM as stack can do SPI flash read/write/erase/map/unmap
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2023-12-12 22:10:38 -08:00
Ville Juven
996625ec58 riscv/arch_elf.c: Handle PCREL_HI20/LO12_I/S relocations correctly
There is a problem with the current elf loader for risc-v: when a pair of
PCREL_HI20 / LO12 relocations are encountered, it is assumed that these
will follow each other immediately, as follows:

label:
	auipc      a0, %pcrel_hi(symbol)    // R_RISCV_PCREL_HI20
	load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S

With this assumption, the hi/lo relocations are both done when a hi20
relocation entry is encountered, first to the current instruction (addr)
and to the next instruction (addr + 4).

However, this assumption is wrong. There is nothing in the elf relocation
specification[1] that mandates this. Thus, the hi/lo relocation always
needs to first fixup the hi-part, and when the lo-part is encountered, it
needs to find the corresponding hi relocation entry, via the given "label".
This necessitates (re-)visiting the relocation entries for the current
section as well as looking for "label" in the symbol table.

The NuttX elf loader does not allow such operations to be done in the
machine specific part, so this patch fixes the relocation issue by
introducing an architecture specific cache for the hi20 relocation and
symbol table entries. When a lo12 relocation is encountered, the cache
can be consulted to find the hi20 part.

[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
2023-12-12 17:32:36 -08:00
raiden00pl
267d039295 cmake: NUTTX_COMMON_DIR must be set after .config definitions are included
otherwise NUTTX_COMMON_DIR is empty if CONFIG_ARCH_BOARD_COMMON is set from menuconfig

Co-authored-by: hartmannathan <59230071+hartmannathan@users.noreply.github.com>
2023-12-12 16:48:08 -03:00
Ville Juven
7bcbaa5dc7 riscv_pmp.c: Revert LOG2_CEIL back to run-time log2ceil function
The macro LOG2_CEIL is intended to be used in the pre-processor phase. If
used run-time it will generate a massive amount of extra code (~3.5K) which
is a problem, as the PMP configuration is quite often executed from a first
stage bootloader with a limited amount of code memory.

Code size differences pre- and post:

Memory region         Used Size  Region Size  %age Used
            envm:      112064 B     112384 B     99.72%

Memory region         Used Size  Region Size  %age Used
            envm:      108952 B     112384 B     96.95%
2023-12-12 08:51:14 -08:00
Lee Lup Yuen
614570cdcb arch/riscv: Add support for Bouffalo Lab BL808 SoC (T-Head C906)
This PR adds support for the Bouffalo Lab BL808 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for PINE64 Ox64 SBC.

Most of the code was derived from NuttX for Star64 JH7110. The UART Driver was derived from BL602 NuttX. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64

`Kconfig`: Added ARCH_CHIP_BL808 for BL808 SoC

`include/bl808/chip.h`: BL808 Definitions

`include/bl808/irq.h`: External Interrupts

`src/bl808/chip.h`: Interrupt Stack Macro

`src/bl808/bl808_allocateheap.c`: Kernel Heap

`src/bl808/bl808_head.S`: Linux Header and Boot Code

`src/bl808/bl808_irq.c`: Configure Interrupts

`src/bl808/bl808_irq_dispatch.c`: Dispatch Interrupts

`src/bl808/bl808_memorymap.h`: Memory Map

`src/bl808/bl808_mm_init.c`, `bl808_mm_init.h`: Memory Mgmt

`src/bl808/bl808_pgalloc.c`: Page Allocator

`src/bl808/bl808_serial.c`, `bl808_serial.h`: UART Driver

`src/bl808/bl808_start.c`: Startup Code

`src/bl808/bl808_timerisr.c`: Timer Interrupt

`src/bl808/hardware/bl808_memorymap.h`: PLIC and UART Base Address

`src/bl808/hardware/bl808_plic.h`: PLIC Register Addresses

`src/bl808/hardware/bl808_uart.h`: UART Register Addresses

`src/bl808/Kconfig`: BL808 Config

`src/bl808/Make.defs`: Makefile
2023-12-12 08:50:03 -08:00
Zhe Weng
22b6076f26 net/udp: Add check when sending too big packet without IP frag
Commit 8a63d29c removed `devif_iob_send` from `udp_sendto_buffered`
workflow, `devif_iob_send` drops too big packet. Now we still need a
place to check the packet length, otherwise a packet larger than MTU
may be sent to the net driver.

In case of similar problem happens somewhere else, this commit also
adds a check in `netdev_upperhalf`, and count these cases into
`NETDEV_TXERRORS`.

Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
2023-12-12 06:42:33 -08:00
Xiang Xiao
ca5a9c711a Remove @ and % tag from all comments
and format the multiple line comments

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-12-11 17:00:10 -03:00
Michal Lenc
02aeb66644 mtd/w25q: add nxsig_usleep to busy waiting in w25qxxxjv_erase_sector()
Busy waiting in w25qxxxjv_erase_sector() was without nxsig_usleep and
was causing the entire system to freeze for significant amount of time
as sector erase takes some time.

This commit adds nxsig_usleep into busy waiting to prevent system lock.
Sleep is set to sector erase time based on W25Q series datasheet.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-12-11 16:00:07 -03:00
anjiahao
8c4e17953e board/stm32: add demo for gdbstub
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 08:43:26 -08:00
anjiahao
bf03bb557f support gdbstub use serial.
we can use uart to debug nuttx,like debugger:

1. read/write memory
2. Use watchpoint,breakpoint,single step.
    use up_debugpoint api

3. Ctrl+c to stop, continue, or single step.
    hold uart send and receive

4. register a panic event, when crash or assert/panic, we use uart to
   debug.

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 08:43:26 -08:00
anjiahao
a423d9b404 gdbstub:convert gdb pid strat to 1
gdb pid strat is 1, nuttx is 0, so convert it

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 08:43:26 -08:00
anjiahao
bb0a706bdc arch/arm:add up_debugpoint api
on armv8-m/armv7-m,implement breakpoint & watchpoint using FBP & DWT

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 08:43:26 -08:00
Lee Lup Yuen
0bac2efd0e Extend MMU Flags to 64-bit for T-Head C906 and Svpbmt
Currently RISC-V NuttX supports 32-bit MMU Flags inside a Page Table Entry. This PR extends the MMU Flags to 64-bit, to support T-Head C906 Core and the new RISC-V Svpbmt Extension.

T-Head C906 uses Bits 59 to 63 in a Leaf Page Table Entry to configure the Memory Type: Cacheable / Bufferable / Strongly-Ordered. For the upcoming port of NuttX to PINE64 Ox64 BL808 SBC, we need to set the Memory Type to Strongly-Ordered for I/O Memory, which requires 64-bit MMU Flags.

Details of C906 MMU: https://lupyuen.github.io/articles/plic3#t-head-errata

Newer RISC-V Cores will use the Svpbmt Extension to configure the Memory Type (Cacheable / Strongly-Ordered). Svpbmt uses Bits 61 to 62 in a Leaf Page Table Entry to define the Memory Type. This also requires 64-bit MMU Flags.

Details of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/main/src/supervisor.adoc#svpbmt
2023-12-11 02:10:14 -08:00
anjiahao
1295ccdd0e Documentation:add Documentation for stack statistics
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 02:06:51 -08:00
anjiahao
25f599fe31 add demo for record stack defconfig
xtensa: esp32s3-devkit:stack
arm: stm32f429i-disco:stack

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 02:06:51 -08:00
anjiahao
94d449e722 arch:Mark key functions to prohibit instrumentation to prevent recursive calls
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 02:06:51 -08:00
anjiahao
d932e0af2a sched/procfs:use instrument to statistics run time max stack
Usage:
1. CONFIG_FS_PROCFS_MAX_STACK_RECORD > 0, such as 32,
2. add '-finstrument-functions' to CFLAGS for What you want to check
   stack.
3. mount porcfs
4. cat /proc/<pid>/stack will print backtace & size

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 02:06:51 -08:00
anjiahao
7dfbd14eba libc: add instrument api support
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.

We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.

Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
   becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.

use instrument_register to register entry function and exit function.
They will be called by the instrumented function

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 02:06:51 -08:00
zhanghongyu
404616d621 linux_Dockerfile: only copy gn binary into docker
Minimize the size of the docker image

Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2023-12-11 10:46:47 +01:00
Mete Balci
2215278a53 stm32u5: fix EXTICR2,3,4 register offsets 2023-12-11 10:42:09 +01:00
Xiang Xiao
19baa56fb5 procfs/cpuinfo: Zero copylen in cpuinfo_read
to avoid return the negative number

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-12-11 10:36:03 +01:00