Commit Graph

309 Commits

Author SHA1 Message Date
zhangyuan21
548424713b arch/arm64: Each core initializes its own idle stack in SMP
When the MMU/MPU of core0 is enabled while those of other cores are not,
it is unsafe to operate the idle stack simultaneously. The idle stack
of other cores will be flushed by the contents in the cache of core0,
therefore it is necessary to initialize the idle stack and let each
core handle it on its own.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-19 17:41:48 +08:00
zhangyuan21
4466c3d6e9 arm64/cache: Support unalign cache clean.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-18 15:45:42 +03:00
Xiang Xiao
7dc0d70092 arch: Save sigdeliver into xcp in the case of signal self delevery
to avoid the infinite recusive dispatch:
*0  myhandler (signo=27, info=0xf3e38b9c, context=0x0) at ltp/testcases/open_posix_testsuite/conformance/interfaces/sigqueue/7-1.c:39
*1  0x58f1c39e in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:167
*2  0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*3  0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:115
*4  0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:435
*5  0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*6  0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*7  0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*8  0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:115
*9  0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:435
*10 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*11 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*12 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*13 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:115
*14 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:435
*15 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*16 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*17 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*18 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:115
*19 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:435
*20 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*21 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*22 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*23 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:115
*24 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:435
*25 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*26 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*27 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*28 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:115
*29 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:435
*30 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*31 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-17 11:53:18 -06:00
Lee Lup Yuen
4ed48c33e9 arm64/a64: Add support for Multiple UART Ports
Currently only Port UART0 is supported for Allwinner A64. This PR adds support for all UART Ports: UART1 to UART4. (Except R-UART, which is a special low-power UART)

This is required for the upcoming LTE Modem Driver (Quectel EG25-G) for PINE64 PinePhone, which uses UART3. [(Details here)](https://lupyuen.github.io/articles/lte2)

The code was adapted from the NuttX UART Driver for Allwinner A1X: [`a1x_serial.c`](https://github.com/apache/nuttx/blob/master/arch/arm/src/a1x/a1x_serial.c)

`arch/arm64/src/a64/a64_serial.c`: Added ports UART1 to UART4, based on [`a1x_serial.c`](https://github.com/apache/nuttx/blob/master/arch/arm/src/a1x/a1x_serial.c)

`arch/arm64/src/a64/a64_serial.h`: Added IRQs for UART1 to UART4. Moved UART Base Addresses to `a64_memorymap.h`

`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added UART Base Addresses for UART0 to UART4

`arch/arm64/src/a64/Kconfig`: Added UART1 to UART4 to Allwinner A64 Peripheral Selection menu

`boards/arm64/a64/pinephone/configs/lcd/defconfig`, `lvgl/defconfig`, `nsh/defconfig`, `sensor/defconfig`: Fixed `UART1_SERIAL_CONSOLE` to `UART0_SERIAL_CONSOLE`
2023-05-11 09:41:18 +02:00
simbit18
2909260f91 arch/arm64/Kconfig: Fix help attribute
Replace help => ---help---
2023-05-10 22:51:11 +08:00
hujun5
6e71527af2 arch/arm64: 64 bit platform compile error reported
compile error log:
common/arm64_arch_timer.c: In function 'arm64_tick_max_delay':
common/arm64_arch_timer.c:178:12: error: conversion from 'long unsigned int' to 'clock_t' {aka 'unsigned int'} changes value from '18446744073709551615' to '4294967295' [-Werror=overflow]
  178 |   *ticks = UINT64_MAX;
      |            ^~~~~~~~~~

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-10 09:06:59 +02:00
hujun5
7f4cb3057a arch/arm64: merge serial_pl011.c and qemu_serial.c
At present, the serial drivers qemu_serial.c and serial_pl011.c on the fvp-v8r and qemu platforms in arm64 are duplicated
and need to be merged. The plan is to place them under the drivers\serial directory to create a common code module,
so that both fvp-v8r and qemu can use the same code.
In the future, if new platforms use pl011 serial ports, they can also be directly reused

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-10 09:06:59 +02:00
qinwei1
2eac660ff6 arm64: Updating ARCH_EARLY_PRINT support
Summary:
  Keeping this option out of depend on any common serial.
Using the option, need to implement xxx_lowputc.S/c.
  You can also logging the booting message through rewriting
fake arm64_lowputc with other debug method (eg semihosting,
ARM debug channel etc).

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-05-09 21:00:48 +08:00
chao an
25bce71b14 arm64/makefile: preprocess link script to make configure more flexibly
1. arm64/makefile: preprocess link script to make configure more flexibly
2. arm64/EXTRA_LIBS: link all staging library

Signed-off-by: chao an <anchao@xiaomi.com>
2023-05-09 20:48:33 +08:00
hujun5
0f243bde33 arch: fix the issue of asynchronous signal processing
in SMP, signal processing cannot be nested, we use xcp.sigdeliver to identify whether there is currently a signal being processed, but this state does not match the actual situation
One possible scenario is that signal processing has already been completed, but an interrupt occurs, resulting in xcp.sigdeliver not being correctly set to NULL,
At this point, a new signal arrives, which can only be placed in the queue and cannot be processed immediately
Our solution is that signal processing and signal complete status are set in the same critical section, which can ensure status synchronization

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-08 09:11:14 +02:00
hujun5
6bf989159e system/signal: in interrupting the context, regs modify logic error
In the interrupt context, we should first save the interrupt context and modify the interrupt register
to execute the signal processing program immediately after exiting the current interrupt

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-07 20:33:46 +08:00
zhangyuan21
841b178782 assert: show stacks with the sp from regs
1. Get the value of sp from dump regs when an exception occurs,
   to avoid getting the value of fp from up_getsp and causing
   incomplete stack printing.
2. Determine which stack the value belongs to based on the value
   of SP to avoid false reports of stack overflow

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-05 13:40:04 +08:00
zhangyuan21
884be2bdb9 assert: Distinguish between assert and exception
CURRENT_REGS may change during assert handling, so pass
in the 'regs' parameter at the entry point of _assert.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-03 14:49:32 +08:00
hujun5
6063c0516e cpu: in SMP pthread_cancel occasionally deadlock
In smp when cpu0 calls up_cpu_resume to release the cpu1 lock, another locked cpu1 did not execute immediately,
and soon cpu0 called up_cpu_resume again, now cpu1 unable to respond to the interrupt at this time, resulting in a deadlock.
Our solution is to restore cpu1 execution from asynchronous to synchronous to ensure that cpu1 is restored.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-04-23 23:33:09 +08:00
qinwei1
c4f3f8801f arm64: Support for FPU profiling with procfs
Summary:

   To reduce the count of FPU context switching will result at a
performance improve with system. it need to balance between
the using of FPU and counts of FPU trap
   the PR submit a base method to see performance counts for
the FPU with NuttX procfs
   Please read README.txt at chapter of FPU Support and Performance
for more information

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-04-22 01:38:21 +08:00
zhangyuan21
dfcba925e7 arch/arm64: add cache enable and disable function
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:22:04 +08:00
zhangyuan21
652fc7648e arch/arm64: Fixed error in getting cache size when there was no mmu
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:22:04 +08:00
zhangyuan21
41f83a0271 arch/arm64: change up_saveusercontext to assembly code
minidump will backtrace failure when use C code to save user context,
because the stack push operation in C code can disrupt the stack information.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:11:00 +08:00
hujun5
ab0b3336c4 arch/arm64:Suppot tickless mode
1 Similar to Linux and zephyr, all implementations are in arm64_arch_timer.c

2 Arm64 tickless is turned off by default. If it needs to be turned on, you need to configure the switch CONFIG_SCHED_TICKLESS ON

3 The implementation strategy for tick/tickless is to use the timer inside the CPU and implement the timer driver based on the ARCH_TIMER framework.

4 We implemented tick_* Callback functions to adapt to the driven interface to avoid time format conversion overhead

5 In arm64_tick_cancel func,The remaining time that is not used, so this value can be ignored without reading the corresponding register to obtain the remaining cycles

6 Currently, tick/tickless can takes effect in SMP and non SMP mode, ostest can pass.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-04-22 01:08:04 +08:00
zhangyuan21
c00498c164 arch/arm: update running task when context switch occurred
The text describes an issue related to the running task in code.
The running task is only used when calling the _assert function
to indicate the task that was running before an exception occurred.
However, the current code only updates the running task during
irq_dispatch, which is suitable for ARM-M architecture but not
for ARM-A or ARM-R architecture, because their context switches
are not done through irq handler. Therefore, if the following
process is followed, the value of the running task will be incorrect:

1. task1 is running, this_task()=task1
2. do_irq is executed, setting running task()=task1
3. task1 switches to task2
4. task2 is running and generates a data abort
5. In the data abort, the _assert function is called,
   and the running task obtained is still task1, but
   the actual task that generated the exception is task2.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 10:14:05 +09:00
zhangyuan21
f5f0af4f9c arch/arm64: fixed backtrace skip calc error
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
zhangyuan21
2c599bb9e6 arch/arm64: call PANIC in arm64_fatal_error
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
zhangyuan21
e4ae2b48b8 arch/arm64: Obtaining the correct fp pointer
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
zhangyuan21
024b13f3ed arch/arm: enable eoimode only select CONFIG_XXX_GIC_EOIMODE
On a GICv2 implementation, setting GICC_CTLR.EOImode to 1 separates
the priority drop and interrupt deactivation operations.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-11 08:54:45 +02:00
zhangyuan21
c239d19df0 nuttx: add more dependent header file
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-11 09:13:32 +03:00
wangming9
a7fc26124d arch/arm64: the arm64 perf interface supports pmu
Summary:
- Support arm64 pmu api, Currently only the cycle counter function is supported.
- Using ARM64 PMU hardware capability to implement perf interface, modify all
  perf interface related code.
- Support for pmu init under smp.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-04-10 16:23:49 -03:00
wangming9
75760a9fdb arch/arm64: Adds custom chip option
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-04-10 16:23:49 -03:00
Xiang Xiao
bc3e6c84e1 arch: Rename up_[early]serialinit to [arm64|riscv|x86_64][early]serialinit
The naming standard at:
https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+Architecture%2C+MCU%2C+and+Board+Interfaces
requires that all MCU-private function begin with the name of the architecture, not up_.

follow the change from: https://github.com/apache/nuttx/pull/930

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-27 12:35:04 +03:00
ligd
bb281eedfa cache: add up_get_xcache_linesize() support
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-03-20 17:17:22 +08:00
qinwei1
e3f0f86514 arm64: add arm64_serialinit/arm64_earlyserialinit
Summary:

   add arm64_serialinit/arm64_earlyserialinit function prototype
to arm64_internal.h as common function for arm64 based chip.
   Testing with ostest in SP and SMP

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-05 09:44:51 +08:00
Xiang Xiao
454921eac7 arch/boards: Rename up_lowputc to [arm64|renesas]_lowputc
follow other arch coding style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-04 11:08:00 +02:00
qinwei1
d2d954f691 arm64: ARMv8-r(Cortex-R82) support( add FVP platform )
Summary:
   Adding virtual evaluate platform FVP. This FVP board configuration
will be used to emulate generic ARM64v8-R (Cotex-R82)series hardware
platform and provide support for these devices:

 - GICv3 interrupt controllers for ARMv8-r
 - PL011 UART controller(FVP)

Note:
1. ostest is PASSED at fvp ( single core and SMP)
2. the FVP tools can be download from ARM site, please check FVP
  board readme.txt

TODO: merge PL011 UART driver to common place

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-02 13:33:15 +08:00
qinwei2004
fa359e355c Update arm64_head.S 2023-03-01 13:23:48 +08:00
qinwei1
518eb4076e arm64: ARMv8-r(Cortex-R82) support(mpid fix)
Summary
  Different ARM64 Core will use different Affn define, the mpidr_el1
value is not CPU number, So we need to change CPU number to mpid
and vice versa, the patch change the mpid define into platform

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
d5c6b8a94b arm64: add 64-bit time for all arm64 platform
Summary
  For ARM64 architecture, the arch timer is 64-bit,
the CONFIG_SYSTEM_TIME64 need to be enabled just like
x86_64 and risc-v 64

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
4cb5ff3353 arm64: ARMv8-r(Cortex-R82) support(add ARCH_SET_VMPIDR_EL2 option)
Summary

   VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID.
From architecture manual of AArch64, the behave is:
  -reading register MPIDR_EL1 in EL2, it's return real MPIDR_EL1
  -reading register MPIDR_EL1 in EL1, it's return VMPIDR_EL2
  So since NuttX for SMP is running at EL1 to read MPIDR_EL1 for
  identify CPU id, it's need to set VMPIDR_EL2 to MPIDR_EL1 for
  every CPU at boot EL2 stage.
  For some platform, the bootloader or hypervisor will do that at
  the EL2 stage, but not all.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
0841f4dbaa arm64: ARMv8-r(Cortex-R82) support
Summary:

  Adding armv8-r(Cortex-R82) support and modify some common code to
fit the change, the change including:

1. ARM Single Security State Support, ARMv8-R support only single
   security state, and some GIC configure need to change and fit
2. For ARMv8-R, only have EL0 ~ EL2, the code at EL3 is not necessary
   and system register for EL3 is not accessible(gcc will failed when
   access these registers)
3. add base MPU configure for the platform.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
4240723b78 arm64: add ARCH_EARLY_PRINT support
Summary:
  The aarch64 have EL0~El3 execute level and NS/S (security state),
the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R)
state. but booting NuttX have different ELs and state while with
different platform, if NuttX runing at wrong ELs or state it will
be not normal anymore. So we need to print something in arm64_head.S
to debug this situation.
Enabling this option will need to implement up_earlyserialinit and
up_lowputc functions just you see in qemu, if you not sure,
keeping the option disable.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
e5564a9872 arm64: PSCI config support
Summory
   This Power State Coordination Interface (PSCI) defines a standard
interface for power management. the PCSI need to implement handling
firmware at EL2 or EL3 for ARM64. the PSCI maybe not applicable
for arm core without PCSI firmware interface implement.
  Add configure option for it.

Note:
1. ostest is PASSED at qemu and fvp ( single core and SMP)

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
Xiang Xiao
2c5f653bfd Remove the tail spaces from all files except Documentation
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-26 13:24:24 -08:00
Xiang Xiao
8b4ecac6c2 libc: Move math library from libs/libc/math to libs/libm/libm
to prepare the support of other implementation e.g.:
https://github.com/JuliaMath/openlibm
https://gitlab.com/gtd-gmbh/libmcs

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-23 10:40:07 +02:00
Fotis Panagiotopoulos
85ceb7920e Typo fixes. 2023-02-17 11:17:11 -03:00
chao an
3a0fdb019d nuttx: replace all ARRAY_SIZE()/ARRAYSIZE() to nitems()
Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-09 20:05:44 +08:00
Ville Juven
9ac3e841da group_addrenv: Fix call to group_addrenv for targets that don't need it 2023-02-09 00:14:52 +08:00
Ville Juven
f4b82b6405 sched/addrenv: Remove up_addrenv_restore
The function is not relevant any longer, remove it. Also remove
save_addrenv_t, the parameter taken by up_addrenv_restore.

Implement addrenv_select() / addrenv_restore() to handle the temporary
instantiation of address environments, e.g. when a process is being
created.
2023-02-08 02:51:23 +08:00
Nathan Hartman
5f9cb6faf4 drivers/serial: Fix docstrings on UART interrupt handlers 2023-02-07 04:41:36 +08:00
Gustavo Henrique Nihei
e6b204f438 nuttx: Use MIN/MAX definitions from "sys/param.h"
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-02-01 23:47:44 +08:00
yinshengkai
3f97a87162 tools: add separate flags parameter for COMPILE/COMPILEXX
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2023-01-31 13:42:33 +08:00
qinwei1
b989e4f3a6 arch:arm64: add support for nuttx arm64 Toolchain Selection
Summary:
1. to enable Toolchain select Kconfig option, making something depend on
   the opton to be configured with menuconfig

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-01-29 14:37:16 +08:00
Ville Juven
42d0e356c2 arch/addrenv: Change group_addrenv_t to arch_addrenv_t
This is preparation for moving address environments out of the group
structure into the tcb.

Why move ? Because the group is destroyed very early in the exit phase,
but the MMU mappings are needed until the context switch to the next
process is complete. Otherwise the MMU will lose its mappings and the
system will crash.
2023-01-27 23:17:01 +08:00
Ville Juven
686b990a85 arch/ARCH_KERNEL_STACK: Fix signal handling with kernel stack
There were two issues with signal handling:
- With a kernel stack the "info" parameter was passed from kernel memory.
  This is fixed by making a stack frame to the user stack and copying it
  there.
- If the signal handler uses a system call, the kernel stack was completely
  and unconditionally destroyed, resulting in a crash in the user application

There is also no need to check ustkptr, it is always NULL. Why ? Because
signal delivery is deferred when a system call is being executed.
2023-01-26 20:41:42 +08:00
Xiang Xiao
d7ee492fc4 board/arch: Remove FAR decorator
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-25 13:05:07 +02:00
Xiang Xiao
f64da13e9b libxx: Add CXX_STANDARD to select -std=c++??
and default to "c++17"

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-16 15:41:57 +02:00
Jukka Laitinen
70de321de3 arch/Kconfig: remove virtual memory allocator dependency from MM_SHM
The dependency should be vice versa; the MM_SHM should depend on the
existence of the virtual memory range allocator.

Create a new CONFIG flag CONFIG_ARCH_VMA_MAPPING, which will define that
there is a virtual memory range allocator. Make MM_SHM select that flag

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-01-13 02:20:13 +08:00
Lee Lup Yuen
6d70b91a55 arm64/a64: Fix PIO Interrupt
The current implementation of PIO Interrupt for Allwinner A64 is incomplete. This PR fixes the implementation of PIO Interrupt for all supported PIO Ports (PB, PG and PH).

### Modified Files

`arch/arm64/src/a64/a64_pio.c`, `a64_pio.h`: Add implementation of PIO Interrupt

`arch/arm64/include/a64/irq.h`: Add IRQ for PIO Port PH

`arch/arm64/src/a64/hardware/a64_pio.h`: Fix addresses of PIO Interrupt Registers
2023-01-06 13:43:44 +08:00
zouboan
7e81dce71c arm64/a64: add driver for Allwinner A64 I2C bus
arm64/a64: add driver for Allwinner A64 I2C bus

arm64/a64: add driver for Allwinner A64 I2C bus

arm64/a64: add driver for Allwinner A64 I2C bus
2023-01-03 01:45:56 +08:00
Lee Lup Yuen
17639af0a8 arm64/pinephone: Add driver for LCD Panel (Xingbangda XBD599)
This PR adds the driver for Xingbangda XBD599 LCD Panel (based on Sitronix ST7703 LCD Controller) on PINE64 PinePhone. This PR also includes:

- The driver for X-Powers AXP803 Power Mgmt IC, which calls our driver for Allwinner A64's Reduced Serial Bus. The PMIC Driver is needed to power on the MIPI DSI Interface for the LCD Panel.

- A simple Display Driver that renders a Test Pattern on the LCD Display at startup. It calls our Allwinner A64 drivers for Display Engine, Timing Controller TCON0 and MIPI Display Serial Interface.

The NuttX Frame Buffer Driver will be implemented in the next PR.

`arch/arm64/src/a64/a64_de.c`, `a64_de.h`: Changed the Frame Buffer pointer to `const` for Allwinner A64 Display Engine

`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for PWM, for controlling the PWM Backlight

`boards/arm64/a64/pinephone/src/pinephone_bringup.c`: Call `fb_register()` to start the Display Driver at startup

`boards/arm64/a64/pinephone/src/Makefile`: Added LCD Driver, PMIC Driver and Display Driver to Makefile

`boards/arm64/a64/pinephone/Kconfig`: Added the Kconfig option for "PINE64 PinePhone > LCD Display" (`CONFIG_PINEPHONE_LCD`) which enables the LCD Driver, PMIC Driver and Display Driver

`boards/arm64/a64/pinephone/src/pinephone_lcd.c`, `pinephone_lcd.h`: Driver for Xingbangda XBD599 LCD Panel

`boards/arm64/a64/pinephone/src/pinephone_pmic.c`, `pinephone_pmic.h`: Driver for X-Powers AXP803 Power Mgmt IC

`boards/arm64/a64/pinephone/src/pinephone_display.c`: Simple Display Driver that renders a Test Pattern in `up_fbinitialize()`

`boards/arm64/a64/pinephone/configs/lcd/defconfig`: New PinePhone Board Configuration `pinephone:lcd` that enables the LCD Driver (`CONFIG_PINEPHONE_LCD`)

`platforms/arm/a64/boards/pinephone/index.rst`: Added PinePhone Board Configuration `pinephone:lcd` that enables the LCD Driver
2022-12-27 11:44:17 +08:00
Xiang Xiao
b9d7d00943 arch: Remove the unused arch color function variant
up_check_tcbstack_remain, up_check_stack, up_check_stack_remain and up_check_intstack_remain

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-12-24 22:40:52 +02:00
zhangyuan21
45394eb6dc arch: save user context in assert common code
This is the work continue with #7875

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2022-12-24 13:02:56 +08:00
Lee Lup Yuen
c8cf27e848 arm64/a64: Add driver for Reduced Serial Bus
This PR adds the driver for Reduced Serial Bus (RSB) on Allwinner A64 SoC. The RSB Driver will be called by the upcoming Power Mgmt IC Driver for PINE64 PinePhone, to power on the LCD Display.

`arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > RSB" (`CONFIG_A64_RSB`), which enables the RSB Driver

`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for RSB

`arch/arm64/src/a64/Make.defs`: Added the RSB Driver to the Makefile

`arch/arm64/src/a64/a64_de.c`: Increase PLL Timeout for Allwinner A64 Display Engine

`boards/arm64/a64/pinephone/configs/nsh/defconfig`: Set PinePhone Board Config `CONFIG_BOARD_LOOPSPERMSEC` to the value computed by `calib_udelay`

`arch/arm64/src/a64/a64_rsb.c`, `a64_rsb.h`: RSB Driver for Allwinner A64

`platforms/arm/a64/boards/pinephone/index.rst`: Added RSB as supported peripheral for PinePhone
2022-12-24 12:01:46 +08:00
Lee Lup Yuen
64a54d2dfd arm64/a64: Add driver for Display Engine
This PR adds the driver for Display Engine 2.0 on Allwinner A64 SoC. The Display Engine Driver will be called by the upcoming LCD Driver for PINE64 PinePhone.

`arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > DE" (`CONFIG_A64_DE`), which enables the Display Engine Driver

`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for Display Engine

`arch/arm64/src/a64/Make.defs`: Added the Display Engine Driver to the Makefile

`boards/arm64/a64/pinephone/configs/nsh/defconfig`: Removed Scheduler Debug Info (`CONFIG_DEBUG_SCHED_INFO`) from the PinePhone Board Config, because it garbles the Console Output.

`arch/arm64/src/a64/a64_de.c`, `a64_de.h`: Display Engine Driver for Allwinner A64

`platforms/arm/a64/boards/pinephone/index.rst`: Added Display Engine as supported peripheral for PinePhone
2022-12-21 13:17:34 +08:00
zouboan
60c0184b76 A64/irq.h: Add irq definition of Allwinner A64 interrupts 2022-12-20 23:34:23 +08:00
Lee Lup Yuen
377477a948 arm64/a64: Add driver for TCON0
This PR adds the driver for TCON0 (Timing Controller) on Allwinner A64 SoC. The TCON0 Driver will be used by the upcoming Display Driver for PINE64 PinePhone.

`arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > TCON0" (`CONFIG_A64_TCON0`), which enables the TCON0 Driver

`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for TCON0

`arch/arm64/src/a64/Make.defs`: Added the TCON0 Driver to the Makefile

`arch/arm64/src/a64/a64_tcon0.c`, `a64_tcon0.h`: TCON0 Driver for Allwinner A64

`platforms/arm/a64/boards/pinephone/index.rst`: Added TCON0 as supported peripheral for PinePhone
2022-12-19 20:10:54 +08:00
zhangyuan21
453a1a7332 arch: move stack and task dump to common code
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2022-12-17 01:59:35 +08:00
zhangyuan21
632d87ee71 arch: remove up_release_pending function
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2022-12-16 21:29:57 +08:00
Lee Lup Yuen
b895207489 arm64/a64: Add driver for MIPI DSI
This PR adds the driver for Allwinner A64's MIPI Display Serial Interface (DSI) and MIPI Display Physical Layer (D-PHY).

This driver will be used by the upcoming Display Driver for PINE64 PinePhone.

- `include/nuttx/crc16.h`: Added 16-bit CRC-CCITT

- `libs/libc/misc/Make.defs`: Added 16-bit CRC-CCITT to Makefile

- `arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > MIPI DSI" (`CONFIG_A64_MIPI_DSI`), which enables the MIPI DSI Driver

- `arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for MIPI DSI

- `arch/arm64/src/a64/Make.defs`: Added the MIPI DSI Driver to the Makefile

- `libs/libc/misc/lib_crc16ccitt.c`: Compute 16-bit CRC-CCITT

- `arch/arm64/src/a64/mipi_dsi.c`, `mipi_dsi.h`: Compose MIPI DSI Packets (Long, Short, Short with Parameter)

- `arch/arm64/src/a64/a64_mipi_dsi.c`, `a64_mipi_dsi.h`: MIPI DSI Driver for Allwinner A64

- `arch/arm64/src/a64/a64_mipi_dphy.c`, `a64_mipi_dphy.h`: MIPI D-PHY Driver for Allwinner A64

- `platforms/arm/a64/boards/pinephone/index.rst`: Added MIPI DSI as supported peripheral for PinePhone

Co-Authored-By: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-12-14 22:37:32 +08:00
田昕
0382b63f5d move common assert logic together.
Signed-off-by: 田昕 <tianxin7@xiaomi.com>
2022-12-12 17:05:02 +08:00
zhangyuan21
ffd2eb5b14 arch/arm: only compare callee-saved registers for fpu
Registers S0-S15 (D0-D7, Q0-Q3) do not need to be preserved. They can be used for passing
arguments or returning results in standard procedure-call variants.
Registers D16-D31 (Q8-Q15), do not need to be preserved.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2022-12-09 11:00:38 +08:00
zouboan
753f46dffe arch/arm64: add support of systemreset 2022-12-07 21:17:39 +08:00
Lee Lup Yuen
c2d75c930b arm64/a64: Add drivers for PIO and LEDs
This PR adds the drivers for Allwinner A64 PIO (Programmable I/O) and PinePhone LEDs (Red / Green / Blue).

The PIO Driver is based on the NuttX PIO Driver for Allwinner A10: [`arch/arm/src/a1x/a1x_pio.c`](https://github.com/apache/nuttx/blob/master/arch/arm/src/a1x/a1x_pio.c)

-   `arch/arm64/src/a64/Make.defs`: Add PIO Driver to Makefile

-   `boards/Kconfig`: Add `ARCH_HAVE_LEDS` to PinePhone

-   `boards/arm64/a64/pinephone/src/pinephone.h`: Define PinePhone LEDs

-   `boards/arm64/a64/pinephone/src/pinephone_boardinit.c`: Start Auto LEDs

-   `boards/arm64/a64/pinephone/src/pinephone_bringup.c`: Start User LEDs

-   `boards/arm64/a64/pinephone/src/Makefile`: Add LED Driver to Makefile

-   `boards/arm64/a64/pinephone/configs/nsh/defconfig`: Add `CONFIG_USERLED` to `nsh` config

-   `arch/arm64/src/a64/a64_pio.c`, `a64_pio.h`: Allwinner A64 PIO Driver

-   `arch/arm64/src/a64/hardware/a64_memorymap.h`: PIO Memory Map

-   `arch/arm64/src/a64/hardware/a64_pio.h`: PIO Definitions

-   `boards/arm64/a64/pinephone/include/board.h`: Define PinePhone LEDs

-   `boards/arm64/a64/pinephone/src/pinephone_autoleds.c`: Driver for Auto LEDs

-   `boards/arm64/a64/pinephone/src/pinephone_userleds.c`: Driver for User LEDs

-   `introduction/supported_platforms.rst`: Add Allwinner A64 as Supported Platform

-   `platforms/arm/a64/boards/pinephone/index.rst`: Add PIO and LEDs to PinePhone
2022-12-06 18:14:39 +08:00
Masayuki Ishikawa
f7937d11a2 arch: arm64: Fix qemu_pl011_txint() in qemu_serial.c
Summary:
- I noticed that the nsh prompt can not be shown when disabling
  debug features. Actually, the prompt will be shown when a user
  input happens.
- This commit fixes this issue by adding uart_xmitchars() as
  other serial drivers do.

Impact:
- None

Testing:
- Tested with qemu-armv8a:netnsh on QEMU-7.1

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-12-01 19:38:03 +08:00
Masayuki Ishikawa
1eb3d01956 arch: arm64: Add qemu_virtio.c
Summary:
- This commit adds qemu_virtio.c

Impact:
- None

Testing:
- Tested with qemu-armv8a:netnsh (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-11-29 13:16:44 +08:00
Masayuki Ishikawa
b1ebca68f1 arch: arm64: Remove arm64_netinitialize() from qemu_boot.c
Summary:
- This commit removes arm64_netinitialize() from qemu_boot.c

Impact:
- None

Testing:
- Tested with QEMU-7.1

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-11-29 13:16:44 +08:00
Lee Lup Yuen
b31054b1e3 arch/arm64: Add support for PINE64 PinePhone
This PR adds support for PINE64 PinePhone and the Allwinner A64 SoC (based on Arm Cortex-A53).

With this PR, PinePhone boots successfully to nsh (via microSD Card) and runs console apps.

-   `arch/arm64/Kconfig`: Added Allwinner A64 SoC

-   `boards/Kconfig`: Added PINE64 PinePhone

-   `arch/arm64/src/a64/Kconfig`: New Kconfig for Allwinner A64 SoC

-   `boards/arm64/a64/pinephone/Kconfig`: New Kconfig for PINE64 PinePhone

-   `src/a64/a64_boot.c`, `a64_boot.h`: Boot functions for Allwinner A64

-   `src/a64/a64_lowputc.S`: Low-level console output

-   `src/a64/a64_serial.c`, `a64_serial.h`: A64 Serial Driver

-   `src/a64/chip.h`: A64 SoC Definitions

-   `include/a64/chip.h`: A64 Memory Map, Generic Interrupt Controller

-   `include/a64/irq.h`: A64 Interrupts

-   `src/a64/Make.defs`: Source files for A64

-   `configs/nsh/defconfig`: Board Configuration for `pinephone:nsh`

-   `src/pinephone_appinit.c`: Init PinePhone

-   `src/pinephone_boardinit.c`: Init PinePhone

-   `src/pinephone_bringup.c`: Start PinePhone Drivers

-   `src/pinephone.h`: PinePhone Declarations

-   `include/board_memorymap.h`: PinePhone Memory Map

-   `scripts/dramboot.ld`: PinePhone Linker Script

-   `scripts/Make.defs`: Source files for PinePhone

-   `src/Makefile`: PinePhone Makefile

-   `platforms/arm/a64/boards/pinephone/index.rst`: Building and booting NuttX on PinePhone

-   `platforms/arm/a64/index.rst`: Overview of Allwinner A64

-   `introduction/supported_platforms.rst`: Added Allwinner A64

-   `introduction/detailed_support.rst`: Added Allwinner A64
2022-11-25 17:19:48 +08:00
zhangyuan21
d8051ba979 nuttx/sched: merge up_block_task and up_unblock_task 2022-11-22 22:59:08 +08:00
zhangyuan21
a8fa51e6bf arch: rename arch special function name 2022-11-22 16:27:56 +08:00
zhangyuan21
5c1b518314 nuttx/sched: move reprioritize process to public function 2022-11-22 15:29:00 +09:00
zhangyuan21
08f7152d9f nuttx/sched: remove nxsched_remove_readytorun from up_block_task
It takes about 10 cycles to obtain the task list according to the task
status. In most cases, we know the task status, so we can directly
add the task from the specified task list to reduce time consuming.
2022-11-22 15:29:00 +09:00
zhangyuan21
e54b602208 nuttx/sched: remove nxsched_remove_blocked from up_unblock_task
It takes about 10 cycles to obtain the task list according to the task
status. In most cases, we know the task status, so we can directly
delete the task from the specified task list to reduce time consuming.
2022-11-22 15:29:00 +09:00
Lee Lup Yuen
6aba739f05 arch/arm64: Add support for Generic Interrupt Controller Version 2
Currently NuttX on Arm64 supports Generic Interrupt Controller (GIC) Versions 3 and 4: [`arm64_gicv3.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm64/src/common/arm64_gicv3.c), [`arm64_gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm64/src/common/arm64_gic.h). This PR adds support for GIC Version 2, which is needed by [Pine64 PinePhone](https://lupyuen.github.io/articles/interrupt) based on Allwinner A64 SoC.

This 64-bit implementation of GIC v2 is mostly identical to the existing GIC v2 for 32-bit Armv7-A ([`armv7-a/arm_gicv2.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/arm_gicv2.c), [`armv7-a/gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/gic.h)), with minor modifications to support 64-bit Registers (Interrupt Context).

-   `arch/arm64/Kconfig`: Under "ARM64 Options", we added an integer option `ARM_GIC_VERSION` ("GIC version") that selects the GIC Version. Valid values are 2, 3 and 4, default is 3.

-   `arch/arm64/src/common/arm64_gicv2.c`: Implements 64-bit GIC v2 based on 32-bit [`armv7-a/arm_gicv2.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/arm_gicv2.c) and [`armv7-a/gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/gic.h), modified to support 64-bit Registers (Interrupt Context).

    Function and Macro Names have not been changed, for easier cross-referencing between the 32-bit and 64-bit implementations of GIC v2.

-   `arch/arm64/src/common/arm64_gicv3.c`: Added Conditional Compilation for GIC v3. This file will not be compiled if `ARM_GIC_VERSION` is 2.

-   `arch/arm64/src/common/arm64_gic.h`: Added the Version Identifier for GIC v2. At startup we read the GIC Version from hardware and verify that it matches `ARM_GIC_VERSION`.

-   `arch/arm64/include/qemu/chip.h`: Added the QEMU Base Addresses for GIC v2.

-   `arch/arm64/src/common/Make.defs`: Added the source file that implements GIC v2.

-   `boards/arm64/qemu/qemu-armv8a/README.txt`: Added the documentation for testing GIC v2 with QEMU.

-   `boards/arm64/qemu/qemu-armv8a/configs/nsh_gicv2/defconfig`: Added the Board Configuration `qemu-armv8a:nsh_gicv2` for testing GIC v2 with QEMU. Identical to `qemu-armv8a:nsh`, except that `ARM_GIC_VERSION` is 2.
2022-11-20 21:44:12 -08:00
Xiang Xiao
f9479885ba arch/arm64: Move group_addrenv to arm64_syscall_switch
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-11-20 08:17:03 -03:00
yinshengkai
85f727f232 tools: replace INCDIR to Makefile variable
In the past, header file paths were generated by the incdir command
Now they are generated by concatenating environment variables

In this way, when executing makefile, no shell command will be executed,
it will improve the speed of executing makfile
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2022-11-03 19:59:55 +08:00
Xiang Xiao
b607f80cf3 arch: Remove the unnecessary nosanitize_address from backtrace source code
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-29 08:26:04 +02:00
Hidenori Matsubayashi
544552c305 arch/arm64/arm64_arch_timer: delete unused includes
Delete unnecessary includes.

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-19 23:15:00 +02:00
anjiahao
d1d46335df Replace nxsem API when used as a lock with nxmutex API
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-17 15:59:46 +09:00
Hidenori Matsubayashi
ffe8dd39c6 arch/arm64: update for coding style
Replace "unsigned char" with "bool".

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-16 17:20:14 +08:00
Hidenori Matsubayashi
28180b49d1 arm64: add Cortex-A57 and Cortex-A72 configurations
This change adds the following:
- Rename the board configuration name from qemu-a53 to qemu-v8a.
- Add the configurations for Cortex-A57 and Cortex-A72.

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-14 09:27:35 +08:00
Hidenori Matsubayashi
06cf41901f arch/arm64: cleanup defconfigs
Use CONFIG_ARCH_CHIP_QEMU instead of CONFIG_ARCH_CHIP_QEMU_A53. This is because these configurations depend on the hardware configuration of qemu (memory map, irq numbers, etc.).

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-13 19:26:26 +08:00
Hidenori Matsubayashi
b0f9241ec1 arch/arm64: update to follow NuttX C Coding Standard
This change moves the static vars to the appropriate place to follow the coding standard. It also adds comments as sections and `static` where necessary.

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-09 17:38:31 +08:00
Hidenori Matsubayashi
0b03a2316f arch/arm64/qemu/qemu_boot: fix wrong memory size
The default size in QEMU system is 128MB, and the size specified in chip.h is also 128MB. However, the region size for MMU was 512MB, so fixed it.

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-09 17:18:26 +08:00
Hidenori Matsubayashi
1297c23e7d arch/arm64/arm64_mmu: add mmu_nxrt_config
This change is a refactoring to match the userspace mmu_regions implementation.

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-09 12:52:40 +09:00
Xiang Xiao
70290b6e38 arch: Change the linker generated symbols from uint32_t to uint8_t *
and remove the duplicated declaration

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-24 21:26:56 +02:00
Xiang Xiao
3c1c29f2c4 arch: move non arm g_current_regs defintion to common place
to avoid the code duplicaiton

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-21 22:23:11 +02:00
ligd
e2df52390a SMP: fix crash when switch to new task which is still running
Situation:

Assume we have 2 cpus, and busy run task0.

CPU0                                CPU1
task0 -> task1                      task2 -> task0
1. remove task0 form runninglist
2. take task1 as new tcb
3. add task0 to blocklist
4. clear spinlock
                                    4.1 remove task2 form runninglist
                                    4.2 take task0 as new tcb
                                    4.3 add task2 to blocklist
                                    4.4 use svc ISR swith to task0
                                    4.5 crash
5. use svc ISR swith to task1

Fix:
Move clear spinlock to the end of svc ISR

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-09-17 17:37:47 +09:00
chao an
0f0a94186f arch/arm/toolchain: migrate the toolchain define to arch/arm/Kconfig
migrate the toolchain define to arch/arm/Kconfig to simplify new toolchain registration

Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-16 14:47:27 +08:00
Huang Qi
32a21a1b67 UBSan: Allow custom the sanitizer in Kconfig
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-09-02 19:07:09 +08:00
wangbowen6
b15d38246c up_nputs: fix AddressSanitizer: global-buffer-overflow problem
==2117790==ERROR: AddressSanitizer: global-buffer-overflow on address 0x64d9e3c0 at pc 0x59ac4e16 bp 0xcefe8058 sp 0xcefe8048
READ of size 1 at 0x64d9e3c0 thread T0
    #0 0x59ac4e15 in up_nputs sim/up_nputs.c:54
    #1 0x59a67e4c in syslog_default_write syslog/syslog_channel.c:220
    #2 0x59a67823 in syslog_default_write syslog/syslog_write.c:101
    #3 0x59a67f10 in syslog_write syslog/syslog_write.c:153
    #4 0x59a651c3 in syslogstream_flush syslog/syslog_stream.c:60
    #5 0x59a6564e in syslogstream_addchar syslog/syslog_stream.c:104
    #6 0x59a6576f in syslogstream_putc syslog/syslog_stream.c:140
    #7 0x5989fc4d in vsprintf_internal stdio/lib_libvsprintf.c:952
    #8 0x598a1298 in lib_vsprintf stdio/lib_libvsprintf.c:1379
    #9 0x59a64ea4 in nx_vsyslog syslog/vsyslog.c:223
    #10 0x598a601a in vsyslog syslog/lib_syslog.c:68
    #11 0x59b0e3dc in AIOTJS::logPrintf(int, char const*, ...) src/ajs_log.cpp:45
    #12 0x59b03d56 in jse_dump_obj src/jse/quickjs/jse_quickjs.cpp:569
    #13 0x59b03ea1 in jse_dump_error1(JSContext*, unsigned long long) src/jse/quickjs/jse_quickjs.cpp:602
    #14 0x59b03dd9 in jse_dump_error(JSContext*) src/jse/quickjs/jse_quickjs.cpp:591
    #15 0x59bed615 in ferry::DomComponent::callHook(char const*) src/framework/dom/component.cpp:65
    #16 0x59bfe0ff in ferry::DomComponent::initialize() src/framework/dom/component.cpp:645
    #17 0x59bb141d in dom_create_component(JSContext*, unsigned long long, unsigned long long, unsigned long long) (/home/wangbowen/project/central/vela_miot_bes_m0/bin/audio+0x365c41d)
    #18 0x59b4c0d3 in AIOTJS::__createComponent(JSContext*, unsigned long long, int, unsigned long long*) (/home/wangbowen/project/central/vela_miot_bes_m0/bin/audio+0x35f70d3)
    #19 0x5a56ec17 in js_call_c_function quickjs/quickjs.c:16108

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-09-01 11:51:48 +08:00
Gustavo Henrique Nihei
5ed2ee85c9 arch: Improve documentation for up_fpucmp function
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-08-26 11:57:06 +08:00
Xiang Xiao
d22e1e1998 compiler.h: Add nosanitize_address macro
and replace all __attribute__((no_sanitize_address)) with it

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-08-23 17:50:52 +02:00
Xiang Xiao
c44a7cbf88 arch: Add ARCH_COVERAGE_ALL option
so the user could disable the full image instrumentation,
but enable the instrumentation by files or directories.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-08-23 17:50:52 +02:00
Huang Qi
a06ec54cd0 debug: Introduce portion of UBSan
without UBSan
```
 text    data     bss     dec     hex filename
  85612     208  142258  228078   37aee nuttx
```

with UBSan:
```
   text    data     bss     dec     hex filename
 194290   98164  208634  501088   7a560 nuttx
```

```c
int main(int argc, FAR char *argv[])
{
  uint32_t ptr[32];
  printf("Hello, World!! %lu\n", ptr[64]);
  return 0;
}
```
Try to run this sample:
```
nsh> hello
ubsan_prologue: ================================================================================
ubsan_prologue: UBSAN: array-index-out-of-bounds in hello_main.c:39:37
__ubsan_handle_out_of_bounds: index 64 is out of range for type 'uint32_t [32]'
ubsan_epilogue: ================================================================================
Hello, World!! 1070182368
nsh>
```

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-08-22 13:57:29 +08:00
Xiang Xiao
13a7ae3d06 arch: Call board_reset before up_irq_save and spin_trylock
since board_reset may call some kernel functions which try
to acquire the lock again

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-28 08:18:24 -04:00
Jiuzhu Dong
5c8fd46126 arch/stack: rename do_stack_check with arch prefix
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-07-27 20:48:33 +08:00
Jiuzhu Dong
79597d0caf arch/up_stack_check: using running_task to get correct task context
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-07-27 20:48:33 +08:00
Masayuki Ishikawa
06b158a490 arch: arm64: Fix warnings in arm64_cpstart.c
Summary:
- Fix warnings in arm64_cpstart.c if CONFIG_DEBUG_INFO=n

Impact:
- None

Testing:
- Tested with qemu-a53:nsh_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-07-19 10:49:32 +08:00
Xiang Xiao
61dff1c125 arch/arm64: Implement up_nputs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-17 17:31:19 +03:00
Masayuki Ishikawa
82cd9b0a4a arch: arm64: Add stack coloration for SMP
Summary:
- This commit adds stack coloration for SMP

Impact:
- None

Testing:
- Tested with qemu-a53:nsh_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-07-15 16:16:02 +08:00
Masayuki Ishikawa
3682bcd4b3 arch: arm64: Fix do_stackcheck()
Summary:
- Since the stack coloration is done for every 32bits
  this function should be done in the same way.

Impact:
- None

Testing:
- Tested with qemu-a53:nsh

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-07-15 16:16:02 +08:00
qinwei1
e77b06721b arch: arm64: ARMv8-A support for NuttX
N/A

Summary:

Arm64 support for NuttX, Features supported:

1. Cortex-a53 single core and SMP support: it's can run into nsh shell at
   qemu virt machine.

2. qemu-a53 board configuration support: it's only for evaluate propose

3. FPU support for armv8-a: FPU context switching at NEON/floating-point
  TRAP is supported.

4. psci interface, armv8 cache operation(data cache) and smccc support.

5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko

Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail

Note:
1. GCC MACOS issue
The GCC 11.2 toolchain for MACOS may get crash while compiling
float operation function, the following link describe the issue
and give analyse at the issue:

https://bugs.linaro.org/show_bug.cgi?id=5825

it's seem GCC give a wrong instruction at certain machine which
without architecture features

the new toolchain is not available still, so just disable the MACOS
cibuild check at present

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-07-14 09:35:49 -04:00