sergiotarxz/nuttx
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652 Commits

Author SHA1 Message Date
Gregory Nutt
5f67fc8f1b RTC alarms: getalarmdatetime functions are private and should be declared static. 2017-09-03 12:20:13 -06:00
Gregory Nutt
789e204141 Correct naming of fields in struct alm_rdalarm_s. Should not be the same as the corresponding fields of struct alm_setalarm_s. The whole purpose of that naming convention is to keep the field names unique. 2017-09-03 09:51:47 -06:00
Gregory Nutt
92b3c9477a Port Boris Astardzhiev RTC change for STM32L4 to STM32F7 2017-09-03 08:39:02 -06:00
Jussi Kivilinna
fe7d8c941c stm32f7: do not enable read-modify-write on DTCM. "AN 4667 - STM32F7 Series system architecture and performance" recommends to disable read-modify-write on DTCM: "If the DTCM-RAM is used as data location and the variables used are byte or/and halfword types, since there is no ECC management in this RAM on the STM32F7 Series, it is recommended to disable the read-modify-write of the DTCM-RAM in the DTCM interface (inthe DTCMCR register) to increase the performance." 2017-09-01 08:01:54 -06:00
Juha Niskanen
809569cda9 STM32L4 ADC: implement peripheral 2017-08-28 07:05:33 -06:00
Juha Niskanen
a2dc88e075 STM32, STM32L4, STM32F7 ADC: fix channel 18 sample time 2017-08-28 07:05:33 -06:00
David Sidrane
ef42c25140 stm32f7:SDMMC add dcache alignment check in dma{recv|send}setup 
In the where CONFIG_SDIO_PREFLIGHT is not used and
   dcache write-buffed mode is used (not write-through)
   buffer alignment is required for DMA transfers because
   a) arch_invalidate_dcache could lose buffered writes data
   and b) arch_flush_dcache could corrupt adjacent memory if
   the buffer and the bufflen, are not on ARMV7M_DCACHE_LINESIZE
   boundaries.
 2017-08-17 09:51:37 -10:00
David Sidrane
1e7ddfea8e stm32f7:SDMMC remove widebus limitation on DMA 
There is no documantation for the STM32F7 that limits DMA on
   1 bit vrs 4 bit mode.
 2017-08-17 09:48:46 -10:00
David Sidrane
dffab2f4dd stm32f7:DMA add dcache alignment check in stm32_dmacapable 
In the case dcache write-buffed mode is used (not write-through)
   buffer alignment is required for DMA transfers because
   a) arch_invalidate_dcache could lose buffered writes data
   and b) arch_flush_dcache could corrupt adjacent memory if
   the maddr and the mend+1, the next next address are not on
   ARMV7M_DCACHE_LINESIZE boundaries.
 2017-08-17 09:39:14 -10:00
David Sidrane
38cbf1f660 stm32f7:DMA correct comments and document stm32_dmacapable 
Updated comment to proper refernce manual for STM32F7 not
   STM32F4.

   Added stm32_dmacapable input paramaters documentation.
 2017-08-17 09:35:50 -10:00
David Sidrane
ab578bb338 stm32f7:rtc Missing semicolon 2017-08-15 16:17:55 -10:00
Gregory Nutt
e224d354b8 STM32F7: Remove unsupported configuration item the crept in when header file was cloned. 2017-08-13 12:37:59 -06:00
Gregory Nutt
f6f4856cc6 Eliminate some warnings found in build testing. 2017-08-13 12:24:48 -06:00
Gregory Nutt
873de7b480 configs/*/README.txt: Update to the new URL for obtaining the ARM toolchain. 2017-08-13 07:18:19 -06:00
Gregory Nutt
2ab8852b29 STM32F7: Some STM32F7 builds failed in build testing due to undefined STM32_SRAM1_BASE. I think that is because stm32_allocateheap.c was not including chip/stm32_memorymap.h 2017-08-13 06:50:48 -06:00
Gregory Nutt
03c26df04a STM32F7 builds broken. This is a work around to at least keep them building. 2017-08-13 06:44:04 -06:00
Titus von Boxberg
55e9c8990c stm32_rcc: code style 2017-08-01 16:25:19 +02:00
Titus von Boxberg
a4e97d5daf Added functions for DSI clock source selection 2017-08-01 16:24:48 +02:00
Gregory Nutt
05ea22e9ab STM32F7: Fix for coding standard violations that came in with cd3ca1140e3b669676fd3ccbb4624643f33d6aae -- missed a file last time 2017-07-31 18:36:38 -06:00
Gregory Nutt
5f4fdb42be STM32F7: Fix for coding standard violations that came in with cd3ca1140e3b669676fd3ccbb4624643f33d6aae 2017-07-31 18:35:37 -06:00
Titus von Boxberg
604a6dc0fa improved help text 2017-08-01 01:23:28 +02:00
Titus von Boxberg
bdee01f492 added function for reset 2017-08-01 01:23:28 +02:00
Titus von Boxberg
0947b31fbb STM32_RCC_DCKCFGR2 has nothing to do with PLLI2S; PLLI2S is not dependent on LTDC, instead on SAICLK1/2 generated from PLLI2S 2017-08-01 01:23:28 +02:00
Titus von Boxberg
9d56dbb403 comment corrected 2017-08-01 01:23:28 +02:00
Titus von Boxberg
63bce1fc34 no board specific dithering values used; corrected comment; corrected dithering init 2017-08-01 01:23:28 +02:00
Titus von Boxberg
ec95720d13 corrected LIPOS/LIPCR calculation 2017-08-01 01:23:28 +02:00
Titus von Boxberg
28a53d8e25 change only polarity bits in LTDC_GCR 2017-08-01 01:23:28 +02:00
Titus von Boxberg
5de2468521 comments corrected 2017-08-01 01:23:28 +02:00
Titus von Boxberg
69aca28e87 commented 2017-08-01 01:23:28 +02:00
Titus von Boxberg
ec43001d91 HEAP2 depends on CONFIG_ARCH_HAVE_HEAP2, not on particular FMC RAM type 2017-08-01 01:23:28 +02:00
Titus von Boxberg
777b17928f corrected register debugging 2017-08-01 01:23:28 +02:00
Titus von Boxberg
1944ab6f9b added missing config option for register value debugging 2017-08-01 01:23:28 +02:00
Titus von Boxberg
dc392a6c68 enable APB2 DSI clock 2017-08-01 01:23:28 +02:00
Gregory Nutt
5f31999b75 Trivial fix to spacing 2017-07-27 11:50:59 -06:00
Titus von Boxberg
28eab902d0 No FSMC, only FMC for STM32F7 2017-07-27 18:27:01 +02:00
Gregory Nutt
c3b552e072 Minor cosmetic updates from review of last PR. 2017-07-20 07:39:57 -06:00
Titus von Boxberg
a20c3b17ce warning message when using DSI (for debugging) 2017-07-19 20:39:27 +02:00
Titus von Boxberg
7b07471ece documentation update to f7 2017-07-19 19:14:50 +02:00
Titus von Boxberg
6d29a04752 naming errors/inconsitencies/typos 2017-07-19 19:14:49 +02:00
Titus von Boxberg
1241960d4a STM32F7: Switch from CCM to DTCM 2017-07-19 19:07:53 +02:00
Titus von Boxberg
071b2dda28 compileable with LTDC_INTERFACE and LTDC_USE_DSI 2017-07-19 19:07:53 +02:00
Titus von Boxberg
e67ba8c88d option for DSI output 2017-07-19 19:07:53 +02:00
Titus von Boxberg
d590ba7ab2 do not enforce CONFIG_STM32_CCMEXCLUDE for CONFIG_ARCH_CHIP_STM32F7, macro rename STM32 -> STM32F7, #include corrections 2017-07-19 19:07:53 +02:00
Titus von Boxberg
1826c1165a macro rename STM32 -> STM32F7, #include corrections 2017-07-19 19:07:53 +02:00
Titus von Boxberg
32e417c3ac renamed STM32_LCDTFT_BASE to STM32_LTDC_BASE for consistency 2017-07-19 19:07:53 +02:00
Titus von Boxberg
58053fef0f macro rename STM32 -> STM32F7 2017-07-19 19:07:53 +02:00
Titus von Boxberg
ec3e4cabab added config and make stuff for stm32f7 ltdc 2017-07-19 19:07:53 +02:00
Titus von Boxberg
ea703b832a copied from stm32 2017-07-19 19:07:53 +02:00
Titus von Boxberg
07531de2e4 Copied files from stm32 2017-07-19 19:07:53 +02:00
Titus von Boxberg
f3267ddb71 I2C4_SDA can also be on GPIO PB7 2017-07-18 11:43:53 +02:00