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14325 Commits

Author SHA1 Message Date
Gregory Nutt
8e18e8ae54 arch/arm/src/max326xx: Get's past a few initial compile problems. Still a long road ahead. 2018-11-17 15:36:40 -06:00
Gregory Nutt
6d5c1ec64f arch/arm/src/max326xx: Add encodings that will be needed for GPIO pin configurations. 2018-11-17 15:01:21 -06:00
Gregory Nutt
61fd244fd3 Add support for the Maxim Integrated MAX32660-EVSYS board. 
Squashed commit of the following:

    arch/arm/src/max326xx and configs/max32660-evsys/nsh/defconfig:  Work out some issues related to MAX326xx configuration.

    configs/max32660-evsys:  Add unverified board support framework.
 2018-11-17 13:24:09 -06:00
Anthony Merlino
4d574e7a60 Merged in antmerlino/nuttx/stm32f2-write-protect (pull request #762) 
arch/arm/stm32: stm32_flash_writeprotect supported the same for STM32F20XX as STM32F4XXX

Approved-by: GregoryN <gnutt@nuttx.org>
 2018-11-17 17:29:29 +00:00
Gregory Nutt
a427a40bd0 arch/arm/src/max326xx/chip: Add MAX32660 SPIMSS register definition header files. 2018-11-17 11:21:29 -06:00
Gregory Nutt
1527720be9 arch/arm/src/max326xx/chip: Add SPI register definition header file. 2018-11-17 10:47:57 -06:00
Gregory Nutt
854f171c66 arch/arm/src/max326xx/chip: Add I2C register definition header file. 2018-11-17 09:19:17 -06:00
Mateusz Szafoni
6673ae3e9c arch/arm/src/stm32/stm32_pwm.c: STM32 MOE is not being appropriately handled for PWM for advanced timers. It is only ever reset and so no PWM train is generated. This change addresses this. Noted by Dave Marples. 2018-11-17 06:55:19 -06:00
Gregory Nutt
8000e0b263 arch/arm/src/max326xx/Kconfig: Needs to select CONFIG_UARTn_SERIALDRIVER. 2018-11-17 06:36:25 -06:00
Gregory Nutt
13d902a0a5 arch/arm/src/max326xx: Bring in some mostly standard, ARMv7-M, 'boilerplate' files. 2018-11-16 15:33:01 -06:00
Gregory Nutt
06f132c5d0 Brings in WIP port for the Maxim Integrated MAX326xx MCU family. Not really very much in place yet so marked EXPERIMENTAL in Kconfig file. 
Squashed commit of the following:

    Update a README.  Mark MAX326XX as EXPERIMENTAL before bringing into master.
    arch/arm/src/max326xx/chip:  Add MAX32660 TMR register definition header files.
    arch/arm/src/max326xx/chip:  Add MAX32660 WDT register definition header files.
    arch/arm/src/max326xx/chip:  Add MAX32660 RTC register definition header files.
    arch/arm/src/max326xx/chip:  Add MAX32660 UART register definition header files.
    arch/arm/src/max326xx/chip:  Add DMA register definition header files.
    Update some comments explaining what is meant by a 'chip family'
    arch/arm/src/max326xx/chip:  Add GPIO register definition header files.
    arch/arm/src/max326xx/chip:  Add FLC register definition header files.
    arch/arm/src/max326xx/chip:  Add FCR, PWRSEQ, and SIR register definition header files.
    arch/arm/src/max326xx/chip:  Add ICC register definition header file.
    arch/arm/src/max326xx/chip:  Add memory map header files.
    arch/arm/include/max326xx:  Minor fleshing out.
    arch/arm/arm/include/max326xx: Add basic support for Maxim MAX326xx family.  arch/arm/Kconfig and arch/arm/src/max326xx/Kconfig:  Add basic condiguration support for the MAX326xx.
 2018-11-16 13:17:47 -06:00
Gregory Nutt
be1567d924 Trivial changes from review or last PR. 2018-11-15 15:08:02 -06:00
David Sidrane
2a13f13c0f Merged in david_s5/nuttx/master_imxrt_headers (pull request #761) 
imxrt:Add FLEXPWM

Approved-by: GregoryN <gnutt@nuttx.org>
 2018-11-15 21:02:38 +00:00
David Sidrane
a92a025e5f Merged in david_s5/nuttx/master_f4_446_469_GPIO (pull request #760) 
stm32:STM32F446 & STM32F469 correct PC1 SPI assignments

Approved-by: GregoryN <gnutt@nuttx.org>
 2018-11-15 17:14:49 +00:00
Xiang Xiao
dbf01d12b7 Assertions: Identify the running task correctly when dumping task state information. It takes time to switch to the target task after g_readytorun has been modified. If panic/assert happen during this period, the dump will contain the incorrect and confusing information due to the difference between the real running task and the return value of this_task(). This change resolve this problem by adding g_running_task to track the real running task through the context switch. 2018-11-15 07:11:51 -06:00
David Sidrane
c6db972702 - imxrt: Add PIT, GPT, and QIMER(TMR) header files 
Squashed commit of the following:

    imxrt: Add QTIMER(TMR)
    imxrt: Add GPT
    imxrt: Add PIT
 2018-11-13 16:34:59 -06:00
Dave Marples
9b68efe251 arch/arm/src/imxrt/imxrt_usdhc.c: Improve SD card handling in the DMA case. For now I think we can consider this complete for both Interrupt and DMA transfers. There is other stuff to add (high speed, low voltage, DDR etc.) later, 2018-11-13 06:41:27 -06:00
Dave Marples
50a1b9eddf arch/arm/src/imxrt: This commit complete the interrupt driven USDHC1 functionality for the IMXRT EVKB. There is more work to be done to complete DMA mode and further changes will follow. 2018-11-12 13:47:44 -06:00
Gregory Nutt
a42c5e57fc Cosmetic updates from review of last PR. 2018-11-12 09:53:44 -06:00
Mateusz Szafoni
becb667f56 Merged in raiden00/nuttx_pe (pull request #758) 
stm32/stm32_adc: major refator

stm32/stm32_adc: use STM32 ADC IP core version and ADC available functions instead of chip family names in conditional compilation

stm32/chip: replace family specific ADC headers with STM32 ADC IP core version headers

stm32/stm32_adc: configurable sample time supported for all chips, not only L1

stm32/stm32_adc: enable/disable interrupts supported for all chips, not only L1

stm32/stm32_adc: resolution configuration

stm32/stm32f33xxx_adc: remove wrong assertion

configs/nucleo-f303ze: support for ADC and ADC example

configs/stm32f429i-disco: support for ADC and ADC example

Approved-by: GregoryN <gnutt@nuttx.org>
 2018-11-12 15:45:55 +00:00
Xiang Xiao
543f4ed8ec arch/ all assertion functions: up_assert move the register dump to first make the more important info first 2018-11-11 12:53:59 -06:00
Xiang Xiao
dfe788be25 arch/ all assertion functinos: up_stackdump dump the full stack if stack overflow the stack info is very useful to find the backtrace 2018-11-11 12:52:36 -06:00
Xiang Xiao
e4106a3744 arch/ assertions files: up_registerdump capture the general register if not yet saved and up_saveusercontext is implemented, the register dump is very useful to find the cause of failure. 2018-11-11 12:50:50 -06:00
Xiang Xiao
084904c40b arch/arm/src: Remove general register dump from fault handler since the same info already dump in PANIC 2018-11-11 12:47:03 -06:00
Gregory Nutt
2b3ec4172d arch/: Add 'BOARD_ASSERT_RESET_VALUE' in config/Kconfig and replace reboot status '0' to 'CONFIG_BOARD_ASSERT_RESET_VALUE'. 2018-11-10 14:06:46 -06:00
Xiang Xiao
e6ebbe875a arch/arm/src/common/up_exit.c: Fix typo. Caused compiler error when system debug enabled. 2018-11-10 14:01:21 -06:00
Xiang Xiao
f71cd2678a arch/sim/src/up_netdriver.c: Fix error 'invalid operands to binary &' 2018-11-10 14:00:13 -06:00
Juha Niskanen
e37f260d67 arch/arm/src/stm32l4: add initial support for STM32L412 and STM32L422 chips 2018-11-09 09:54:20 -06:00
Xiang Xiao
28abd336da arch/sim/src/up_hostfs.c: Support S_IFSOCK, DT_LNK, O_DIRECT and O_SYNC 2018-11-09 09:13:55 -06:00
Petteri Aimonen
ec6c7839d3 Merged in paimonen/nuttx/pullreq_STM32_NDAC_fix (pull request #752) 
NuttX: STM32F407VG has only one DAC

NDAC=2 causes compilation error when trying to use e.g. STM32_DAC1_CR macro.

Approved-by: GregoryN <gnutt@nuttx.org>
 2018-11-09 12:15:57 +00:00
David Sidrane
f6e21619e2 Merged in david_s5/nuttx/master_imxrt_boards (pull request #751) 
imxrt:Clock config fixes and board.h sets sources and divisors

* imxrt:clockconfig bug fix & Board config set clocks

      Fixed logic that was not clearing bits as ~ was
      mising in &= mask operations.

      Use valuse from the board.h file so set the Mux that
      selects the clock sources.

      Use board defined PODF values to select clock.

      Only configure USDHC2 clocks when board defines clocks.

* imxrt1050-evk:Board setting used to set  LSPI and USDHC Clocks

Approved-by: GregoryN <gnutt@nuttx.org>
 2018-11-09 00:52:50 +00:00
Xiang Xiao
247414c6ad drivers/mtd and other MTD drivers: Remove mtd_procfsoperations since we can now get the same information from inode 2018-11-08 09:46:11 -06:00
Gregory Nutt
9c3e65f15f net/mld: Fix a few compilation problems that cropped up in a different network configuration. Fix a logic error in setting the 'Other Querier Present' timer. Various cosmetic improvements. 2018-11-07 18:21:21 -06:00
Gregory Nutt
68e45d0453 Reported by Anonymous in Bitbucket Issue #129: 
When MIPS port is built for microMIPS and then loaded as an application, the __start entry point is entered in microMIPS mode, but the CPU core initialization code there misses to set the config3ISAOnExc bit to 1. Subsequently, exceptions are entered in MIPS32 mode, but the code base was built for microMIPS.
 2018-11-07 10:48:33 -06:00
Gregory Nutt
e640635c41 arch/arm/src/imxrt/imxrt_gpioirq.c: Fix some inconsistent spacing and indentation noted in review of previous commit. 2018-11-06 16:51:46 -06:00
David Sidrane
a0745bbef6 Merged in david_s5/nuttx/master_imxrt (pull request #748) 
Adding imxrt 106x

* imxrt:Fix comment in imxrt105x_memorymap

* imxrt:Add imxrt1060 memory map

* imxrt:Add imcrt106x to imxrt_memorymap

* imxrt:Add i.MX RT 106x to Kconfig

* imxrt:Moved IMXRT_GPIO_NPORTS to chip.h & fixed comments

* imxrt:105x IRQ fix comment

* imxrt:gpioirq GPIO4,5 using wrong boundry

* imxrt:Add RT106x irq headers & Kconfig

* imxrt:Add rt106x GPIO chip headers

* imxrt:Extend Number of GPIO ports

* imxrt:Add 106x DMAMUX header

* imxrt:iomuxc add 106x

* imxrt:106x iomuxc extend Indexes

* imxrt:pinmux Add 106x

* imxrt:clockconfig use imxrt_memorymap.h

* imxrt:allocateheap use OCRAM2 as BASE when avaialbe

Approved-by: GregoryN <gnutt@nuttx.org>
 2018-11-06 22:47:20 +00:00
Anthony Merlino
7f10234468 Merged in antmerlino/nuttx/spi-initialize (pull request #746) 
This change is needed specifically for the case where a bootloader sets the SPE bit before starting NuttX.  In that case, the test in the SPI driver is bogus.  This change fixes that by assuring that NuttX has booted and initialized at least once (whether or not SPE is set) before the driver starts refusing to initialize.

arch/arm/stm32*: Don't rely on SPI_CR1_SPE to determine if peripheral has been initialized yet.

Approved-by: GregoryN <gnutt@nuttx.org>
 2018-11-01 16:00:27 +00:00
Dave Marples
ae054b93bb arch/arm/src/imxrt/imxrt_usdhc.c: Initial commit of the i.MXRT SDHC driver. This driver is partially functional, working in PIO mode. DMA support and additional testing are needed. 2018-11-01 06:26:51 -06:00
Gregory Nutt
6d93658ff8 Add new configuratin CONFIG_NET_MCASTGROUP. This option is selected automatically if either CONFIG_NET_IGMP or CONFIG_NET_MLD are selected. Most conditional logic based on CONFIG_NET_IGMP replaced with conditioning on CONFIG_NET_MCASTGROUP. 2018-10-31 15:03:51 -06:00
Gregory Nutt
a3c67df91d arch/arm/src/imxrt: Add full support for the LPSPI in poll mode; includes a minor fix for LPI2C. 2018-10-31 12:50:05 -06:00
Anthony Merlino
7750e55d15 Merged in antmerlino/nuttx/stm32f20xx-kconfig-fix (pull request #745) 
Fixes Kconfig options to include all STM32F20XX processors, not just STM32F207

* arch/arm/src/stm32: Fixes Kconfig options to include all STM32F20XX processors, not just STM32F207

* arch/arm/src/stm32: Removes redundant STM32_STM32F429 depends from Kconfig. STM32F4XXX already does this

Approved-by: GregoryN <gnutt@nuttx.org>
 2018-10-31 03:53:13 +00:00
Gregory Nutt
f4a5f7a3b9 arch/risc-v/src/gap8: The correct name of the chip.h should be gap8.h. This in analogy to other architectures. There is frequently a chip.h header file in the arch/src directory, but it has a different function. 2018-10-30 16:34:56 -06:00
Gregory Nutt
552f53e578 arch/risc-v/src/gap8/gap8_tim.c: Fix a typo that I introduced in my review. 2018-10-30 11:19:06 -06:00
Gregory Nutt
9e0ad7b98a arch/risc-v/src/gap8/startup_gap8.S: Remove commented out call to a non-existent function. 2018-10-30 10:39:51 -06:00
Gregory Nutt
e4562fc538 This commit brings in support for the GAP8 architecture. The GAP8 is a 1+8-core DSP-like RISC-V MCU. Also included is support for the Gapuino GAP8 evaluation board. 
Squashed commit of the following:

Author: Gregory Nutt <gnutt@nuttx.org>

    Completes review of configs/gapuino.
    arch/risc-v/include/gap8/chip.h:  Replace the moved chip.h header file with a dummy chip.h header file just to keep the system happy.
    Move include/gap8/chip.h to src/gap8/chip.h.  Internal details should not be exposed outside of arch/ and configs/.  Review all headers files in src/gap8
    Review of arch/risc-v/include.

Author: hhuysqt <hyq9606@126.com>

    corrected author and email
    Add app initialization, add signal support, cleanup irq context and configs
    fix some warnings
    gapuino initial port
    GAP8 initial port
 2018-10-30 09:38:50 -06:00
Mateusz Szafoni
2a4ed884b5 Merged in raiden00/nuttx_pe (pull request #743) 
arch/arm/stm32: add support for STM32F303xD/E; configs: add basic support for nucleo-f303ze

Approved-by: GregoryN <gnutt@nuttx.org>
 2018-10-28 16:39:56 +00:00
Gregory Nutt
11cc274eef Trivial, cosmetic changes from review of last PR. 2018-10-28 06:55:20 -06:00
Mateusz Szafoni
7329c81503 Merged in raiden00/nuttx_h7 (pull request #742) 
Add basic SPI support for H7

* stm32h7: basic SPI support (nodma, noirq)

* nucleo-h743zi: nrf24l01 support

* nrf24l01.c: fix compilation errors

* stm32h7x3xx_rcc.c: enable SYSCFG clock

Approved-by: GregoryN <gnutt@nuttx.org>
 2018-10-28 12:43:08 +00:00
Gregory Nutt
511c90d050 arch/x86/src/qemu/qemu_head.S: Correct .bss, IDLE stack, heap organization. 2018-10-26 15:48:22 -06:00
Daniel P. Carvalho
578114a74f configs/nucleo-l432kc: Added support for AT45DB Serial Flash 2018-10-25 16:12:59 -06:00