Commit Graph

765 Commits

Author SHA1 Message Date
Huang Qi
904f7aabda arch/risc-v: Use riscv_fpuconfig to enable FPU
Use common function instead of chip specified code.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-30 01:33:04 +08:00
Huang Qi
20c511fcf1 arch/risc-v: Rename up_fpuconfig to riscv_fpuconfig
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-30 01:33:04 +08:00
Ville Juven
43d5f60a74 MPFS: Fix issue with external interrupt detection
The bitmask overflow'd. Failing test is at mpfs_irq_dispatch / line 69
2022-03-28 22:40:11 +08:00
Huang Qi
83a5e9958f arch/risc-v: Correct comments for current implementations
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-28 13:41:57 +08:00
Huang Qi
35f9265483 arch/risc-v: Move fpu [re]store to common place
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-28 13:41:57 +08:00
Lee Lup Yuen
c67272f9c8 riscv/bl602: Enable SPI Master in SPI Poll Send
## Summary

SPI Poll Send `bl602_spi_poll_send()` doesn't send any SPI Data because it doesn't enable SPI Master and it doesn't clear the SPI FIFO. Also it hangs because it loops forever waiting for the FIFO.

We fix this problem by moving the code that enables SPI Master and clears the FIFO, from SPI Poll Exchange `bl602_spi_poll_exchange()` to SPI Poll Send. (Note that SPI Poll Exchange calls SPI Poll Send)

[More Details Here](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

## Impact

This problem affects all NuttX Drivers that call `SPI_SEND()` on BL602, including the ST7789 Display Driver.

Previously `SPI_SEND()` didn't send any SPI Data and never returns, because it loops forever waiting to receive data.

Now `SPI_SEND()` sends data and returns correctly.

[More Details Here](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

## Testing

We tested the modified SPI Poll Send with NuttX ST7789 Driver and a Logic Analyser on PineCone BL602:

-  [Testing with Logic Analyser](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

We also tested LVGL with ST7789 on PineCone BL602:

-  [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)

As for the modified SPI Poll Exchange, we tested with Semtech SX1262 SPI Transceiver on PineCone BL602:

-  [Testing SPI Poll Exchange](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-25)
2022-03-28 13:32:27 +08:00
Xiang Xiao
8c8c60f70a arch: Add -fsanitize=kernel-address to ARCHCPUFLAGS if CONFIG_MM_KASAN=y
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-27 23:01:47 +03:00
ligd
e87d262c7f arch/Toolchain.defs: add wildcard for EXTRA_LIBS
VELAPLATFO-1491

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-27 22:53:58 +03:00
Huang Qi
052c071867 arch/risc-v: Minor style change
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-26 16:52:13 +09:00
Huang Qi
494230a841 arch/risc-v: Improve performance of context switch
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-26 07:19:09 +09:00
Petro Karashchenko
7afedda89e arch/risc-v: improve style consistency accross chip variants
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-25 10:26:15 -03:00
Ville Juven
44bec4cf8e RISC-V: Add missing code to dumpstate
Just add the kernel stack dumping for completeness
2022-03-24 00:15:28 +08:00
Ville Juven
77e90d9c87 RISC-V: Include support for kernel stack
Preparation for CONFIG_BUILD_KERNEL=y, which requires that a kernel
stack is allocated for each user process.
2022-03-24 00:15:28 +08:00
Huang Qi
9cffc105c8 arch: Show assigned cpu in dump task
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-23 22:18:15 +08:00
Huang Qi
f09ea317c1 risc-v/qemu-rv: Restore FPU context after context switch
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-23 19:30:04 +08:00
Petro Karashchenko
68902d8732 pid_t: unify usage of special task IDs
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-22 21:22:32 +08:00
Petro Karashchenko
3fff4508c7 netinitialize: call xxx_netinitialize unconditionally
The xxx_netinitialize is defined to a function only if
CONFIG_NET=y and CONFIG_NETDEV_LATEINIT=n.  Otherwise it
is defined to an empty macro.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-19 17:41:33 +08:00
Huang Qi
00efcd3308 arch/risc-v: Merge riscv_getnewintctx into common
And also mask the bits which should be preserved (from ISA spec)

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-19 17:38:18 +08:00
Janne Rosberg
d72a523c00 risc-v/mpfs: add support for ethernet 2022-03-18 17:22:27 +02:00
Janne Rosberg
07aeb12b30 risc-v/common: add call to riscv_netinitialize() 2022-03-18 17:22:27 +02:00
Eero Nurkkala
ec2352a4f9 risc-v/mpfs: usb: fix ep0 read done
USB EP0 reads data from the fifo but doesn't mark the read
done which adds significant delays. Fix this unnecessary
slowdown due to operation timeouts by finishing the read
properly.

Also add a missing function description to the function
mpfs_ep_set_fifo_size().

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-18 22:47:29 +08:00
Ville Juven
15960f25a5 MPFS: Add board_memorymap.h
Move the target specific memory map to a separate file so there is no
need to copy&paste the __xxram_start etc linker symbols to each file
that needs them.

Also add MMU flags for I/O and kernel areas, they will be needed
when the kernel runs with virtual addresses also.
2022-03-18 09:35:00 -03:00
Ville Juven
ade848b60a MPFS: Use linker symbols for heap allocation 2022-03-18 18:20:12 +08:00
Ville Juven
75afe491ad RISC-V: Prepare for CONFIG_BUILD_KERNEL
- Thread context prior to system call needs to be preserved
- Allocate a kernel heap
2022-03-18 18:20:12 +08:00
Ville Juven
195705d11f MPFS: Create centralized module for PLIC address handling
Reduce complexity and copy-paste amount by implementing a module
to handle calculating PLIC offsets.
2022-03-18 18:20:12 +08:00
Ville Juven
745f00e77d MPFS: Use riscv_mhartid to obtain hartid
Preparation for S-mode, read mhartid via function call instead of
directly from the machine mode register
2022-03-18 18:20:12 +08:00
Ville Juven
f8ffcbbf36 MPFS: Remove definition and reference to MPFS_PLIC_CTRL
The register does not exist. c906 implementation has it, but MPFS does not.
2022-03-18 18:20:12 +08:00
Ville Juven
0f91eab626 MPFS: Protected mode, fix MMU mapping
The mapped vaddr was wrong, don't want to map the page tables, but
the user space area (start of .text) instead.
2022-03-18 18:20:12 +08:00
Ville Juven
9269a86d00 RISC-V: Add common data memory and instruction barriers 2022-03-18 18:20:12 +08:00
Gustavo Henrique Nihei
baa09aa999 risc-v/esp32c3: Remove deprecated option for disabling atomics support
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-17 23:40:29 +08:00
Huang Qi
807304f283 arch/risc-v: Rework riscv_get_newintctx
Some fields of mstatus were marked as Reserved Writes Preserve Values, Reads Ignore Values (WPRI),
so we must keep its origin value with addition flags.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-17 15:43:30 +08:00
Huang Qi
9cc0a609bd arch/risc-v: Correct stack coloration in riscv_cpu_boot
In smp system riscv_cpu_boot run in idle task so there is a overlap with the origin coloration range and in used stack.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-16 14:12:45 +02:00
Eero Nurkkala
c38d547900 risc-v/mpfs: usb: fix ep0 stall/resume and rx reads
Fix EP0 stall and resume properly. EP0 wasn't clearly addressed
on stall / resume operations.

Also fix data reads that provide garbage for the first request.
It has always random data as it's completed prior to any read
operation.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-16 00:59:25 +08:00
Ville Juven
e843c441de RISC-V: Fix nasty bug in PMP region test
The end address was not handled correctly, it is not a part of a mapped
region.
2022-03-15 18:59:20 +02:00
Petro Karashchenko
b04447d066 timer_lowerhalf: minor improvements
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-15 10:30:48 +08:00
Xiang Xiao
b6bc460b2c arch: Make the comment and definition of CONFIG_SYS_RESERVED correctly
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-14 22:51:00 +02:00
Xiang Xiao
54e630e14d arch: Merge up_arch.h into up_internal.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-14 09:32:17 +02:00
Xiang Xiao
e800f54bfd arch/mpfs: Don't include nuttx header file in mpfs_opensbi.c
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-14 09:32:17 +02:00
Xiang Xiao
c96c96a399 drivers: Merge the common driver initialization into one place
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-13 11:24:48 -03:00
Xiang Xiao
ea614090cd arch/risc-v: Change hex number to low case in csr.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-13 10:17:25 +02:00
Jukka Laitinen
d9607f71d2 Revert "arch/risc-v: Correct FPU register save area in riscv_copystate"
This reverts commit 86358bff3bc814efb564a4427b4bcd6c3c91dbf0.
2022-03-11 23:43:41 +08:00
Jukka Laitinen
81a19c1ce8 arch/riscv/src/mpfs: Make cleaner pinmux configurations for USB
Mux USB IO pins one-by-one using package specific pinmux definitions. This avoids accidentally overwriting IO settings for other pins.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-03-11 00:22:43 +02:00
Xiang Xiao
c0f3ac97bc arch/risc-v: Update opensbi to 4998a712b2ab504eff306110879ee05af6050177
include theis commit:
commit 6ad8917b7e27e5e80fb9268492b9111b17ed2024
Author: Petro Karashchenko <petro.karashchenko@gmail.com>
Date:   Fri Jan 28 09:13:23 2022 +0200

    lib: fix compilation when strings.h is included

    In a systems that provide strings.h and it is included
    together with sbi_bitops.h the compilation error appears.
    The ffs() and fls() are provided by strings.h

    Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
    Reviewed-by: Anup Patel <anup@brainfault.org>

and fix this warning:
Error: include/sbi/sbi_bitops.h:47:19: declaration of 'ffs' shadows a built-in function
 static inline int ffs(int x)
                   ^~~

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-10 19:46:01 +02:00
Huang Qi
8267a76186 arch/risc-v: Implement SYS_save_context in swint
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-10 16:11:14 +08:00
Huang Qi
7022c630fe arch/risc-v: Correct FPU register save area in riscv_copystate
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-10 16:11:14 +08:00
Eero Nurkkala
a21a396bd8 risc-v/mpfs: usb: apply review fixes
PR#5688 review fixes are in this patch. The PR was already
merged so the fixes are addresses here as a separate patch.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-09 10:26:56 +02:00
Huang Qi
c6e636a871 arch/risc-v: Save/Load float register in setjmp
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-09 10:15:54 +02:00
Huang Qi
8dedf1d9af arch/risc-v: Correct handling of QPFPU and DPFPU
If QPFPU enabled we will never enter the expected QPFPU branch since
option QPFPU depend on DPFPU.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-09 10:15:54 +02:00
Eero Nurkkala
4b2fbab998 risc-v/mpfs: usb: fix an unused variable warning
Fix an unused variable warning if the CONFIG_HAVE_USBTRACE
(and USB_DEBUG) aren't set.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-08 23:00:31 +08:00
Eero Nurkkala
8c1ab129ac risc-v/mpfs: add USB device driver
This adds a simple USB device driver for the mpfs. However,
this driver is still at its early phase. Only limited testing
with CDC/ACM has been conducted.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-08 16:49:29 +08:00