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13543 Commits

Author SHA1 Message Date
Gregory Nutt
92b3c9477a Port Boris Astardzhiev RTC change for STM32L4 to STM32F7 2017-09-03 08:39:02 -06:00
Boris Astardzhiev
b1eceb838b Extend the RTC framework with an alarm read ioctl (RTC_RD_ALARM). Through it consumer could get configuration settings about previously scheduled hardware alarms (active status, hours, minutes, seconds). 2017-09-03 08:39:02 -06:00
Mateusz Szafoni
daac3bd7f8 Merged in raiden00/nuttx (pull request #476) 
Master

* stm32_dac.c: fix compilation when DMA disabled for channel

* smps.h: update some comments

* smps.c: more sanity checks

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-02 19:52:21 +00:00
Jussi Kivilinna
fe7d8c941c stm32f7: do not enable read-modify-write on DTCM. "AN 4667 - STM32F7 Series system architecture and performance" recommends to disable read-modify-write on DTCM: "If the DTCM-RAM is used as data location and the variables used are byte or/and halfword types, since there is no ECC management in this RAM on the STM32F7 Series, it is recommended to disable the read-modify-write of the DTCM-RAM in the DTCM interface (inthe DTCMCR register) to increase the performance." 2017-09-01 08:01:54 -06:00
Juha Niskanen
258fa08e69 STM32L4 DAC: Fix naming so that DAC1 and DAC2 always refer to channels 1 and 2 
User should not be bothered by details like how many IP blocks there are. As no
current STM32L4 has second DAC block (channel 3), remove support for such
hypothetical hardware. DMA channels corrected.

Change-Id: I2cba7e55803871f1ff945538113f12cf5088f68d
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2017-09-01 10:01:03 +03:00
Juha Niskanen
0003ad171d STM32L4 DAC: separate DMA buffer configuration for channels 
Change-Id: Ibc6dc90b39b784b5534b8908eaf615bf1ddcb7ed
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2017-09-01 10:00:55 +03:00
Juha Niskanen
4025205772 STM32L4 DAC: add option for routing DAC output to ADC 
Actually write something to the DAC DMA buffer.

Change-Id: I1b2516ac26fb17f5242611b56be8926c5f40c2c7
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2017-09-01 10:00:46 +03:00
Gregory Nutt
91d473b816 Revert "stm32 FLASH allow non blocking operation on constrained devices" 
This reverts commit ad2ef95ddf.
 2017-08-31 15:14:26 -06:00
David Sidrane
9fc283526a Merged in david_s5/nuttx/master_stm32_flash (pull request #474) 
stm32 FLASH allow non blocking operation on constrained devices

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-08-31 18:04:07 +00:00
Sergey Ustinov
8c35b2ddca Add the set counter function for stm32 timers 2017-08-31 11:54:00 -06:00
David Sidrane
ad2ef95ddf stm32 FLASH allow non blocking operation on constrained devices 
On a very memory constrained device with a single task. The
   sem_wait and sem_post operations can be disabled, to save space.
   The default is blocking enabled.
 2017-08-31 07:47:37 -10:00
Sergei Ustinov
795650a2fb I'm worried about the stm32_tim_getcounter funtion. It returns always 32 bits. But major stm32 timers have 16 bits counters. I think, it's not a good idea to return the memory behind the TIMx_CNT register. This changes adds the register size checking. 2017-08-31 11:45:28 -06:00
Gregory Nutt
a7fd8eb203 Trivial removal of a blank line. 2017-08-31 11:36:18 -06:00
Gregory Nutt
27cfde9968 Protected/Kernel Builds: Review us of kmm_addregion vs. kumm_addregsion in other configurations. 2017-08-31 08:49:21 -06:00
Gregory Nutt
69f1399aa7 LPC43xx: Add external RAM to the user heap, not the kernel heap. 2017-08-31 08:12:42 -06:00
Alan Carvalho de Assis
ef3898c2dd LPC43xx: Modify up_allocate_(k)heap() to support PROTECTED mode 2017-08-31 07:58:16 -06:00
Gregory Nutt
9d3b1af1cd ARM syscall logic: Clear bit 0 in PC settings. Bit 0 is the thumb mode indication and should not be set in the PC. 2017-08-30 13:56:03 -06:00
raiden00pl
85c48de040 stm32_hrtim: add DMA configuration 2017-08-28 17:44:14 +02:00
Juha Niskanen
809569cda9 STM32L4 ADC: implement peripheral 2017-08-28 07:05:33 -06:00
Juha Niskanen
a2dc88e075 STM32, STM32L4, STM32F7 ADC: fix channel 18 sample time 2017-08-28 07:05:33 -06:00
Juha Niskanen
e8cd2f88b8 STM32L4 RCC: enable ADC clock source 2017-08-28 07:05:32 -06:00
Alan Carvalho de Assis
81d6cefd65 Add support to STM32F433RC 2017-08-28 07:05:32 -06:00
raiden00pl
5695a55569 stm32_dac.c: support external triggering for DMA transfer 2017-08-27 18:25:55 +02:00
Mateusz Szafoni
ea35f31f73 Merged in raiden00/nuttx (pull request #469) 
Master

* stm32f0/Kconfig: remove references to HRTIM

* STM32F33: missing SYSCFG CFGR3 definitions

* stm32_hrtim.h: remove redundant definitions

* stm32_hrtim.c: fix DAC triggers configuration

* stm32_hritm.c: warning message when default value selected

* stm32_hrtim.c: missing master timer logic

* stm32_hrtim.c: add more assertions

* stm32_dac.c: fix conditional

* stm32_dac.c: conditional logic for timer triggering

* stm32_dac.c: fix TSEL configuration when HRTIM

* stm32_dac.c: unnecessary condition

* stm32_dac.c: DMA request remapping

* stm32_dac.c: fix commpilation errors

* stm32_dac.c: add DMA buffers initialization logic

* stm32_hrtim.c: enable DAC triggering

* analog/comp.c: fix compilation errors when poll disabled

* stm32_hrtim.c: remove doubled assertions

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-08-27 12:49:53 +00:00
Gregory Nutt
7858ed834b Minor, cosmetic changes from review of last comment. 2017-08-27 06:48:42 -06:00
Masayuki Ishikawa
cc9c8260f0 arch/arm/src/lc823450: Add eMMC/SD and USB support 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2017-08-27 19:11:07 +09:00
Masayuki Ishikawa
56bf5b2a98 arch/arm/src/lc823450: Conform to the NuttX coding style 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2017-08-27 19:11:03 +09:00
Gregory Nutt
f43f372823 Update some comments. 2017-08-26 11:50:41 -06:00
Nickolay Semyonov (RPI)
1fcc7ec38e Ommitted a file in previous commit 2017-08-26 11:45:08 -06:00
Gregory Nutt
48c27f8ffc Simulator: Adds necessary functionality to build Simulator under ARM Linux. Tested only on Raspberry3. Currently setjmp/longjmp do not save/restore floating point registers. Patch provided by Bitbucket user nbkolchin. 2017-08-26 11:38:44 -06:00
Juha Niskanen
1be5f0a3fc STM32L4 COMP: comparators share RCC enable bit with SYSCFG 2017-08-25 07:06:39 -06:00
Juha Niskanen
1152e4868b STM32L4 DAC: report transfer as completed in DMA callback. Without this even O_NONBLOCK writes block the calling task if DAC was using DMA. 2017-08-25 07:05:11 -06:00
Juha Niskanen
874947d7e5 STM32L4 TIM: TIM15,16,17 are always in APB2 2017-08-25 07:02:21 -06:00
Gregory Nutt
dc8f3778a9 drivers/sensors: Fix more naming of configurations to be compliant for two more drivers. Still a few more to go. 2017-08-24 10:26:53 -06:00
Jussi Kivilinna
310a29227a drivers/lcd: add DD-12864WO-4A/SSD1309 support to SSD1306 driver 2017-08-22 08:32:52 -06:00
Juha Niskanen
d7ae3d74c3 STM32L4 ADC: correct EXTSEL macros 2017-08-22 06:49:48 -06:00
Pekka Ervasti
6b1ccef2f9 STM32L4 COMP: bind to upper half comp driver 2017-08-22 06:47:57 -06:00
raiden00pl
a5997cb186 stm32_dac: add support for HRTIM triggering 2017-08-21 19:46:18 +02:00
raiden00pl
a5f3a5848d stm32_dac.c typo 2017-08-21 18:59:21 +02:00
raiden00pl
db7a94288f stm32f33xxx_dma.h: typos 2017-08-21 18:50:07 +02:00
raiden00pl
b460f2bca1 stm32f10xxx_dma.h: fix DAC names and remove STM32F33 section 2017-08-21 18:50:07 +02:00
raiden00pl
104ff2b5d8 stm32_dac: separate dma buffer configuration for channels 2017-08-21 18:50:07 +02:00
Juha Niskanen
37867ae3b9 chip.h edited online with Bitbucket: correct some STM32_NDAC 2017-08-21 07:30:58 +00:00
Mateusz Szafoni
ccd421b158 stm32_dac.c edited online with Bitbucket 2017-08-20 18:47:44 +00:00
raiden00pl
04743f3e77 stm32_dac: change name convention. Previous naming was confusing 2017-08-20 20:19:53 +02:00
raiden00pl
0bed6ac8b4 STM32F33: correct STM32_NDAC 2017-08-20 20:07:50 +02:00
raiden00pl
a8e8862ef9 stm32_dac.c: fix some configuration logic. When STM32_NDAC is greather than 1, then second channel is always DAC1OUT2. 2017-08-20 19:02:56 +02:00
raiden00pl
1479fd6075 stm32_comp: add default INM configuration and some missing COMP1,3,5,7 code 2017-08-20 10:45:55 +02:00
raiden00pl
30ebd32ab4 stm32f33xxx_pinmap.h: missing define 2017-08-20 10:45:55 +02:00
raiden00pl
241c42447f stm32f33xxx_comp.h: typos 2017-08-20 10:45:55 +02:00
raiden00pl
01c98df18c STM32F33: remove redundant DAC file 2017-08-20 10:45:55 +02:00
David Sidrane
b594d43d24 Merged in david_s5/nuttx/upstream_dma_dcache_fix (pull request #462) 
STM32F7:SDMMC, DMA dcache check in stm32_dmacapable and  SDMMC stm32_dma{recv|send}setup

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-08-17 20:14:24 +00:00
David Sidrane
ef42c25140 stm32f7:SDMMC add dcache alignment check in dma{recv|send}setup 
In the where CONFIG_SDIO_PREFLIGHT is not used and
   dcache write-buffed mode is used (not write-through)
   buffer alignment is required for DMA transfers because
   a) arch_invalidate_dcache could lose buffered writes data
   and b) arch_flush_dcache could corrupt adjacent memory if
   the buffer and the bufflen, are not on ARMV7M_DCACHE_LINESIZE
   boundaries.
 2017-08-17 09:51:37 -10:00
David Sidrane
1e7ddfea8e stm32f7:SDMMC remove widebus limitation on DMA 
There is no documantation for the STM32F7 that limits DMA on
   1 bit vrs 4 bit mode.
 2017-08-17 09:48:46 -10:00
David Sidrane
dffab2f4dd stm32f7:DMA add dcache alignment check in stm32_dmacapable 
In the case dcache write-buffed mode is used (not write-through)
   buffer alignment is required for DMA transfers because
   a) arch_invalidate_dcache could lose buffered writes data
   and b) arch_flush_dcache could corrupt adjacent memory if
   the maddr and the mend+1, the next next address are not on
   ARMV7M_DCACHE_LINESIZE boundaries.
 2017-08-17 09:39:14 -10:00
David Sidrane
38cbf1f660 stm32f7:DMA correct comments and document stm32_dmacapable 
Updated comment to proper refernce manual for STM32F7 not
   STM32F4.

   Added stm32_dmacapable input paramaters documentation.
 2017-08-17 09:35:50 -10:00
Gregory Nutt
06a12bea6c STM32L476VG Discovery: Add a knsh configuration that may be used to test the PROTECTED build mode. 2017-08-17 09:15:12 -06:00
Gregory Nutt
06473e89de Update MRF24J40 starhub configuration for the SAME70 Xplained. 2017-08-16 09:39:25 -06:00
David Sidrane
5ef33f3e58 Merged in david_s5/nuttx/upstream_missing_semi (pull request #459) 
stm32f7:rtc Missing semicolon

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-08-16 02:49:24 +00:00
David Sidrane
ab578bb338 stm32f7:rtc Missing semicolon 2017-08-15 16:17:55 -10:00
Gregory Nutt
dcb8df76d0 Fix argument to SPI initializatio function 2017-08-15 19:07:35 -06:00
Juha Niskanen
f383308a02 STM32L4 ADC: add ADC register definitions 2017-08-14 06:47:12 -06:00
Juha Niskanen
2fbd7d7b59 STM32L4 DAC: port from STM32. Note that this does not address the somewhat confusing relation between STM32L4_NDACS and DAC2 config macros that comes from original STM32 code. 2017-08-14 06:38:13 -06:00
Juha Niskanen
9ac80e45f5 STM32L4 COMP: input minus pin extended selection 2017-08-14 06:29:13 -06:00
Juha Niskanen
a9343ca12b stm32/stm32f0: Fix some funny shifts in DAC header files. 2017-08-14 06:28:09 -06:00
Gregory Nutt
e224d354b8 STM32F7: Remove unsupported configuration item the crept in when header file was cloned. 2017-08-13 12:37:59 -06:00
Gregory Nutt
f6f4856cc6 Eliminate some warnings found in build testing. 2017-08-13 12:24:48 -06:00
Sungki Kim
d9c1f37ed5 modify default uart pin for ESP-WROOM-32 2017-08-13 22:42:42 +09:00
Sungki Kim
dbe4978c6a fix gpio enable reg 2017-08-13 22:42:10 +09:00
Gregory Nutt
873de7b480 configs/*/README.txt: Update to the new URL for obtaining the ARM toolchain. 2017-08-13 07:18:19 -06:00
Gregory Nutt
2ab8852b29 STM32F7: Some STM32F7 builds failed in build testing due to undefined STM32_SRAM1_BASE. I think that is because stm32_allocateheap.c was not including chip/stm32_memorymap.h 2017-08-13 06:50:48 -06:00
Gregory Nutt
03c26df04a STM32F7 builds broken. This is a work around to at least keep them building. 2017-08-13 06:44:04 -06:00
Gregory Nutt
4fa6106b57 Fix some compile problems found in build testing. 2017-08-12 14:28:27 -06:00
Gregory Nutt
1f989af845 Update TODO list; SAMv7 XDMAC: Remove and unused global array. 2017-08-12 12:26:13 -06:00
Gregory Nutt
4b6f0149ec Eliminate a warning found in build testing. 2017-08-12 11:14:11 -06:00
Gregory Nutt
6bae133e74 Fix two warnings found in build testing. 2017-08-12 11:09:48 -06:00
Gregory Nutt
bd7c84b23e Remove CONFIG_NETDEV_MULTINIC. This increases code size by a little, but greatly reduces the complexity of the network code. 2017-08-08 14:24:12 -06:00
Stefan Kolb
22dfa875fc I discovered while working on the SAMV7 mcan driver that the implementation of the CAN error handling is suboptimal. In the current implementation the following errors are implemented as pending errors: 
* Receiving
  * MCAN_INT_STE (Stuff Error)
    More than 5 equal bits in a sequence occurred.
  * MCAN_INT_CRCE (CRC Error)
    Received CRC did not match the calculated CRC.
  * MCAN_INT_RF0L (Receive FIFO 0 Message Lost)
    Receive FIFO 0 message lost, also set after write attempt to Receive FIFO 0 of size zero.
  * MCAN_INT_RF1L (Receive FIFO 1 Message Lost)
    Receive FIFO 1 message lost, also set after write attempt to Receive FIFO 1 of size zero.

* Sending
  * MCAN_INT_BE (Bit Error)
    Device wanted to send a rec / dom level, but monitored bus level was dominant / recessive.
  * MCAN_INT_TEFL (Tx Event FIFO Element Lost)
    Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.

* General
  * MCAN_INT_MRAF (Message RAM Access Failure)
    The flag is set, when the Rx Handler
    * has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
    * was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Receive Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted Operation mode (see Section 47.5.1.5). To leave Restricted Operation mode, the processor has to reset MCAN_CCCR.ASM.
  * MCAN_INT_ELO (Error Logging Overflow)
    Overflow of CAN Error Logging Counter occurred.

The listed errors are not pending, the errors occurred and are gone directly afterwards. This commit changes the described behavior and simplifies the handling of CAN errors.
 2017-08-07 10:31:04 -06:00
Jeff
4cbde22992 I'm working on bringing up USB full-speed support on STM32F405.  My board does not include a USB power switch, VBus sensing, over current detection, or ID pin. 
This commit add a config STM32_OTGFS_VBUS_ CONTROL which lets us selectively disable VBus sensing and control.  I also sneaked in a change to disable the configgpio call for the ID pin, which is only used in OTG mode which isn't supported yet.  The only pins that need to be initialized should be OTGFS_DP and OTGFS_DM.

These changes let a USB mouse enumerate on my platform if it's plugged in on power-up.  Plugging, unplugging, clicking, or moving the mouse cause NSH to stop responding.  Because I'm using the ramlog, I don't have useful debug messaging yet, so there's a lot more work I have to do to troubleshoot it or get my JTAG debugging set up, but these patches shouldn't hurt anything.  I'm hoping my issue is something simple I overlooked in configuration.

I'm planning to add similar changes for the OTGHS peripheral (using integrated full speed phy) but I still need to test those changes before submitting patches.
 2017-08-07 10:24:31 -06:00
Simon Piriou
b1f50490bd MTD: Add driver for Macronix QuadSPI flash memory 2017-08-06 10:51:17 -06:00
Gregory Nutt
4cc13f8d94 Simulator: x86 stack needs to be aligned to 16-byte boundaries. 2017-08-04 07:03:39 -06:00
Gregory Nutt
42b3ee4cfc Fix a few errors that crept in with my review changes. 2017-08-02 09:19:29 -06:00
Gregory Nutt
5f2d4b8f84 Changes from review of commit e851a24329 2017-08-02 08:26:08 -06:00
Masayuki Ishikawa
e851a24329 arch/arm/src/lc823450: Initial support for ON Semiconductor LC823450 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2017-08-02 21:09:43 +09:00
Titus von Boxberg
55e9c8990c stm32_rcc: code style 2017-08-01 16:25:19 +02:00
Titus von Boxberg
a4e97d5daf Added functions for DSI clock source selection 2017-08-01 16:24:48 +02:00
Gregory Nutt
05ea22e9ab STM32F7: Fix for coding standard violations that came in with cd3ca1140e -- missed a file last time 2017-07-31 18:36:38 -06:00
Gregory Nutt
5f4fdb42be STM32F7: Fix for coding standard violations that came in with cd3ca1140e 2017-07-31 18:35:37 -06:00
Titus von Boxberg
604a6dc0fa improved help text 2017-08-01 01:23:28 +02:00
Titus von Boxberg
bdee01f492 added function for reset 2017-08-01 01:23:28 +02:00
Titus von Boxberg
0947b31fbb STM32_RCC_DCKCFGR2 has nothing to do with PLLI2S; PLLI2S is not dependent on LTDC, instead on SAICLK1/2 generated from PLLI2S 2017-08-01 01:23:28 +02:00
Titus von Boxberg
9d56dbb403 comment corrected 2017-08-01 01:23:28 +02:00
Titus von Boxberg
63bce1fc34 no board specific dithering values used; corrected comment; corrected dithering init 2017-08-01 01:23:28 +02:00
Titus von Boxberg
ec95720d13 corrected LIPOS/LIPCR calculation 2017-08-01 01:23:28 +02:00
Titus von Boxberg
28a53d8e25 change only polarity bits in LTDC_GCR 2017-08-01 01:23:28 +02:00
Titus von Boxberg
5de2468521 comments corrected 2017-08-01 01:23:28 +02:00
Titus von Boxberg
69aca28e87 commented 2017-08-01 01:23:28 +02:00
Titus von Boxberg
ec43001d91 HEAP2 depends on CONFIG_ARCH_HAVE_HEAP2, not on particular FMC RAM type 2017-08-01 01:23:28 +02:00
Titus von Boxberg
777b17928f corrected register debugging 2017-08-01 01:23:28 +02:00
Titus von Boxberg
1944ab6f9b added missing config option for register value debugging 2017-08-01 01:23:28 +02:00