Commit Graph

870 Commits

Author SHA1 Message Date
Xiang Xiao
94cb0c6072 arch: Move -nostdinc++ to Tooolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-29 21:08:14 -03:00
Ville Juven
b3baf95835 UMM: Implement getter for address environment heap start vaddr
Using the Kconfig macro does not work for RISC-V target, as there the
user heap follows .data/.bss and does not obey any Kconfig provided
boundary.

Added stubs for ARM and Z80 also.
2022-04-29 23:13:16 +08:00
Ville Juven
e674d5cb86 RISC-V: Add crt0 file
Contains the code for the user process signal trampoline.
2022-04-29 02:02:15 +08:00
Ville Juven
0ccda05a82 RISC-V: Move wipe_page to pgalloc.h and rename it riscv_pgwipe 2022-04-29 02:02:15 +08:00
Ville Juven
3d8ba496a2 RISC-V: Add pgpool to vaddr utility function
The only mapping that is supported now is vaddr=paddr, but the function
DOES check that the address is within the page pool, so it is not
useless.
2022-04-29 02:02:15 +08:00
Ville Juven
1322f82802 RISC-V: Copy kernel memory mappings to userspace addrenv
Copy the kernel mappings to the new (user) address environment. The
copyuing is done exactly once. This relies on the fact that the kernel
L1/L2 mappings will never change, as all of the kernel memory is mapped
upon boot.
2022-04-29 02:02:15 +08:00
Ville Juven
57127b9429 RISC-V: Initial support for CONFIG_BUILD_KERNEL
This implements initial support for kernel build (address environments,
page allocator) for RISC-V.

This is done a bit differently compared to the ARMV7 implementation:

- Support implemented for Sv39 MMU, however the implementation should be
  extensible for other MMU types also.
- Instead of preserving and moving the L1 references around, a canonical
  approach is used instead, where the page table base address register
  is switched upon context switch.
- To preserve a bit of memory, only a single L1/L2 table is supported,
  this gives access to 1GiB of virtual memory for each process, which
  should be more than enough.

Some things worth noting:
- Assumes page pool is mapped with vaddr=paddr mappings
- The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are
  ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used
  for ARCH_DATA_RESERVE
- ARCH_DATA_RESERVE is placed at the beginning of the userspace task's
  address environment
2022-04-29 02:02:15 +08:00
Gustavo Henrique Nihei
ffab2dc628 risc-v: Restrict Fence instruction for chips that support S-mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-04-28 01:18:46 +08:00
Gustavo Henrique Nihei
1967805b91 risc-v: Fix format specifier in debug log
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-04-28 01:18:46 +08:00
chao.an
cbef8681fe arch/risc-v: add support for GCC LTO
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-27 23:42:37 +08:00
Ville Juven
216574bba8 OpenSBI: Add riscv_hardfp.S to compilation
It will just become an empty object if FPU support is not included.
2022-04-27 23:20:51 +08:00
dytang
d7cc3f9275 RISC-V: workaround for the RV64 SoC which does not has mem mapped MTIMER currten value regs. 2022-04-27 22:48:54 +08:00
Abdelatif Guettouche
587145a881 riscv/Makefile: Delete old target used for debugging.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-27 12:58:57 +08:00
Xiang Xiao
fc16cfaefe Correct the code alignment found in review
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-26 11:34:28 +03:00
Ville Juven
6546789b7e RISC-V: Add syscall support for vfork
If vfork is called via syscall (PROTECTED/KERNEL build) need to set up
return parameters for syscall. Otherwise the SW will get lost.
2022-04-25 16:23:17 +03:00
Xiang Xiao
8f8ee25a9c boards: Move -g from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-25 16:23:03 +03:00
Ville Juven
a014daf44f RISC-V: Add implementation for vfork 2022-04-25 15:44:32 +08:00
Ville Juven
2580520828 RISC-V: Fix system crash when FPU is in use
FPU registers need to be written prior to updating CSR_STATUS
2022-04-25 15:44:06 +08:00
Xiang Xiao
75326e563d boards: Move -fno-common from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-25 07:57:29 +03:00
Xiang Xiao
5a565e753c pm: Move pm_initialize call from driver_initialize to xxx_pminitialize
since it's too late with the below commit:
ommit a594a5d7a8
Author: chao.an <anchao@xiaomi.com>
Date:   Mon Apr 11 19:44:26 2022 +0800

    sched/init: drivers_initialize() should be late than up_initialize()

    up_initialize
    |
     ->up_serialinit
       |
        ->uart_register  /* ("/dev/console", &CONSOLE_DEV); */

    drivers_initialize
    |
     ->syslog_console_init
       |
        ->register_driver /* ("/dev/console", &g_consoleops, 0666, NULL); */

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-22 14:36:27 +03:00
Masayuki Ishikawa
04f81ecddb arch: risc-v: Do not enable FPU for K210 with QEMU
Summary:
- I noticed that maix-bit:smp does not work with QEMU.
- Actually, QEMU supports sifive_u (not K210) but it works
  if FPU is disabled.
- This commit fixes this issue.

Impact:
- K210 with QEMU only

Testing:
- Tested with qemu-5.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-04-22 14:52:04 +08:00
Huang Qi
06c7a3ca59 arch/risc-v/riscv_misaligned: Implement float load/store support
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-22 12:23:10 +08:00
Huang Qi
be95e76910 arch/risc-v: Enable FPU for K210
K210 support rv64gc ISA, now we enable F/D extension for it.

Note: QEMU for K210 don't support FPU now.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-21 21:47:29 +03:00
chao.an
1c8e12406e compile/opt: add config DEBUG_LINK_MAP
Selecting this option will pass "-Map=$(TOPDIR)$(DELIM)nuttx.map" to ld
when linking NuttX ELF. That file can be useful for verifying
and debugging magic section games, and for seeing which
pieces of code get eliminated with DEBUG_OPT_UNUSED_SECTIONS.

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-22 01:37:23 +08:00
chao.an
64d7326ed5 compile/opt: add config DEBUG_OPT_UNUSED_SECTIONS
Enable this option to optimization the unused input sections with the
linker by compiling with " -ffunction-sections -fdata-sections ", and
linking with " --gc-sections ".

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-22 01:37:23 +08:00
Huang Qi
0332b78f99 arch/risc-v: Don't clear reserved bits in fcsr in riscv_fpuconfig
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-21 15:26:05 +08:00
Huang Qi
48b81bda09 arch/risc-v: Change riscv_savefpu/riscv_loadfpu to macro
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-20 16:08:17 +03:00
chao.an
e066d5d1e0 arch/risc-v: Unify the toolchain definition of RVG for linux and windows
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-19 23:17:27 +08:00
Ville Juven
5b6dd876b8 risc-v/riscv_assert.c Fix dumping of status from ISR
The status dump did not work if the first fault triggers before
the first context switch (during nx_start()).
2022-04-19 15:28:09 +03:00
Xiang Xiao
7a0fd8d10f arch/risc-v: Remove FAR from chip and board folder
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-19 00:22:45 +03:00
chao.an
29005bd79f board/arch_fpu*: move arch_[get|cmp]fpu to common arch
rename the arch api:
arch_getfpu  -> up_saveusercontext
arch_cmpfpu  -> up_cmpfpu

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-18 22:22:16 +08:00
chao.an
5bdfae66ce arch/arm: export arm_saveusercontext()
rename arm_saveusercontext() -> up_arm_saveusercontext()

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-18 22:22:16 +08:00
Xiang Xiao
ef1a98dd00 Remove the unneeded void cast
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-17 23:32:05 +03:00
Xiang Xiao
32ee2ae407 Remove the unneeded worker_t cast
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-17 23:32:05 +03:00
chao.an
c08d9047b2 arch/Toolchain.defs: replace all ${/$} with $(/$)
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-17 00:58:34 +08:00
Jan Charvat
6ec86361a8 arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller included into Kconfig.
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
2022-04-15 22:55:26 +08:00
Jan Charvat
e28584131d arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller driver.
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
2022-04-15 22:55:26 +08:00
Jan Charvat
0fa1541a80 arch/riscv/esp32c3: esp32c3_twai.h TWAI (CAN) controller registers provided by Espressif.
File provided by Abdelatif Guettouche

Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
2022-04-15 22:55:26 +08:00
Huang Qi
a94c865791 arch/risc-v: Use fs status definition from csr.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-15 19:41:31 +08:00
Ville Juven
47945e83b2 MPFS: Set correct interrupt per mode (M-/S-mode) for mtimer 2022-04-14 16:36:06 +03:00
chao.an
b3d47e246f arch/stack_color: correct the stack top of running task
This PR to ensure the stack pointer is locate to the stack top

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-14 16:48:19 +08:00
Ville Juven
c2b69cc2c9 RISC-V: mtimer register via SBI when S-mode is in use
Cannot access the memory mapped registers directly when the kernel
runs in S-mode, must forward the access to SBI.
2022-04-14 16:43:34 +08:00
Ville Juven
3d6ab5c804 RISC-V: Add SBI glue logic
Currently only stubs for mtime handling added, with a gentle reminder
that the actual implementation is still missing.
2022-04-14 16:43:34 +08:00
Abdelatif Guettouche
6d12ee19e2 arch: Move the DUMP_ON_EXIT logic after nxtask_exit.
Otherwise we will try to dump the state of the current task, however the
exit handler has already started doing some cleanup and invalidated its
group.  Accessing the group from dumponexit will crash.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-13 21:59:23 +08:00
Abdelatif Guettouche
d6c952c56f arch: Fix compile error when enabling CONFIG_DUMP_ON_EXIT
"error: incompatible types when assigning to type 'struct filelist *' from type 'struct filelist'
   filelist = tcb->group->tg_filelist;"

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-13 21:59:23 +08:00
Ville Juven
190e3aded3 MPFS: Use riscv_exception_attach like the others do
Exception / fault handling goes to unexpected ISR, fix by setting the
common ISR handlers like all other RISC-V platforms do.
2022-04-13 21:56:21 +08:00
Ville Juven
2b29dec5e0 MPFS: Fix mtimecmp address
MTIMECMP0 was incorrect
2022-04-13 21:56:21 +08:00
Huang Qi
f5cf35784e arch/risc-v: Correct format of 32-bit insn in misaligned handler
FIx:
Format specifies type 'unsigned long' but the argument has type 'uint32_t' (aka 'unsigned int')

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-13 18:33:36 +08:00
Huang Qi
898d789a5f arch/risc-v/riscv_misaligned: Correct sw source register
If source register of sw instruction is x0, we must point it to a constant zero
since in NuttX's context,
value of index 0 is EPC.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-13 18:33:36 +08:00
Ville Juven
370152f3ba RISC-V: Move mhartid to own assembly macro+function
Hartid and cpuindex are not the same thing. Hartid is needed regardless
of SMP, for external interrupt handling etc.

SMP needs cpuindex which might not be index == hartid, so both are
needed. IMO it is clearer to provide separate API for both.

Currently the implementation of up_cpu_index is done a bit lazily,
because it assumes hartid == cpu index, but this is not 100% accurate,
so it is still missing some logic.
2022-04-13 12:00:40 +02:00