Commit 8a63d29c removed `devif_iob_send` from `udp_sendto_buffered`
workflow, `devif_iob_send` drops too big packet. Now we still need a
place to check the packet length, otherwise a packet larger than MTU
may be sent to the net driver.
In case of similar problem happens somewhere else, this commit also
adds a check in `netdev_upperhalf`, and count these cases into
`NETDEV_TXERRORS`.
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
Busy waiting in w25qxxxjv_erase_sector() was without nxsig_usleep and
was causing the entire system to freeze for significant amount of time
as sector erase takes some time.
This commit adds nxsig_usleep into busy waiting to prevent system lock.
Sleep is set to sector erase time based on W25Q series datasheet.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
we can use uart to debug nuttx,like debugger:
1. read/write memory
2. Use watchpoint,breakpoint,single step.
use up_debugpoint api
3. Ctrl+c to stop, continue, or single step.
hold uart send and receive
4. register a panic event, when crash or assert/panic, we use uart to
debug.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Currently RISC-V NuttX supports 32-bit MMU Flags inside a Page Table Entry. This PR extends the MMU Flags to 64-bit, to support T-Head C906 Core and the new RISC-V Svpbmt Extension.
T-Head C906 uses Bits 59 to 63 in a Leaf Page Table Entry to configure the Memory Type: Cacheable / Bufferable / Strongly-Ordered. For the upcoming port of NuttX to PINE64 Ox64 BL808 SBC, we need to set the Memory Type to Strongly-Ordered for I/O Memory, which requires 64-bit MMU Flags.
Details of C906 MMU: https://lupyuen.github.io/articles/plic3#t-head-errata
Newer RISC-V Cores will use the Svpbmt Extension to configure the Memory Type (Cacheable / Strongly-Ordered). Svpbmt uses Bits 61 to 62 in a Leaf Page Table Entry to define the Memory Type. This also requires 64-bit MMU Flags.
Details of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/main/src/supervisor.adoc#svpbmt
Usage:
1. CONFIG_FS_PROCFS_MAX_STACK_RECORD > 0, such as 32,
2. add '-finstrument-functions' to CFLAGS for What you want to check
stack.
3. mount porcfs
4. cat /proc/<pid>/stack will print backtace & size
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.
We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.
Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.
use instrument_register to register entry function and exit function.
They will be called by the instrumented function
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Virtio driver can used this api to judge whether the this feature
is supported by both virtio driver and device.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Binary nibble to/from ascii hex conversion was buggy on both
lib_slcdencode and lib_slcddecode libraries.
This bug caused the slcd library to fail to decode 5-byte sequence command
which have 'count' argument value bigger than 0x9.
Signed-off-by: Federico Braghiroli <federico.braghiroli@gmail.com>
Revert "ci/docker: Fix " Could not find GN_EXECUTABLEXX using the following names: gn""
This reverts commit d6ac9e1aed.
Revert "tools/ci: Skip copy gn temporary files"
This reverts commit 4673fccece.
If the gap between sp and stack_top is too small,
then the stack will not be output,
modify the conditional loop condition, and fix this problem
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Previously CONFIG_USBDEV_SOFINTERRUPT existed in many platform
drivers but did nothing. This commit adds a callback function
usbdev_sof_irq() that can be used to take action on this interrupt.
The ADC peripheral can only support up to
50MHz on rev V silicon and 36MHz on Y silicon.
The existing driver always used no prescaler
and kept boost setting at 0.
The 1170 usage of the GPR registers is to select the
between GPIO{2|3} or CM7_GPIO{2|3} where as the 1060
it selected ports between 1-6,2-7..4-9 and uses
different GPR registers.
For the 1170 we are defaulting to GPIO{2|3} and not
supporting the swtich to CM7_GPIO{2|3}.
