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16197 Commits

Author SHA1 Message Date
Bhindhiya
9707f39ff7 RX65N DTC Driver Support Added 2020-09-26 11:45:15 -03:00
David Sidrane
4a6f7cacd5 stm32f7:serial Bug Fix: Ensure next buffer is processed 
When the Head to Tail relationship was H < T, then
   only the tail to end of buffer was sent.

   The fix is: In the txdma completion to do a second
   the DMA operation using nbuffer if the nlength is
   non zero.

stm32f7:serial UART5 use actual size

   UART5 was using the CONFIG_UART5_TXBUFSIZE
   not the UART5_TXBUFSIZE_ADJUSTED.
   Since the buffer size was adjusted up, this
   has no dcache implications.
   If the UART5_TXBUFSIZE_ADJUSTED is larger
   then CONFIG_UART5_TXBUFSIZE it will present
   a larger usable buffer to the system's
   serial driver.
 2020-09-25 22:09:05 +01:00
Sebastian Ene
c47ad0c909 arch/sim: Add host timer to oneshot timer logic 
## Summary of Changes

Add a host timer that generates periodic signals and sends SIGALRM to
the process that runs the NuttX simulation. This logic is integrated as
part of the existing NuttX oneshot timer. The host timer installs an
irq handler which is expected to run every CONFIG_USEC_PER_TICK .

Signed-off-by: Sebastian Ene <nuttx@fitbit.com>
 2020-09-25 17:36:16 -03:00
Nathan Hartman
090d822f33 tiva: Fix nxstyle warnings 
arch/arm/src/tiva/tiva_gpio.h:

    * Fix nxstyle warnings. No functional changes.

arch/arm/src/tiva/tiva_mpuinit.h:

    * Fix nxstyle warnings. No functional changes.

arch/arm/src/tiva/tiva_qencoder.h:

    * Fix nxstyle warnings. No functional changes.
 2020-09-25 16:37:45 +01:00
anjana
c6b51771f0 USB Device Mode Driver Support for RX65N 2020-09-25 09:06:59 -03:00
Nathan Hartman
44d7f14121 tiva: tiva_ssi.h: Fix nxstyle warnings 
arch/arm/src/tiva/tiva_ssi.h:

    * Fix nxstyle warnings. No functional changes.
 2020-09-24 16:00:55 -03:00
Matias N
0f9fb67b0c nrf52 spi: build fixes for !SPI_EXCHANGE 2020-09-24 09:51:51 -03:00
Bhindhiya
d0e0af7826 Renesas .gitignore files added 2020-09-24 10:10:40 +01:00
Nathan Hartman
c8bb4474bb tiva: tiva_periphrdy.h, tiva_pwm.h: Fix nxstyle warnings 
arch/arm/src/tiva/tiva_periphrdy.h:

    * Fix nxstyle warnings. No functional changes.

arch/arm/src/tiva/tiva_pwm.h:

    * Fix nxstyle warnings. No functional changes.
 2020-09-23 22:00:17 +01:00
Thomas Axelsson
f193f0f702 imxrt: Style fixes in mux and ADC hardware headers 2020-09-23 13:16:33 -03:00
Thomas Axelsson
d67bc0c3c8 imxrt: ADC driver 
Based on LPC17xx_40xx and STM32 drivers.
 2020-09-23 13:16:33 -03:00
Daniel Mesham
c8dc9e39ac arch/arm: stm32l4: Fix typo in TIM15 PWM config 
When configuring TIM15_CH2 as output, we mistakenly referred to TIM12 instead.
 2020-09-23 14:29:10 +02:00
zhongan
6240977341 rv32im: add missing call of 'up_savefpu'. 
Change-Id: Iaf2e212a4fdea2f5f04a178d24755e0e37a30ef6
Signed-off-by: zhongan <zhongan@xiaomi.com>
 2020-09-23 10:22:45 +01:00
zhongan
07dd053e86 risc-v: add putreg64 for mtimer registers. 
Change-Id: I18fe312c95c73966f5c09fd18081b0c72923e2ac
Signed-off-by: zhongan <zhongan@xiaomi.com>
 2020-09-23 10:22:45 +01:00
Daniel Agar
3df8f79111 stm32f412ce fixes 2020-09-22 22:44:43 -07:00
saramonteiro
7d889bf4c4 nrf52: Fix typo, replace setcc with getcc 2020-09-22 21:07:31 -03:00
Xiang Xiao
031984f76a arch/arm: Select arm family when ARCH_ARM1136J/ARCH_ARM1156T2/ARCH_ARM1176JZ is defined 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-09-22 23:05:29 +01:00
Xiang Xiao
d078518502 arch/arm: Should include arch/armv8-m/spinlock.h when CONFIG_ARCH_ARMV8M is defined 
forget in commit 2376d8a266
Author: qiaowei <qiaowei@xiaomi.com>
Date:   Wed Apr 22 10:09:50 2020 +0800

    Porting arch/armv8-m support

    1. Add dsp extension; float point based on hardware and software.
    2. Delete folder "iar"
    3. Add tool chain for cortex-M23 and cortex-M35p

    Signed-off-by: qiaowei <qiaowei@xiaomi.com>
    Change-Id: I5bfc78abb025adb0ad4fae37e2b444915f477fe7

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-09-22 23:05:29 +01:00
Xiang Xiao
7faf72cabc arch/arm: Add ARCH_ARMV6M Kconfig to prepare the support of CortexM0+ 
also align with the armv7m implementation

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-09-22 23:05:29 +01:00
Nathan Hartman
560a052144 tiva: tiva_timer.h: Fix nxstyle warnings 
arch/arm/src/tiva/tiva_timer.h:

    * Fix nxstyle warnings. No functional changes.
 2020-09-22 10:29:28 -07:00
Bhindhiya
c5ef686707 Warnings in NuttX Renesas common files Resolved 2020-09-22 09:49:46 -07:00
Abdelatif Guettouche
a128995eab arch/xtensa: Few typos and style fixes. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-09-21 19:14:19 -04:00
Nathan Hartman
bc9d3cdd14 tiva: tiva_flash.h: Fix nxstyle warnings 
arch/arm/src/tiva/tiva_flash.h:

    * Fix nxstyle warnings. No functional changes.
 2020-09-21 22:04:45 +01:00
Xiang Xiao
68a2727c12 arch/sim: Extend the heap size to 64MB 
to support the more complex application and
remove the special definition for CONFIG_MM_SMALL

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-09-21 07:40:17 -07:00
zhongan
657d1c9fdc Add and fix CSR macros listed in RISC-V spec V1.10. 
Add csr operatiing macros.

Change-Id: Ia5c148d10709c21424c5ecaaca01b7d200fb8e01
Signed-off-by: zhongan <zhongan@xiaomi.com>
 2020-09-21 07:35:56 -07:00
chenwen
64e2f102ac xtensa/esp32: Add power management of force-sleep 2020-09-20 17:23:07 +01:00
Bhindhiya
7910b58415 RX65N Defconfig Modification 2020-09-18 23:58:37 +01:00
Nathan Hartman
4ceb8ef4e1 tiva: tiva_sysctrl.h: Fix nxstyle warnings 
arch/arm/src/tiva/tiva_sysctrl.h:

    * Fix nxstyle warnings. No functional changes.
 2020-09-18 23:50:59 +01:00
Brennan Ashton
1473c6848f nRF52: Add hooks for missing SPI register callbacks 
This implements the missing callback hooks nrf52_spi0/1/2/3register
that are usually used with mmcsd for card detection.

This also stubs out the missing spi trigger function which is not
used on this platform.

The card detect was tested with the nRF52-feather board and a
modified KeyBoard FeatherWing.

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-09-18 04:31:47 -07:00
ligd
a9830254cf SIM in MacOS: make MacOS link process same with Linux 
1. There is difference about symbol replace on nuttx-names.in
   between MacOS & Linux
2. For MacOS, if open '-fvisibility=hidden' and adjust nuttx-names.in,
   it will meet symbol link-back-to-nuttx error.
3. Make the MacOS replace behaviour, same with Linux

Note:
MacOS should install objcopy with command:
$ brew install binutils
$ export PATH=$PATH:/usr/local/opt/binutils/bin

already check in to cibuild.sh

Change-Id: If78b784cc0ecb98cdbf7091de38acef00a8a02f3
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2020-09-18 18:58:32 +09:00
Fotis Panagiotopoulos
b0b5f87699 Removed broken overdrive function in STM32. 2020-09-18 02:53:40 -07:00
Nathan Hartman
a4d1a20b93 tiva: tiva_lowputc.h: Fix nxstyle warnings 
arch/arm/src/tiva/tiva_lowputc.h:

    * Fix nxstyle warnings. No functional changes.
 2020-09-17 11:07:35 -07:00
Nathan Hartman
e916896aa9 tiva: tiva_eeprom.h: Fix nxstyle warnings 
arch/arm/src/tiva/tiva_eeprom.h:

    * Fix nxstyle warnings. No functional changes.
 2020-09-16 22:15:34 -03:00
Nathan Hartman
de7953c0ee tiva: tiva_userspace.h: Fix nxstyle warnings 
arch/arm/src/tiva/tiva_userspace.h:

    * Fix nxstyle warnings. No functional changes.
 2020-09-16 09:45:17 -07:00
Xiang Xiao
1475309c5b Fix nxstyle warning 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-09-16 06:57:29 -07:00
Xiang Xiao
bf7399a982 arch: Initialize idle thread stack information 
and remove the special handling in the stack dump

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia1ef9a427bd4c7f6cee9838d0445f29cfaca3998
 2020-09-16 06:57:29 -07:00
Brennan Ashton
8602e46d4a nRF: Add missing Kconfig entry for SPI2_MASTER 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-09-16 07:26:29 +02:00
Matias N
166242c171 use "export" to expose TOPDIR to all child make instead of passing it around every time 2020-09-15 21:11:33 -07:00
Nathan Hartman
0eae2a1f59 tiva: tiva_ssi.c: Fix nxstyle warnings 
arch/arm/src/tiva/common/tiva_ssi.c:

    * Fix nxstyle warnings. No functional changes.
 2020-09-15 12:48:20 -03:00
Bhindhiya
7c67cffb69 RX65N Pre-check Warnings Resolved 2020-09-15 20:41:02 +08:00
Abdelatif Guettouche
d47131d8ae arch/xtensa/src/esp32/hardware/esp32_spi.h: Remove a leftover license. 2020-09-15 14:40:17 +08:00
Abdelatif Guettouche
55f7473ba0 arch/xtensa/src/esp32/esp32_spiflash.c: #if0-out unused functions. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-09-15 14:40:17 +08:00
Abdelatif Guettouche
a97a9aeaf6 arch/xtensa/src/esp32/esp32_spiflash.c: File scope global variables are 
prefixed with g_

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-09-15 14:40:17 +08:00
Nakamura, Yuuichi
7ce5369873 Fix cxd56 uart deadlock 2020-09-15 15:12:02 +09:00
Bhindhiya
0e22eceef2 RX65N Ethernet pre-check warnings resolved 2020-09-15 09:51:04 +08:00
Matias N
3e48832cf6 z80: missing removal of KDEFINE/EXTRAFLAGS at arch level 2020-09-15 09:49:55 +08:00
Brennan Ashton
c9e618b7b6 nRF: Incorrect base addresses for SPI controllers 1,2,3 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-09-14 19:11:21 -03:00
Nathan Hartman
e681396d35 tiva: tiva_lowputc.c, tiva_qencoder.c: Fix nxstyle warnings 
arch/arm/src/tiva/common/tiva_lowputc.c:

    * Fix nxstyle warnings. No functional changes.

arch/arm/src/tiva/common/tiva_qencoder.c:

    * Fix nxstyle warnings. No functional changes.
 2020-09-14 12:16:28 -03:00
dongjiuzhu
3634bb6ba5 sim/uart: support tty operation in arch/sim 
Change-Id: I6943c1e928ed821aa913bc619e5b8c581b5610c3
Signed-off-by: dongjiuzhu <dongjiuzhu1@xiaomi.com>
 2020-09-14 09:23:46 -03:00
Brennan Ashton
93eeecff6a nrf52: SPI transfer failure and corruption 
The current EasyDMA implementation will fail if a transfer of over
255 bytes is requested with no warning.

Also we do not set the RX and TX transfer lengths to 0 if the
buffer is NULL which can cause data to be written to the old
address as well as cause unexpected transaction lenghts.
Example:
  transfer 1:
   rx_len  = 10
   rx_buff != NULL
   tx_len  = 10
   tx_buff != NULL
  transfer 2:
   rx_len = 2
   rx_buff != NULL
   tx_buff == NULL
  Total transaction length for the second would be 10 because it
  would still be using the old rx length of 10 and would
  corrupt data in the old rx buffer.

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-09-14 07:21:24 +02:00