Commit Graph

36 Commits

Author SHA1 Message Date
zhongan
657d1c9fdc Add and fix CSR macros listed in RISC-V spec V1.10.
Add csr operatiing macros.

Change-Id: Ia5c148d10709c21424c5ecaaca01b7d200fb8e01
Signed-off-by: zhongan <zhongan@xiaomi.com>
2020-09-21 07:35:56 -07:00
ligd
36a0978952 arch/risc-v/src/rv32im: update & complete risc-v rv32im arch
1. add schedulesigaction.c
2. add SYS_save_context handling
3. Skip ECALL instruction when up_swint()

Change-Id: Id52c6dd9ee1052441957b73463c00d3fd26555c5
Signed-off-by: ligd <liguiding@fishsemi.com>
2020-06-30 09:31:21 -03:00
Xiang Xiao
4fbbd2e3bf arch: Move PRIxMAX and SCNxMAX definition to include/stdint.h
like other related macro(e.g. INTMAX_MIN, INTMAX_MAX...)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I8863599960b1a9b1c22ae9c35735a379a4c745b0
2020-06-10 08:24:47 +02:00
Xiang Xiao
7758eb8658 arch: Define INTx_C and UINTx_C macro
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia50ea8764880fabd3d878c95328632c761be6b43
2020-06-10 08:24:47 +02:00
Gregory Nutt
c2244a2382 Remove CONFIG_TLS
A first step in implementing the user-space error is force TLS to be enabled at all times.  It is no longer optional
2020-05-07 12:04:16 -06:00
Ouss4
6eb6d31c32 Fix nxstyle complaints 2020-05-06 21:56:40 -06:00
Ouss4
a4dd967440 arch/: Implement up_tls_info() for the rest of the architectures. 2020-05-06 21:56:40 -06:00
Xiang Xiao
11705ffc71 Fix nxstyle issue 2020-04-14 13:02:00 -06:00
zhongan
0d3691a460 Add fpu support. 2020-04-14 13:01:47 -06:00
Nathan Hartman
679b4fbee2 arch: Fix included directed -> included directly
This typo had been copied and pasted into numerous irq and syscall
headers.
2020-04-05 22:31:15 +01:00
aenrbes
d450f5ce77
Add support for Litex VexRiscV. 2020-03-21 06:01:56 +00:00
Xiang Xiao
cde88cabcc Run codespell -w with the latest dictonary again
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-02-23 22:27:46 +01:00
Xiang Xiao
e7d9260014 arch: Customize the typedef of size_t instead of intptr_t
To ensure size_t same as toolchain definition in the first place and rename CXX_NEWLONG to ARCH_SIZET_LONG.  The change also check whether __SIZE_TYPE__ exist before CONFIG_ARCH_SIZET_LONG so our definition can align with toolchain(gcc/clang) definition automatically.
2020-02-18 07:15:19 -06:00
Masayuki Ishikawa
1a4ff4c4cd arch: risc-v: Add support for PROTECTED build to rv64gc 2020-02-14 09:29:51 -06:00
Xiang Xiao
76bbed07a4 Call up_irqinitialize from irq subsystem
Call up_irqinitialize from irq subsystem to make the irq ready for use as soon as possible
2020-02-08 07:39:22 -06:00
Masayuki Ishikawa
81f1133174 ELF64 support (#220)
* include: Introduce elf64.h and elf.h

    Added elf64.h for 64bit ELF support and moved common definitions
    from elf32.h to elf.h. Also introduced Elf_xxx to be used in
    common libraries such as binfmt.

  * binfmt, include, modlib, module: Add support for ELF64

    Elf_xxx must be used instead of Elf32_xxx to support ELF64.
    To use ELF64, CONFIG_ELF_64BIT must be enabled.

  * binfmt, modlib: Add support for relocate address

  * arch: risc-v: Add include/elf.h

  * libs: machine: Add risc-v related files.

    NOTE: Currently only supports ELF64

  * boards: maix-bit: Add elf and posix_spawn configurations

  * boards: maix-bit: Add support for module configuration
2020-02-07 17:10:23 -06:00
Xiang Xiao
80277d1630
Refine the preprocessor conditional guard style (#190) 2020-01-31 19:07:39 +01:00
Xiang Xiao
68951e8d72 Remove exra whitespace from files (#189)
* Remove multiple newlines at the end of files
* Remove the whitespace from the end of lines
2020-01-31 09:24:49 -06:00
Juha Niskanen
a762c06ed9 Fix typos and some incorrect comments
Author: Alan Carvalho de Assis <acassis@gmail.com>

    Run nxstyle against .c and .h files and fix it

Author: Juha Niskanen <juha.niskanen@haltian.com>

    Fix typos and some incorrect comments
2020-01-20 09:32:36 -03:00
Masayuki Ishikawa
29d3ed2ec1 Feature k210 smp (#71)
* arch: risc-v: Remove unused typedef for irqstate_t

    NOTE: irqstate_t is defined in arch/risc-v/include/types.h

  * arch: risc-v: Add typedef irqstate_t for __LP64__
  * arch: risc-v: Add SMP support to K210 (RV64GC) processor
  * boards: maxi-bit: Update READMEs and add smp/defconfig
2020-01-10 08:04:41 -06:00
Masayuki Ishikawa
255f3008cf arch: k210: Applied changes doned for fe310 recently.
NOTE: In the future, these code should be moved under common code
once they support both RV32 & RV64 architectures.
2020-01-09 09:33:10 -03:00
Masayuki Ishikawa
d76ba14d58 arch: fe310: Fix mstatus handling
In previous commit, mstatus.mie was set when creating a new task
    but this change was incorrect and had a side effect such that
    a machine interrupt would be enabled just before returning from
    interrupt handling routine to switch context.

    Also, mstatus.mpp is set to machine mode in up_get_newintctx()
    instead of fe310_dispatch_irq().
2020-01-08 10:39:00 -03:00
Masayuki Ishikawa
4ea49c5691 Fix issues on fe310 including interrupt handling (#46)
* arch: fe310: Fix comments

* arch: fe310: Improve irq handling in fe310_serial.c

* arch: fe310: Fix initial interrupt status (mstatus)

Also, removed unnecessary up_enable_irq(FE310_IRQ_ECALLM)
2020-01-07 07:17:39 -03:00
Xiang Xiao
6a3c2aded6 Fix wait loop and void cast (#24)
* Simplify EINTR/ECANCEL error handling

1. Add semaphore uninterruptible wait function
2 .Replace semaphore wait loop with a single uninterruptible wait
3. Replace all sem_xxx to nxsem_xxx

* Unify the void cast usage

1. Remove void cast for function because many place ignore the returned value witout cast
2. Replace void cast for variable with UNUSED macro
2020-01-02 10:54:43 -06:00
Masayuki Ishikawa
e33fc3dc89 Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>

    Run all .c and .h modified in PR through nxstyle.

Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>

    feature k210 (#16)

    * arch: risc-v: Add support for __LP64__ to types.h
    * arch: risc-v: Add support for RV64GC to common files
    * arch: risc-v: Add support for Kendryte K210 processor (RV64GC)
    * boards: risk-v: Add support for Sipeed Maix Bit with K210
    * tools: Add support for Kendryte K210 processor
2019-12-31 09:06:20 -06:00
Masayuki Ishikawa
466ab56c10 Merged in masayuki2009/nuttx.nuttx/fe310_gpio (pull request #1097)
fe310 gpio

* arch: risc-v: Add arch/risc-v/src/common/up_mdelay.c

* arch: risc-v: Add arch/risc-v/src/common/up_udelay.c

* arch: fe310: Add #include <stdint.h> to fe310_start.c

* arch: risc-v: Add up_ack_irq() definition to commpn/up_internal.h

* arch: fe310: Add FE310 GPIO driver

* boards: hifive-revb: Add compiler optimization

* boards: hifive1-revb: Add auto leds related files.

* arch: fe310: Add CPU activity led to fe310_idle.c

* boards: hifive-revb: Add a button

    NOTE: still having a trouble in signal handling.

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-12-19 04:59:30 +00:00
Masayuki Ishikawa
2cde7dcc8d Merged in masayuki2009/nuttx.nuttx/sparkfun_redv (pull request #1091)
Sparkfun RED-V Things Plus

* board: hifive1-revb: Update README-qemu.txt

* arch: fe310: Works with SparkFun RED-V Things Plus

    Should work with HiFive1 Rev.B but not tested yet.

* boards: hifive1-revb: Works with SparkFun RED-V Things Plus

    Should work with HiFive1 Rev.B but not tested yet.

Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-12-08 12:42:48 +00:00
Masayuki Ishikawa
7a8e9581ca Merged in masayuki2009/nuttx.nuttx/hifive1-qemu (pull request #1078)
HiFive1 with qemu

* arch: risc-v: Add include/.gitignore

* arch: risc-v: Add src/.gitignore

* arch: risc-v: Remove uncommon function prototypes in include/irq.h

* arch: risc-v: Add missing symbols and function prototypes in src/common/up_internal.h

* arch: risc-v: Add src/common/up_modifyreg32.c

* arch: risc-v: Enable include Make.dep in src/Makefile

* arch: risc-v: Fix stack coloration in common/up_createstack.c

* arch: risc-v: Add common/up_puts.c

* arch: risc-v: Add common/up_checkstack.c

* arch: rv32im: Move all logics from up_dumpstate.c to up_assert.c

    This change is same as other architectures like arm/src/armv7-m

* arch: Select ARCH_HAVE_STACKCHECK for RISC-V in Kconfig

* arch: risc-v: Add SiFive fe310 processor

    NOTE: Currently only tested with qemu

* boards: hifive1-revb: Add SiFive hifive1-revb board

    NOTE: Currently only tested with qemu

* tools: Add fe310 processor to configure.sh

Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-11-28 20:37:24 +00:00
Gregory Nutt
abf6965c24 Squashed commit of the following:
libs/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    syscall/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    wireless/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    Documentation/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    include/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    drivers/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    sched/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    configs:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    arch/xtensa:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    arch/z80:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    arch/x86:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    arch/renesas and arch/risc-v:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    arch/or1k:  Remove all references to CONFIG_DISABLE_SIGNALS.  Signals are always enabled.
    arch/misoc:  Remove all references to CONFIG_DISABLE_SIGNALS.  Signals are always enabled.
    arch/mips:  Remove all references to CONFIG_DISABLE_SIGNALS.  Signals are always enabled.
    arch/avr:  Remove all references to CONFIG_DISABLE_SIGNALS.  Signals are always enabled.
    arch/arm:  Remove all references to CONFIG_DISABLE_SIGNALS.  Signals are always enabled.
2019-04-29 14:52:05 -06:00
Gregory Nutt
b1001b4e50 Update TODO list regarding non-queuing of signal actions; Add comments in code at areas where the issue applies. 2019-02-04 08:35:03 -06:00
Gregory Nutt
e4562fc538 This commit brings in support for the GAP8 architecture. The GAP8 is a 1+8-core DSP-like RISC-V MCU. Also included is support for the Gapuino GAP8 evaluation board.
Squashed commit of the following:

Author: Gregory Nutt <gnutt@nuttx.org>

    Completes review of configs/gapuino.
    arch/risc-v/include/gap8/chip.h:  Replace the moved chip.h header file with a dummy chip.h header file just to keep the system happy.
    Move include/gap8/chip.h to src/gap8/chip.h.  Internal details should not be exposed outside of arch/ and configs/.  Review all headers files in src/gap8
    Review of arch/risc-v/include.

Author: hhuysqt <hyq9606@126.com>

    corrected author and email
    Add app initialization, add signal support, cleanup irq context and configs
    fix some warnings
    gapuino initial port
    GAP8 initial port
2018-10-30 09:38:50 -06:00
Gregory Nutt
9222f50e1c arch/: Make sure the up_irq_enable() is available on all architectures. I will not be able to test all of these new versions of this function so this may break things for awhile. 2018-06-06 09:25:40 -06:00
Gregory Nutt
f88a4c6ea8 arch/risc-v/src: Make code follow pattern of other architectures better. Fix some coding standard issues. 2018-06-06 07:46:50 -06:00
Gregory Nutt
1c5ec07414 arch/: Remove dangling space at the end of lines. 2017-06-28 13:16:48 -06:00
Paul A. Patience
912fe06a86 Add architecture-specific inttypes.h 2016-10-27 16:01:38 -04:00
Ken Pettit
201a32cf8c Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it. 2016-10-16 09:47:07 -06:00