Commit Graph

22042 Commits

Author SHA1 Message Date
Jukka Laitinen
155c776ba8 arch/arm64/src/imx9/imx9_usbdev.c: Fix the descriptor alignments and cache management
Align all the dtd and dqh on cache line boundaries and clean up the cache management

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-20 18:43:41 +08:00
chao an
d59f9186ca arch/risc-v: add llvm experimental extensions into command line
LLVM supports (to various degrees) a number of experimental extensions.
All experimental extensions have experimental- as a prefix. There is
explicitly no compatibility promised between versions of the toolchain,
and regular users are strongly advised not to make use of experimental
extensions before they reach ratification.

Fix compile error:
riscv64-unknown-elf-clang: error: invalid arch name 'rv64gcv_zfh_zvfh', requires '-menable-experimental-extensions' for experimental extension 'zvfh'

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-19 20:13:54 +08:00
chao an
e863e3dd37 arch/risc-v: add LLVM clang support
Verified on LLVM-Metal:
$ riscv64-unknown-elf-clang --version
(LLVM-Metal 15.9.0-2023.03.0) clang version 15.9.0
Target: riscv64-unknown-unknown-elf
Thread model: posix

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-19 12:27:56 +08:00
Huang Qi
93d75129de riscv: Add Vector CSRs to csr.h
The CSR register definitions from RVV 1.0 spec: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-registers

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-04-19 00:31:07 +08:00
Ville Juven
d73aab9f71 arm64/imx9: Add LPSPI driver
Add driver for LPSPI

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-18 10:58:02 -03:00
Yanfeng Liu
8d4eae41c1 arch/kconfig: revising kernel mapping configs
- Add ARCH_KVMA_MAPPING to guard kernel mapping.
- Set dependency from MM_KMAP to ARCH_KVMA_MAPPING, as per commit
  70de321de3.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-04-18 17:10:04 +08:00
Ville Juven
169dd50a08 imx9_gpioirq: Fix testing of ICR field from pinset
icr is tested below with macros like GPIO_INT_LOWLEVEL et al. Those macros
are shifted left by GPIO_INTCFG_SHIFT, so the temporary icr variable
should not be shifted right.
2024-04-18 00:40:07 +08:00
Ville Juven
09a6c400f6 imx9_boot.c: Add initialization of pin interrupts
Initialize the pin interrupt support during boot
2024-04-18 00:40:07 +08:00
wangchen
11962c3004 simwifi:change script path from absolute path to soft link
Signed-off-by: wangchen <wangchen41@xiaomi.com>
2024-04-17 19:46:42 +08:00
Pressl, Štěpán
1a2e752ea7 arch/arm/src/samv7/sam_qencoder.c: add support for GETINDEX ioctl call
The SAMV7's qencoder driver now supports the GETINDEX ioctl call
which does not reset the internal Timer/Counter and returns
the current position, position of the last index and the number
of captured indexes to a struct qe_index_s pointer. Because the
SAMV7's timers are 16bit, the extension to 32 bits must be done.

Select CONFIG_SAMV7_QENCODER_ENABLE_GETINDEX in the Kconfig to
enable this functionality.

This driver does not obey the instructions given in the ATSAMV7
2023 datasheet because the recommended trigger resets the internal
counter which is not desired. Instead, a capture into capture A
and capture B registers is used. This way if an event happens
(the rising edge of the index signal), the current counter's value
is captured.

Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
2024-04-17 19:44:34 +08:00
Almir Okato
d098c1dc87 esp32s3: add simple boot support
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s3 targets and removes the need
for running 'make bootloader' command for it.

Other related fix, but not directly to Simple Boot:
- Instrumentation is required to run from IRAM to support it during
initialization. `is_eco0` function also needs to run from IRAM.
- `rtc.data` section placement was fixed.
- Provide arch-defined interfaces for efuses, in order to decouple
board config level from arch-defined values.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-04-17 19:43:05 +08:00
Jukka Laitinen
58f0ee6364 arch/arm64/src/imx9: Add a more capable uart driver
Add an uart driver supporting LPUART1-8, dma, flow control, tc etc.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-17 00:10:10 +08:00
Almir Okato
f4bbe276e1 esp32[c3|c6|h2]: Fix simple boot map_rom_segments
Currently Simple Boot image have fixed 2 ROM segments and
2 RAM segments, then the parsing iterator must stop when all
ROM segments are found.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-04-17 00:09:58 +08:00
Ville Juven
4a82838be7 imx9_iomux.h: Fix issues with the header file
- Add missing include guard
- Add missing C++ guard
- Fix the initialization ordering in IOMUX_PADCFG macro. Why ? Becaused of:

imx9_iomuxc.h:54:3: error: designator order for field 'iomux_padcfg_s::dsyreg' does not match declaration order in 'iomux_padcfg_s'
   54 |   }
      |
2024-04-16 10:56:33 -03:00
Ville Juven
f8c5b91522 arm64/imx9: Add LPI2C driver 2024-04-16 19:14:43 +08:00
Ville Juven
8e32a3ce24 imx93_gpioirq: Fix the GPIO interrupt source names
The original assumption was that the interrupt numbers are divided
so that 16 pins from 1 port are handled by a single interrupt source.

So source 0 would handle pins 0-15 and source 1 would handle pins 16-31.
This assumption is wrong, each pin has two sources, thus there are two
interrupt lines for each pin.

The driver uses source 0, and leaves source 1 disabled.
2024-04-16 19:11:31 +08:00
simbit18
b0504f1e5e fix nxstyle
fix Relative file path does not match actual file.
2024-04-15 15:33:17 -03:00
Ville Juven
2e638f6f19 arch/arm64: Add atomic modifyregXX
These are needed by drivers
2024-04-15 11:53:13 -03:00
Jorge Guzman
5e3cbd1165 stm32h7/linum-stm32h753bi: Add support to littlefs and nxffs with flash mem. via quadspi
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
2024-04-15 13:24:55 +08:00
hujun5
f41f0324a5 qemu/trustzone: add secure memory config
According to the qemu source code, hw/arm/virt.c.
The secure memory of the ARM Virt board is [0xe000000~0xf000000]
and the non-secure memory is configured as [0x40000000~0xffffffff].
We made the following adjustments based on the above virt board configuration

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-04-14 12:07:59 -03:00
Yanfeng Liu
200424e59d arch/risc-v: fix RV32 up_addrenv_destroy
This patch fixes the issue/12122 for RV32, where the scanning should be
limited to user space only.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-04-14 14:49:36 +08:00
Yanfeng Liu
6d7355b929 arch/kconfig: minor revision for KMAP_NPAGES
Adds missing dependency to MM_KMAP, revises comments.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-04-14 14:48:23 +08:00
TimJTi
df7650af71 Improvements relating to SAMA5 TSD driver 2024-04-14 14:47:53 +08:00
Jakub Janousek
3ce84d1ba0 arch and board esp32c3-legacy: Add optional iCE40 FPGA loading support
Signed-off-by: Jakub Janousek <janouja9@fel.cvut.cz>
2024-04-12 10:19:58 -03:00
Inochi Amaoto
412d2ce113 arch/riscv: add T-HEAD CSR mapping
Add T-HEAD CSR mapping file.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-11 22:20:39 +08:00
Inochi Amaoto
bae686e127 arch/riscv: force using encoding macro for CSR access
Using CSR name depends on compiler support heavily, but CSR
encoding does not have this problem. It also make it easy to
add new CSR support even if the compiler does not support.

Unify CSR access by using the CSR encoding macro.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-11 10:43:48 +08:00
Huang Qi
9e78b235fe riscv: Add more debug related CSR definitions
This patch adds more debug related CSR definitions
to arch/risc-v/include/csr.h.

These definitions are from the RISC-V Debug Specification
Version 1.0 rc1 (https://github.com/riscv/riscv-debug-spec).

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-04-10 21:10:39 +08:00
Omar
01aeeaeac6 ESP32S3 I2S GPIO selection master/slave hase same range for BCLK,WS pin 2024-04-10 15:00:45 +08:00
Omar
4c744f1c0e ESP32S3 configuring gpio pin 19 or 20 ( USB_D+/- ) for any purposes 2024-04-10 15:00:45 +08:00
Omar
b864522b65 ESP32S3 I2S BCLK, WSPIN, DINPIN, DOUTPIN pin range changed to 0 48 2024-04-10 15:00:45 +08:00
Jukka Laitinen
729e9fc8e3 arch/arm64/src/Toolchain.defs: Add -mcpu=cortex-a55 if CONFIG_ARCH_CORTEX_A55 is defined
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-09 19:39:33 -03:00
Xiang Xiao
4ea2aeff6b arch: Remove xxx_intstack_top and xxx_intstack_alloc
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-04-09 16:59:00 -03:00
ligd
4e725ecd44 arch: color the intstack for all the CPUs
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-04-09 16:59:00 -03:00
ligd
3844efb5b8 stack: update up_get_intstackbase API to support cpu id
For crash dump all the CPU intstack

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-04-09 16:59:00 -03:00
simbit18
9967989b02 Fix Kconfig style
Remove spaces from Kconfig files
Remove TABs
Add comments
2024-04-09 10:49:23 +08:00
Eren Terzioglu
c0d7419d11 esp32[c3|h2|c6]: Bugfixes for filesystem errors 2024-04-09 10:48:40 +08:00
Alan Carvalho de Assis
67dbdb18e3 stm32f76xx77xx_rcc: Fix PLLI2S factor divisors
Value was set with PLLSAI factor divisors instead of
PLLI2S factor divisors.

Signed-off-by: Alan C Assis <acassis@gmail.com>
2024-04-09 10:45:13 +08:00
Jukka Laitinen
5e5640992d arch/arm64/src/imx9/imx9_flexio_pwm.c: Fix wrong input scale and pulse width
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-08 03:02:42 +08:00
W-M-R
bbec17daff sim/kconfig: select ARCH_TOOLCHAIN_GNU
Missing ARCH_TOOLCHAIN_GNU option causes sim's kasan recursion

Signed-off-by: W-M-R <mike_0528@163.com>
2024-04-07 14:57:44 -03:00
Jorge Guzman
f7a98db234 stm32h7/fdcan: fixed kconfig and debug register
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
2024-04-07 14:56:58 -03:00
Igor Mišić
510b6221ca stm32h7/stm32_i2c: fix sending large data over i2c
To trigger TC interrupt NBYTES needs to be set before RELOAD is disabled
2024-04-07 14:54:47 -03:00
W-M-R
0ede3fc377 kasan: Implementing global variable out of bounds detection
Extracting global variable information using scripts:
kasan_global.py:
1. Extract the global variable information provided by the -- param asan globals=1 option
2. Generate shadow regions for global variable out of bounds detection
Makefile:
1. Implement multiple links, embed the shadow area into the program, and call it by the Kasan module

Signed-off-by: W-M-R <mike_0528@163.com>
2024-04-07 23:31:13 +08:00
Pressl, Štěpán
bf3a5bb4cb arch/arm/src/samv7/sam_pwm.c: adjust arch driver to DCPOL options
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
2024-04-06 13:12:08 +08:00
Jukka Laitinen
0f596ec496 arch/arm64/src/imx9: Add TPM based PWM driver for IMX9
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-05 10:13:32 -03:00
Tiago Medicci Serrano
65bd548521 esp32[c3|c6|h2]: Fix RTC data placement
RTC data was not being correctly placed on RTC's memory data due to
linker issues. Also, the image's RTC memory segment was not being
properly parsed by the bootloader.
2024-04-05 02:50:19 +08:00
Jukka Laitinen
62a64b06bc arch/arm64/src/imx9: Add imx9 usb device driver
This is a modified version from imxrt driver, which has the same controller.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-04 15:47:32 -03:00
Jukka Laitinen
d1d5a4abfe arch/arm64/src/imx9/hardware/imx93/imx93_memorymap.h: Clean up some base address macros
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-04 15:47:32 -03:00
Jukka Laitinen
4d3b753a1a arch/arm64/include/imx9/imx93_irq.h: Define IRQ_USBx interrupt numbers
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-04 15:47:32 -03:00
Jukka Laitinen
47f37e84ba arch/arm64/src/imx9: Flex-IO based PWM driver for imx9
This is a high resolution PWM driver, utilizing one 16-bit Flex-IO timer for
generating PWM period and the rest of the timers to generate PWM duty cycles.

This means that the period has to be the same for every PWM generated from one
FLEXIO block, but this way we can get 16-bit resolution for the PWM signals.

For a typical IMX9 HW there are 8 timers for each Flex-IO block, which means
that by using this driver one can get 7 PWM outputs from one block.

This driver can be later extended to have configuration options to use all
8 channels per flex-io by either using 8+8 -bit timer (less resolution) or by
using an external trigger from an LPIT.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-04 23:17:59 +08:00
Ville Juven
3294598541 arm64/imx9: Add GPIO, IOMUX and external interrupt support
This adds memory mapped registers and drivers for digital I/O.
2024-04-04 12:12:01 +08:00
Ville Juven
f50c439f21 imx9_clockconfig.c: Add way to query clock frequency
The frequency of a clock source is stored in a LUT. Currently the
LUT contains the PLL frequencies set by the boot ROM code.
2024-04-04 12:12:01 +08:00
Mingjie Shen
6aae7ba0eb arch/arm/src/s32k3xx: Fix incorrect check for invalid port or pin number
Signed-off-by: Mingjie Shen <shen497@purdue.edu>
2024-04-04 11:53:06 +08:00
Mingjie Shen
99109b8d79 all: Fix accessing uninitialized local variables
Prior to this commit, in elf_emit() and elf_emit_align(),
ret was uninitialized if total was 0.

Signed-off-by: Mingjie Shen <shen497@purdue.edu>
2024-04-04 11:51:54 +08:00
Mingjie Shen
f2082acfd7 arch/arm/src/am335x: Fix incorrect signedness of variable
The check `if (delta < 0)` in line 353 and 407 would always be false
if delta were unsigned.

Signed-off-by: Mingjie Shen <shen497@purdue.edu>
2024-04-04 11:50:36 +08:00
chenwen@espressif.com
5b83af1607 xtensa/esp32s3: Fix duplicate definition warnings
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-04-03 23:12:43 +02:00
Eren Terzioglu
19b58a78da risc-v/espressif: Fix empty cpuint number 2024-04-02 16:40:24 -03:00
Tiago Medicci Serrano
9520edeb16 espressif/rmt: Fix minor issues regarding formatting and comments
This commit only fix minor issues regarding formatting and comments
2024-04-02 14:50:59 -03:00
Tiago Medicci Serrano
5ba40d083a esp32/rmt: Use the Espressif`s common RMT driver.
This commit implements the common RMT driver (already available for
the other Espressif's xtensa-based devices) for ESP32.
This allows us to have a proper separation between the lower and
upper-half drivers and use the 'ws2812' example to drive WS2812 RGB
LEDs.
2024-04-02 14:50:59 -03:00
Tiago Medicci Serrano
6b73782c27 esp32: Remove outdated/unnecessary code
These functions are no more used directly by NuttX. There is no
need to keep them.
2024-04-02 14:50:59 -03:00
chao an
446e0280b0 arm/stm32f7: fix ci build break
1.
In file included from chip/stm32_rtc.c:31:
chip/stm32_rtc.c: In function 'rtchw_set_alrmar':
chip/stm32_rtc.c:761:11: warning: format '%x' expects argument of type 'unsigned int',
                         but argument 3 has type 'uint32_t' {aka 'volatile long unsigned int'} [-Wformat=]
  761 |   rtcinfo("  ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
      |           ^~~~~~~~~~~~~~~~~~
chip/stm32_rtc.c:761:25: note: format string is defined here
  761 |   rtcinfo("  ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
      |                      ~~~^
      |                         |
      |                         unsigned int
      |                      %08lx

2.

arm-none-eabi-ld: staging/libdrivers.a(userled_lower.o): in function `userled_setled':
drivers/leds/userled_lower.c💯 undefined reference to `board_userled'

Regression:
     stm32h7/linum-stm32h753bi: add support to leds

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-02 15:42:32 +08:00
Yanfeng Liu
3a59644485 build/cmake: kernel mode revision
This fixes kernel mode regression caused by #12011

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-30 12:21:59 +08:00
Tiago Medicci Serrano
4b3b22cbeb esp32/rmt: Remove outdated RMT driver
The new common RMT driver - already available for ESP32-S2 and
ESP32-S3 - will be implemented in another commit for ESP32.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
573e1a255f esp32s3/[ble/wifi]: Improve code compatibility between SoCs
Introduces a couple of minor changes to make it easier to keep the
code update between different Espressif's SoCs.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
2f8e0c7fd4 esp32s3/ble: Rearrange types, data and functions order
This commit just rearranges the order of the types, data and
functions without modifying them. This is done to make it look more
similar with ESP32's ble adapter and ease maintanence.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
62fbb7f03a esp32s3/ble: Update the name of the interrupt status flags
In order to avoid confusion with other interrupt status flags used
by the system and the common source, rename it to be more specific.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
c07f8ab312 esp32s3: use common espressif code instead of chip-specific.
Most of the functions used to set the peripherals are available for
all Espressif's chips. This commit uses this set of functions and
remove outdated functions that perform the same operations in a
chip level.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
09464ff9bc esp32/[ble/wifi]: Update the wireless drivers
This commit updates the Wi-Fi and the BLE driver of ESP32. Most of
the changes rely on using the common sources and header files for
xtensa-based Espressif's SoCs.

The new Wi-Fi driver supports WPA3-SAE for both Station and SoftAP
mode. BLE's coexistence mode was enhanced according to the latest
libraries.

Please note that other sources required minor changes in order to
be compatible with the common sources.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
007dd34ce8 esp32s3/spiflash: Fix error to pause the other CPU during operation
Whenever a SPI flash operation will take place, it's necessary to
disable the cache and run no code from the flash. This includes
pausing the other CPU (when `CONFIG_SMP=y`). This commit prevents
an error to occur when the CPU core is evaluated before the task
is increased to the max priority.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
78fbc2fc64 esp32/spiflash: Fix error to pause the other CPU during operation
Whenever a SPI flash operation will take place, it's necessary to
disable the cache and run no code from the flash. This includes
pausing the other CPU (when `CONFIG_SMP=y`). This commit prevents
an error to occur when the CPU core is evaluated before the task
is increased to the max priority.
2024-03-29 16:14:27 +08:00
chao an
c7770fddfe qemu/armv7a: add Symmetric Multi-Processing (SMP) support
Bringup Co-Processor by PSCI(Power State Coordination Interface)

Signed-off-by: chao an <anchao@lixiang.com>
2024-03-28 19:30:26 +08:00
chenwen@espressif.com
ffc7442af2 xtensa/esp32s3: Add ESP32-S3 AES driver
1. Support AES-128/AES-256 encryption and decryption

Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-03-28 09:34:04 +08:00
xuxin19
741de4b450 cmake:init protected-mode for CMake build
adjust link options for userspace elf
specify system libs and apps lib to only link with nuttx target in flat build mode

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-03-27 23:01:08 +08:00
chenwen@espressif.com
2911c3aed6 xtensa/esp32s3: Add 16-byte-align SPI-Flash encryption write
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-03-27 17:10:32 +08:00
Dong Heng
397396c587 xtensa/esp32s3: Fix one page program span over 2 pages
One page program can't span over 2 pages.
2024-03-27 17:08:17 +08:00
David Sidrane
3932cb2a3b stm32h7:Serial Fix Logic error in up_dma_txavailable 2024-03-26 20:11:49 -03:00
Tiago Medicci Serrano
075b0e5ac0 esp32s2: Update libc stubs to properly acquire/release locks.
Avoid using static mutex and recursive mutex as the resource to be
acquired/release. Instead, create a specific lock for each call if
it does not exist.
2024-03-26 13:53:39 -03:00
Tiago Medicci Serrano
d56e6de628 esp32: Update libc stubs to properly acquire/release locks.
Avoid using static mutex and recursive mutex as the resource to be
acquired/release. Instead, create a specific lock for each call if
it does not exist.
2024-03-26 13:53:39 -03:00
Tiago Medicci Serrano
44e2e9011f esp32s3: Update libc stubs to properly acquire/release locks.
Avoid using static mutex and recursive mutex as the resource to be
acquired/release. Instead, create a specific lock for each call if
it does not exist.
2024-03-26 13:53:39 -03:00
Eren Terzioglu
f5030573b7 esp32[c3|c6|h2]: Fix filesystem test support 2024-03-26 20:56:48 +08:00
Eren Terzioglu
d322140464 boards/esp32c6: Add esp32c6 DevKitM board support 2024-03-26 09:43:08 +08:00
Eren Terzioglu
cfcedab76b arch/espressif: Fix esp32c6 strange characters on boot 2024-03-26 09:39:12 +08:00
Anthony Merlino
d808ed450c stm32h7: Fix race condition in ADC interrupt handling 2024-03-26 01:20:48 +08:00
Yanfeng Liu
56b125bb82 risc-v/arch.h: revising comments
This revises comments about page tables to help understanding.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-25 20:39:24 +08:00
Ville Juven
6a6798ed31 arch/arm64: Add the head obj to libarch.a as well
On other platforms libarch.a contains the head object. Some projects
depend on this fact so let's provide the head object in the archive here
as well.
2024-03-25 20:38:53 +08:00
GC2020
8a08190394 Modify the enable logic of FDCAN (all STM32H7 series are FDCAN pins) 2024-03-25 01:36:52 +08:00
Ville Juven
738bdb95b7 arm64_head.S: Add explicit input section for __start
As __start must be placed at a precise location, a separate, explicit
input section is needed to guarantee this.

Why is this an issue ? NuttX uses --entry=__start which puts __start in
its correct location, but out-of-tree builds won't work, so it more robust
to use an explicit section for the startup code and enforce its placement
in the linker script.
2024-03-23 00:21:54 +08:00
Ville Juven
00986bdd09 arm64/imx9: Add register definitions for LPTMR 2024-03-22 21:37:35 +08:00
Ville Juven
0b8f6af3d6 arm64/imx9: Add register definitions for LPIT 2024-03-22 21:37:35 +08:00
Ville Juven
d2373f4569 arm64/imx9: Add CCM (Clock Controller Module) 2024-03-22 21:37:35 +08:00
ligd
a1836de09a fdt: move fdx_xx extend APIs from boards to drivers
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-22 18:51:33 +08:00
Jukka Laitinen
a54f7ffaa8 arch/arm64/src/common: Remove void * arithmetic
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-03-22 09:48:31 +08:00
simbit18
ac2021b906 Fix Kconfig style
Replace help => ---help---
Remove spaces from Kconfig
Add comments
2024-03-21 22:28:49 +08:00
Ville Juven
7a2edf9414 stm32f7/stm32_foc.c: Set .info_get to foc_lower_ops
This fixes build error (Werror):

Error: chip/stm32_foc.c:1918:12: error: 'stm32_foc_info_get' defined but not used [-Werror=unused-function]
 1918 | static int stm32_foc_info_get(struct foc_dev_s *dev, struct foc_info_s *info)
      |            ^~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
2024-03-21 19:53:29 +08:00
chao an
d90e1cb7b4 arch/tricore: add spinlock support
add atomic test and set operation

Signed-off-by: chao an <anchao@lixiang.com>
2024-03-21 18:47:14 +08:00
Jukka Laitinen
1f6079814a arch/risc-v/src/common/supervisor/riscv_perform_syscall.c: Record the currently running task in risc-v syscall
If a context switch occurs in syscall, the g_running_task need to be recorded for assert logic.
This copies the logic from arm platforms

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-03-21 18:45:41 +08:00
Jukka Laitinen
0dee4eb7f0 arch/arm/src/imxrt/imxrt_start.c: Clear CONTROL register at start to make sure we use MSP as the stack pointer
When entering the function from an external bootloader, the CPU could be using PSP. But the following
code expects MSP to be in use.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-03-21 18:45:00 +08:00
Jukka Laitinen
f1c877d67d arch/risc-v/src/common/riscv_exception.c: Just _exit the user task causing an exception
We shouldn't panic the kernel when a user task excepts, we can just kill the user task and
it's children. Do this by returning to _exit() in kernel context.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-03-20 18:03:15 -03:00
Stuart Ianna
401b3e682c arch/risc-v/litex: Allow FDT to be passed from previous boot change.
Allows a flattened device tree to be passed from either openSBI or the LiteX bios. The FDT is registered can be used, if supported.
2024-03-20 20:53:17 +08:00
Ville Juven
46bd210ae4 arm64/imx9: Add support for imx9 series SoMs, imx93 implemented
Adds support for NXP i.MX9-series System-on-Module chips.

- Support for i.MX93 is added
- CPU is Cortex A55 / ARMv8.2A
  - The chip also contains a Cortex M33, but no support is provided
- Supported drivers include lpuart only for now
2024-03-20 20:13:14 +08:00
Ville Juven
8d52020fe1 arm64_internal.h: Expose prototype for arm64_lowputc
Useful procedure in many places.
2024-03-20 20:13:14 +08:00
Ville Juven
2bed7c4646 arm64_mmu: Add data synchronization barrier after page tables are written
The page tables must be committed to system memory before we can proceed
enabling the MMU. ISB() is not enough to do this.
2024-03-19 15:46:51 -03:00
ligd
327d0789e4 arch: add ARCH_TRUSTZONE_DISABLED choice
We can decide whether use trustzone

After this patch, we can support the following mode:

                             ARCH_HAVE_TRUSTZONE   ARCH_TRUSTZONE_DISABLED  ARCH_TRUSTZONE_SECURE  ARCH_TRUSTZONE_NONSECURE

Without Security Extensions         n                       n                       n                         n
CHIP have NO trustzone

With Security Extensions            y                       y                       n                         n
Only one bin in sec mode

With Security Extensions            y                       n                       y                         n
TEE bin in sec mode

With Security Extensions            y                       n                       n                         y
REE bin in non-sec mode

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-19 18:24:42 +09:00
zhangyuan21
9c0d2e1a3c armv7-a/gicv2: move IRQ to group1 and group0 as the FIQ
Purpose: make the the os crash when busyloop with interrupt disable

Follow the arm gicv2 spec, if we want to use the IRQ and FIQ
simultaneously when not using the processor Security Externsions.
We should:
1. IRQ to Group 1 and FIQ to Group 0;
2. Set CICC_CTLR.FIQEn to 1;

Then in NuttX:
1. implement the arm_decodefiq and directly crash in it;
2. provide interface to change the IRQ to FIQ, e.g. change the
   watchdog IRQ to FIQ, so the watchdog can trigger even with the
   interrupt disabled (up_irq_save() called);

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-19 18:24:42 +09:00
Jorge Guzman
8e0bf9a0b4 stm32h7/linum-stm32h753bi: Add buzzer support
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
2024-03-18 13:48:59 +08:00
Yanfeng Liu
ea8682572c build/cmake: add initial KERNEL mode support
Currently only FLAT mode development can enjoy cmake build system. This
patch tries to add initial kernel mode support. It can build NuttX kernel
and libproxies.a, the latter will be further checked though.

This can already help to build an AMP remote node image as it can share
userland apps living in the AMP master node.

Major changes:

- in top folder:
  - CMakeLists.txt    adjust for KERNEL mode, separate from PROTECTED mode.
- in `syscall`:
  - CMakeLists.txt    add mksyscall target for stubs/proxies generation
- in `syscall/stubs`:
  - CMakeLists.txt    use dependency to mksyscall
- in `syscall/proxies`:
  - CMakeLists.txt    use dependency to mksyscall
- in `arch`:
  - CMakeLists.txt    separate KERNEL from PROTECTED mode.
- in `arch/risc-v/src`:
  - CMakeLists.txt    separate from PROTECTED mode, add sub folders.
- in `arch/risc-v/common`:
  - CMakeLists.txt    add sources and sub-folders for KERNEL mode.
- in `arch/risc-v/k230`:
  - CMakeLists.txt    add sources for KERNEL mode.
- in `boards/risc-v/k230/canmv230/src`:
  - CMakeLists.txt    adjust k230 specific scripts for kernel mode.

New additions:

- in `arch/risc-v/src/nuttsbi/`           add CMakeLists.txt
- in `arch/risc-v/src/common/supervisor/` add CMakeLists.txt

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-15 16:21:23 +08:00
xuxin19
2c9d46f176 cmake:enable libxx for CMake build
distinguish whether to add the CXX header file search path
according to the target Language.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-03-15 01:28:53 +08:00
Yanfeng Liu
ea7dbdc8ac risc-v/k230: fix k230_hart_is_big issue
This patch fixes the issue that k230_hart_is_big() doesn't work in
S-mode. It also adds convenient debug macros to ease debugging process

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-14 00:05:06 +08:00
Yanfeng Liu
1fa2559f00 riscv/k230: add ARCH_HAVE_RESET revise logging
This patch adds board_reset and revises debug logging.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-13 13:46:02 +08:00
Michał Łyszczek
87cec8d5c7 stm32f40xxx_pinmap: add 3rd alternate mapping for USART6
Some stm32 has alternate USART6 pinout on G9/G14 but others have it
on A12/A11. Unfortunately it's very difficult to make proper ifdefs for
this since position is based on package (and pincount) and not chip
itself. Creating such list would take a lot of time. Because of that
I just added another possible config for this pin and moved responsibility
of proper selection onto board code.

Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
2024-03-12 10:09:59 -03:00
Michał Łyszczek
02dc6fa219 stm32_serial.c: fix compilation of onewire driver mode
Onewire driver wants to use "struct up_dev_s *priv", which is extracted
from "struct uart_dev_s" and "struct inode". But inode and uart dev are
only declared when TERMIOS or BSDCOMPAT is also enabled. Without these
driver fails to compile with missing declaration errors. Adding some
additional "#if defined()" to these declarations fix the issue and driver
compiles and works properly (tested with ds18b20 temp sensor).

Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
2024-03-12 13:45:41 +01:00
Marco Casaroli
d048caf1d2 arch/esp32 add openeth mac driver
This driver is used with QEMU, to make it possible
to use networking.

This is not the MAC in ESP32, however, it can be used with QEMU.

The code was shamelessly copied from 31dac92e5f
2024-03-12 08:31:06 -03:00
p-szafonimateusz
768c5a28a1 arch/x86_64: move common Make.defs to common
cosmetic change to simplify intel64 Make.defs

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-12 08:30:37 -03:00
chenwen@espressif.com
277ca97b44 xtensa/esp32: Fix wrong interrupt number
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-03-12 14:36:50 +08:00
Nicolas Lemblé
63782c7ff2 arch/xmc4 Add tickless support 2024-03-11 13:56:07 -03:00
Pressl, Štěpán
9f7f3a6e3a SAMV7: fix typos in Kconfig PWM0 fault input selections - inv. polarity 2024-03-09 18:32:58 -03:00
raiden00pl
be1750d041 arch/nrf91: fix compilation for SPI
remove references to unsupported SPI freq and SPI4 which is not supported
2024-03-10 01:43:11 +08:00
raiden00pl
d33846046e arch/nrf{52|53|91}: fix typo
fix typo sndlock -> sndblock
2024-03-10 01:43:11 +08:00
Eren Terzioglu
11efa29192 esp32h2/scripts: Add simpleboot support for esp32h2 2024-03-09 11:53:47 +08:00
Eren Terzioglu
11a061cad8 esp32c6/scripts: Add simpleboot support for esp32c6 2024-03-09 11:53:47 +08:00
p-szafonimateusz
0fe777abd4 arch/intel64: move timer frequency configuration to common files
this logic can be common for intel64 chips

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-09 11:52:29 +08:00
p-szafonimateusz
636b2309e4 arch/intel64: cosmetic changes for TSC
cosmetic changes for TSC:
- remove unused variables
- add g_ prefix to global variables

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-09 11:52:29 +08:00
p-szafonimateusz
0a24f60e1b arch/intel64: select the system clock source with choice option
this will make it easier to add other sources as system clock

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-09 11:52:29 +08:00
Yanfeng Liu
02d097ac4d riscv/k230: minor revision on PMP settings
This patch simplifies PMP handling for K230 using common APIs.
It also uses `g_misa` variable to expose the MISA issue.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-09 11:52:13 +08:00
p-szafonimateusz
b1fd3da0f6 intel64/intel64_irq.c: support interrupts up to 255
From now all intel64 interrupts are supported.
Required step towards MSI/MSI-X

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-08 20:18:39 -03:00
p-szafonimateusz
2d3c9e00ab intel64/intel64_irq.c: check if IRQ is busy before using
check if interrupt is busy when IRQCHAIN is disabled

this allows user to catch configuration errors and fail early when the
already busy vector is reused

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-08 20:18:39 -03:00
p-szafonimateusz
53aef8e93d arch/x86_64: add SSE instruction support
at default x86_64 supports SSE, SSE2, this commit adds support for
SSE3, SSSE3, SSE41, SSE42 and SSE4A

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-08 08:51:20 +08:00
p-szafonimateusz
8fe76e1271 x86_64/x86_64_initialzie.c: remove up_calibratedelay
This function is not used anywhere.
For udelay calibration we have the calib_udelay app

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-08 08:50:35 +08:00
p-szafonimateusz
83abf9bd27 arch/x86_64: add addrenv support
this commit adds simple addrenv support for x86_64

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-08 08:50:35 +08:00
p-szafonimateusz
7d95bec148 qemu-intel64: move PCI initialization back to board logic
this partly revert 4123615621 which works OK for PCI serial and network cards
but breaks QEMU EDU due to usage of sem and usleep in IDLE thread context.
Another solution will be provided later.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-07 15:03:40 -03:00
Xiang Xiao
64ea027b1a Replace PRIxPTR with %p and remove the cast of (uintptr_t)
The cast of (uintptr_t) is not necessary, and it is better to use %p

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-03-07 09:59:42 -03:00
Yanfeng Liu
cc389b1984 riscv/nuttsbi: revise PMP manipulation in NuttX SBI
Current NuttX SBI assumes empty PMP settings but that is not always
true, for example some bootloaders may have PMP entries locked before
handling over to NuttX. This patch revises it by not using hardcoded
PMP region number.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-07 09:58:55 -03:00
chenwen@espressif.com
53f50c8183 xtensa/esp32s3: Configure DMA maximum buffer size based on access to different RAM
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-03-07 13:32:28 +08:00
Sammy Tran
b4b7710c63 Disable interrupt during FTFC operation 2024-03-06 13:31:48 -03:00
chenwen@espressif.com
09960c5c7d xtensa/esp32s3: Fix the issue of erasing a wide range of flash sectors
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-03-06 18:13:20 +08:00
Yanfeng Liu
a66c7c3ee1 comments/docs: fix typos in comments
This fix some typos in comments.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-06 13:31:50 +08:00
trns1997
54e9e582d5 Use C++ standard lib from toolchain
Signed-off-by: trns1997 <trns1997@gmail.com>
2024-03-06 08:42:44 +08:00
ligd
113ab704c7 goldfish & qemu: handle MMU table and CONFIG_RAM_END
Reproduce:

configure:
./tools/configure.sh qemu-armv7a:nsh -j8
open kasan:
CONFIG_MM_KASAN=y
run:
qemu-system-arm -cpu cortex-a7 -nographic -machine virt,virtualization=off,gic-version=2 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
error:
run hanged

Rootcause:

In Qemu armv7a, the ram-end reserved for MMU PGTABLE:

And the up_allocate_heap()  directly use the ram-end for heap in arch/arm/src/common/arm_allocateheap.c

*heap_size  = CONFIG_RAM_END - g_idle_topstack;

Then they are conflict.
Usually, we won't use the heap end, so can't find the error.
BUT, the KASAN will use the heap end for shadow, so found the error.

Resolve:

up_allocate_heap() consider of MMU, re-define the RAM_END at chip.h

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-06 09:26:44 +09:00
raiden00pl
a20b3e8335 arch/nrf{52|53|91}/spi: fix error message
wrong parameters were passed to spierr()
2024-03-06 00:50:00 +08:00
Marco Casaroli
73c4f2f1e7 fix(esp32s3_spiflash_mtd): debug type specifiers
These log messages are wrong if we use CONFIG_FS_LARGEFILE.
2024-03-05 22:23:50 +08:00
Michal Lenc
44a087111d samv7: add support for USART TX DMA transfers
This commit adds support for TX DMA transfers for USART peripheral. Code
refactor in sam_serial.h was also required in order to have correct
defines for all possible cases (both RX and TX DMA used, just one used,
none used).

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-03-05 09:48:03 +08:00
Tiago Medicci Serrano
dcad39a962 arch: Fix style warnings regarding included header files
This commit fixes style warnings regarding including header files
outside the `Included Files` section.
2024-03-05 09:45:49 +08:00
Tiago Medicci Serrano
c67502d9b4 riscv: Implement page-fault exception and on-demand paging
When an application is being loaded `up_addrenv_create ` calls
`create_region` to create the address environment. Only the first
entry is mapped when the region is created. Virtual memory that is
not mapped will trigger an exception when accessed. Other memory
pages are allocated and mapped on-demand. This enables setting
larger heap and stack for the process without compromising the
overall system memory.
2024-03-05 09:45:49 +08:00
Tiago Medicci Serrano
ae9ef972c0 paging: Rename existing CONFIG_PAGING to CONFIG_LEGACY_PAGING
Current `CONFIG_PAGING` refers to an experimental implementation
to enable embedded MCUs with some limited RAM space to execute
large programs from some non-random access media.

On-demand paging should be implemented for the kernel mode with
address environment implementation enabled.
2024-03-05 09:45:49 +08:00
SPRESENSE
3b3f2d97e9 arch: cxd56: Follow interface change of set_buf() operation
set_buf() operation is changed to have the argument about
format. Follow the change.
2024-03-04 20:39:44 +08:00
ligd
91f0a0f1a8 Revert "goldfish & qemu: handle MMU table and CONFIG_RAM_END"
This reverts commit 2f7b107608.

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-04 18:08:15 +08:00
ligd
b599fdbc0e stm32: fix compile failed
Error: chip/stm32_sdmmc.c:1911:7: error: variable 'regaddress' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized]
 1911 |   if (priv->base == STM32_SDMMC1_BASE)

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-04 18:08:15 +08:00
Yanfeng Liu
a4d61dea80 risc-v/k230: improvements to support K230 vendor u-boot
Previously we need turn off the PMP locks in K230 vendor u-boot to use
NuttX, this complicates the setup process. This patch supports running
NuttX with original vendor u-boot so that to reduce setup complexity.

It also enables empty NSH prompt string in AMP master config as the apps
side support is ready.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-03 12:04:14 -03:00
ligd
2f7b107608 goldfish & qemu: handle MMU table and CONFIG_RAM_END
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-03 18:57:32 +08:00
ligd
7d45afe871 armv7-a/r: use _ebss as idle stack both in SMP mode or not
It is better take the _ebss as IDLE_STACK_BASE like armv8-m

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-03 02:25:03 +08:00
p-szafonimateusz
d4b17f963d arch/intel64: add HPET timer support as oneshot timer
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-03 02:24:40 +08:00
ligd
51d8bbfbd9 armv7-a/r: use arm_timer to setup perf
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-03 02:19:37 +08:00
ligd
5aeab4a36c armv7-a timer:fix timer overflow.
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-03 02:19:37 +08:00
ligd
8eddf00212 armv7a/r: use register cval to set timer
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-03 02:19:37 +08:00
ligd
dabed3c7fb armv7-a/r: correct maxdelay calculating
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-03 02:19:37 +08:00
Marco Casaroli
0c50af583d feat(esp32s3-bootloader): allow 32MB flash
The scripts already support, we are just
missing the entry in the config.
2024-03-01 16:51:47 -03:00
Marco Casaroli
447cc9698f use apps-or-nuttx-Make.defs for archs
This will allow apps to tweak build configuration of NuttX
2024-03-01 12:59:16 -03:00
ligd
2241969e5a SMP: fix crash when switch to new task which is still running
cpu0 thread0:                        cpu1:
sched_yield()
nxsched_set_priority()
nxsched_running_setpriority()
nxsched_reprioritize_rtr()
nxsched_add_readytorun()
up_cpu_pause()
                                     IRQ enter
                                     arm64_pause_handler()
                                     enter_critical_section() begin
                                     up_cpu_paused() pick thread0
                                     arm64_restorestate() set thread0 tcb->xcp.regs to CURRENT_REGS
up_switch_context()
  thread0 -> thread1
arm64_syscall()
    case SYS_switch_context
     change thread0 tcb->xcp.regs
    restore_critical_section()
                                     enter_critical_section() done
                                     leave_critical_section()
                                     IRQ leave with restore CURRENT_REGS
                                     ERROR !!!

Reason:
As descript above, cpu0 swith task: thread0 -> thread1, and the
syscall() execute slowly, this time cpu1 pick thread0 to run at
up_cpu_paused(). Then cpu0 syscall execute, cpu1 IRQ leave error.

Resolve:
Move arm64_restorestate() after enter_critical_section() done

This is a continued fix with:
https://github.com/apache/nuttx/pull/6833

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-01 21:05:00 +09:00
Tiago Medicci Serrano
b03c9cf5f8 esp32s3: Fix symbol collision between mbedTLS and the Wi-Fi driver
This commit closes #11738. Actual fix is tracked in:
https://github.com/espressif/esp-hal-3rdparty/pull/2
2024-02-29 20:47:19 +01:00
chao an
6d50274ebe nuttx/list: rename container_of to list_container_of from public header
Use private naming to avoid conflicts with user applications

In file included from libuv/src/unix/internal.h:25,
                 from libuv/src/unix/udp.c:23:
libuv/src/uv-common.h:57: warning: "container_of" redefined
   57 | #define container_of(ptr, type, member) \
      |
In file included from nuttx/include/nuttx/list.h:47,
                 from nuttx/include/nuttx/tls.h:40,
                 from nuttx/include/nuttx/sched.h:48,
                 from nuttx/include/nuttx/arch.h:87,
                 from nuttx/include/nuttx/userspace.h:35,
                 from nuttx/include/nuttx/mm/mm.h:30,
                 from nuttx/include/nuttx/kmalloc.h:34,
                 from nuttx/include/nuttx/lib/lib.h:31,
                 from nuttx/include/stdio.h:35,
                 from apps/system/libuv/libuv/include/uv.h:59,
                 from libuv/src/unix/udp.c:22:
nuttx/include/nuttx/nuttx.h:48: note: this is the location of the previous definition
   48 | #define container_of(ptr, type, member) \
      |

Signed-off-by: chao an <anchao@lixiang.com>
2024-02-29 19:44:54 +08:00
chenwen@espressif.com
1665114fd1 xtensa/esp32: Fix issue of system blocking when SPIRAM is used as stack
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-02-28 13:31:30 +08:00
chenwen@espressif.com
c14888e759 xtensa/esp32s3: Add the return value of SPI driver
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-02-28 13:30:18 +08:00
p-szafonimateusz
4123615621 x86_64: move PCI bus initialization from qemu-intel64 to common x86_64 and initialize PCI in up_initialize()
many PCI devices must be initialized early during boot process (e.g. PCI serial port)

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-27 10:30:54 -03:00
p-szafonimateusz
cdfce8a055 arch/x86_64: add spinlock support
Add spinlock support for x86_64, needed for SMP

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-27 10:27:34 -03:00
chao an
b413a1f4f7 arm/armv8-r: fix build break if disable CONFIG_UART_PL011
Common code should support the if PL011 is not enabled

Signed-off-by: chao an <anchao@lixiang.com>
2024-02-27 21:22:40 +08:00
p-szafonimateusz
b3c4f3afc3 x86_64/common/Toolchain.defs: change optimization to -Os for CONFIG_DEBUG_FULLOPT
change optimization to -Os for CONFIG_DEBUG_FULLOPT to be compatible with other architectures
and add an option to select CONFIG_DEBUG_CUSTOMOPT

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-26 18:18:20 -03:00
p-szafonimateusz
3a3341ba0e arch/intel64: enable FPU and implement up_fpucmp to pass ostest
enable FPU and implement up_fpucmp to pass ostest

With aggressive optimization enabled (-O2/-O3), ostest FPU test will fail.
This is because the compiler will generate additional vector
instructions between subsequent up_fpucmp() calls (loop vectorization
somewhere in usleep() call), which will consequently overwrite
the expected FPU context (XMM registers).

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-26 18:17:37 -03:00
p-szafonimateusz
5288e063ec newlib: fix support for x86
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-26 23:56:47 +08:00
p-szafonimateusz
b14c3e1e2e arch/intel64: add software reset support
This adds a software reset for intel64, enables the use of
the reboot command from NSH
2024-02-26 23:55:14 +08:00
chenwen@espressif.com
638df3329b xtensa/esp32s3: Fix issue of system blocking when SPIRAM is used as stack
1. Fix issue of system blocking due to disable dcache.
   2. Support Ext-SRAM-Cache mmu mapping in SMP mode.

Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-02-26 12:38:30 -03:00
p-szafonimateusz
743bbfcd7e arch/intel64/Kconfig: add chip choice option
this will be useful for auto selecting CPU features
2024-02-26 20:06:35 +08:00
p-szafonimateusz
39c7ae683f arch/x86_64/Kconfig: remove unused QEMU options
boards definition should be in /boards
2024-02-26 20:06:35 +08:00
p-szafonimateusz
5c85b8618c arch/intel64: prase multiboot2 header before revoking the lower memory
__revoke_low_memory() is called in intel64_lowsetup()

fixes b4b96a6435 (PR #11758) in which the multiboot2 header was accessed
after revoking the low memory which caused page fault.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-24 09:21:04 -08:00
p-szafonimateusz
8c4612be50 arch/intel64: add g_ prefix to global data
to follow NuttX coding standard

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-23 18:16:10 -08:00
p-szafonimateusz
8a43bf1b50 arch/intel64: clear BSS in __nxstart
BSS nulling can now be optimized by the compiler, so it is necessary
to enable SSE instructions early in __nxstart

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-23 18:16:10 -08:00
p-szafonimateusz
b4b96a6435 arch/intel64: convert __nxstart to C function and move appropriate functions there
to follow the approach in other architectures

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-23 18:16:10 -08:00
p-szafonimateusz
f76017ca8a arch/intel64: format asm files, remove unused debug macros
use tab at the beginning of lines, remove C++ comments, fix some tabs to spaces

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-23 18:16:10 -08:00
p-szafonimateusz
16e47d6c8b arch/intel64: fix stack alignment
The stack pointer must be aligned to 16 bytes, otherwise the system crash on the first unaligned data access with vector instruction.
The problem is only observable with optimization enabled, when vector instructions are generated.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-02-23 12:04:54 -03:00
p-szafonimateusz
c3d41195c7 arch/intel64/stackframe.c: fix memset size
this is a follow up to the change from 2335b69120 which missed
updating stack frame length for this memset

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-23 12:04:54 -03:00
Michał Łyszczek
aa75b7f27c stm32/stm32f30xxx_rcc.c: fix broken flash setup
During removal of F1 related stuff, code that configures FLASH
latency was removed, which rendered some of the F3 line unbootable.

It was done by mistake, since previous removed block was
'#ifdef VALUE_LINE', and block with FLASH code was '#ifndef VALUE_LINE'
and so it should not have been removed.

Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
2024-02-23 06:11:26 +01:00
p-szafonimateusz
9b0017659c arch/x86_64: add cmake support
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-23 07:45:57 +08:00
nuttxs
d2b4734756 Deinitialize ESP32-S3 SPI slave GDMA engine 2024-02-22 04:34:29 -08:00
chao an
996b9377a7 arch/tricore: add Infineon AURIX TriCore support
Add support for tricore TC397

1. Porting based on AURIX TC397 KIT_A2G_TC397_5V_TFT evaluation board

   https://www.infineon.com/cms/en/product/evaluation-boards/kit_a2g_tc397_5v_tft/

2. In order to avoid license and coding style issues, The chip-level code
   still uses the implementation of AURIX Development Studio SDK.
   The SDK package will be downloaded as a third-party package during compilation:

   https://github.com/anchao/tc397_sdk

3. Single core only, SMP implementation will be provided in the future.
4. Implemented the basic System Timer, ASCLIN UART driver.
5. Only the Tasking tool chain is supported (ctc/ltc, license maybe required)
6. 'ostest' can be completed on the TC397 development board.

How to run?

1. Setup the tasking toolchain and license

$ export TSK_LICENSE_KEY_SW160800=d22f-7473-ff5d-1b70
$ export TSK_LICENSE_SERVER=192.168.36.12:9090

2. Build nuttx ELF

$ ./tools/configure.sh tc397/nsh
$ make -j
...
artc I800: creating archive libc_fpu.a
LD: nuttx

3. Switch to windows PC, setup AURIX-studio to Debugger Launcher

4. Replace runing ELF to nuttx, and re-download ELF

Signed-off-by: chao an <anchao@lixiang.com>
2024-02-21 21:39:19 -08:00
Eren Terzioglu
aa0dccb7bc risc-v/espressif: Add SPI Flash support 2024-02-21 07:19:51 -08:00
Yanfeng Liu
4456b2db29 risc-v/k230: add IPI support to speed up RPTUN/RPMSG
This patch adds inter-processor interrupt support using K230 mailbox
device to improve the RPMsg efficiency. The polling logic has been
dropped.

Major changes:

- in arch/risc-v/include/k230:
  - irq.h          add IRQ for IPI devices
- in arch/risc-v/src/k230:
  - Kconfig        add IPI related config, increase polling delay
  - Make.defs      add k230_ipi.c to CHIP_SRCS
  - k230_hart.c    fix typo, add notes of zero MISA reading w/ NUTTSBI
  - k230_irq.c     use K230_PLIC_IRQS as ext IRQ limit to support IPI
  - k230_rptun.c   use IPI instead of polling
- in boards/risc-v/k230/canmv230/configs
  - master         enable IPI support
  - remote         enable IPI, TMPFS, RPMSGFS etc

New additions:

- in arch/risc-v/src/k230:
  - k230_ipi.h     add K230 IPI related defintions
  - k230_ipi.c     add K230 IPI driver

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-21 04:37:03 -08:00
chao an
f4bc5b5c6b cmake/toolchain: fix compiler warning on ARM32
-- Detecting CXX compile features
-- Detecting CXX compile features - done
arm-none-eabi-gcc: error:  -Wstrict-prototypes: No such file or directory
arm-none-eabi-gcc: error:  -Wstrict-prototypes: No such file or directory
-- Configuring done
-- Generating done

Signed-off-by: chao an <anchao@lixiang.com>
2024-02-21 00:43:42 -08:00
Rdk-T
cc95a76795 Add XMC4 flash command sequence API 2024-02-20 08:52:27 -08:00
simonatoaca
bb6f32d610 esp32-sparrow-kit: Add I2S support for the board's microphone
The board's microphone uses 24-bit i2s and this commit also fixes
the segmentation fault caused by the audio buffer overflow.

arch/xtensa/src/esp32/esp32_i2s.c: Fix bug regarding 24-bit audio and add AUDIOIOC_STOP to ioctl
drivers/audio/audio_i2s.c: Report number of channels on AUDIOIOC_GETCAPS
in boards/xtensa/esp32/esp32-sparrow-kit:
	/configs/nsh/defconfig: Add I2S configs
	/src/esp32-sparrow-kit.h: Add the signature of esp32_i2sdev_initialize()
	/src/esp32_bringup.c: Add call to esp32_i2sdev_initialize()

Signed-off-by: simonatoaca <simona.alexandra2000@gmail.com>
2024-02-20 06:46:06 -08:00
Tiago Medicci Serrano
e49684d781 risc-v/esp_<rmt|ws2812>: Implement the RMT peripheral for ESP32 RVs
This commit implements the RMT peripheral for all the supported
Espressif's RISC-V devices. It also implements the support for the
WS2812 addressable RGB LED using the RMT peripheral.
2024-02-19 19:02:34 -08:00
Tiago Medicci Serrano
62a608b558 xtensa/esp_ws2812: Get actual RMT clock to encode WS2812 data
WS2812 data is encoded into RMT items according to the RMT clock
source. This commit makes it by using the actual clock source in
spite of a pre-defind value.
2024-02-19 19:02:34 -08:00
Xiang Xiao
2e91c07ca7 Remove the back slash from long literal string
since the back slash is only needed for the long macro definition

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-19 16:43:15 +01:00
chao an
e11c793b33 toolchain/tasking: add dependencies rules for tasking compiler
Tasking compiler uses customized compilation options for generating dependencies files

Signed-off-by: chao an <anchao@lixiang.com>
2024-02-19 03:36:43 -08:00
freakishness
b283e39eb5 Add support for hpm6360evk 2024-02-18 09:17:56 -08:00
raiden00pl
02b418a7ea arch/arm/src/nrf52/CMakeLists.txt: format file 2024-02-18 07:40:41 -08:00
raiden00pl
b3b543e093 arch/nrf52: add initial support for IEEE 802.15.4
Supported features:

- frame transmition
- frame reception and filtering
- immediate ACK (incoming and outgoing)
- promiscuous mode
- delayed transmision
- radio events trace
- setting pending bit for all incoming Data Request frames
- un-slotted CSMA-CA

Work in progres features (some logic is present, but they require more work):

- beacon transmision (periodic transmition works, but requires verification)
- slotted CSMA-CA
- GTS

Fetures not implemented:

- enhanced ACK (Enh-ACK)
- enhanced beacon
- low power mode
- advanced features from IEEE 802.15.4e (DSME, TSCH)

Added examples for boards:

- nrf52832-dk: mrf24j40_6lowpan
- nrf52832-dk: mrf24j40_mac
- nrf52840-dk: ieee802154_6lowpan
- nrf52840-dk: ieee802154_mac
- nrf52840-dongle: ieee802154_mac
- nrf9160-dk-nrf52: ieee802154_6lowpan
- nrf9160-dk-nrf52: ieee802154_mac
2024-02-18 07:40:41 -08:00
raiden00pl
3f763f5d69 nrf52/nrf52_radio: various changes to support IEEE802154
- remove read-write logic - this should be handled by radio protocol implementation
- remove EVENTS and TASKS bit definitions - we can just use a signle definition
- add more radio ops
- fix frequency configuration
- fix printf warnings
- fix radio reset
2024-02-18 07:40:41 -08:00
Bowen Wang
de61a8e009 intel64/Toolchain.defs: move toolchain releated option to Toolchain.defs
Follow other arch does, move common toolchain option to Toolchain.defs

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-02-18 05:34:53 -08:00
Bowen Wang
415f13372d x86_64_netinitialize: support CONFIG_NETDEV_LATEINIT for x86_64
Now x86_64 can use config CONFIG_NETDEV_LATEINIT

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-02-18 05:34:53 -08:00
raiden00pl
f4324e118e arch/nrf{52|53|91}: let the events from comparator correspond to CC id
this allows us to use the same value to set the comparator and handle comparator events,
making RTC easier to use
2024-02-17 05:00:35 -08:00
raiden00pl
a77c3b367a arch/nrf{52|53}/gpiote.c: fix event reconfiguration for a given pin
if a given pinset is already used, we need to update it, not add another event
2024-02-17 05:00:06 -08:00
raiden00pl
dbbe06193e arch/arm/src/nrf{52|53|91}/xxx_rtc.h: include nuttx/irq.h
fixes undefined xcpt_t error that sometimes occurs
2024-02-17 04:59:49 -08:00
Alan Carvalho de Assis
940f1bace0 arch/stm32h7: Clear all PWM channel when during STOP
I noticed when executing pwm STOP command in
multichannel mode, the channel still outputting.

This commit fixes this issue.

Signed-off-by: Alan C. Assis <acassis@gmail.com>
2024-02-15 21:27:22 -08:00
Alan Carvalho de Assis
5975b25951 arch/stm32f7: Clear all PWM channel when during STOP
I noticed when executing pwm STOP command in
multichannel mode, the channel still outputting.

This commit fixes this issue.

Signed-off-by: Alan C. Assis <acassis@gmail.com>
2024-02-15 21:27:22 -08:00
Alan Carvalho de Assis
6d346793ee arch/stm32: Clear all PWM channel when during STOP
I noticed when executing pwm STOP command in
multichannel mode, the channel still outputting.

This commit fixes this issue.

Signed-off-by: Alan C. Assis <acassis@gmail.com>
2024-02-15 21:27:22 -08:00
Yanfeng Liu
709a1c61f1 risc-v/k230: revise k230 hart operations and kernel linker script.
This patch revises `k230_hart.[ch]` by:

  - revising big core boot/stop control.
  - making k230_hart_is_big() available in S-mode.
  - adding more comments.

This patch also revises the `ld-kernel.script` so that to match the
latest MMU pgtable design.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-15 19:53:24 -08:00
Yanfeng Liu
a4b22fe999 risc-v/k230: initial Asymmetric Multi-Processing support
K230 chip has two T-Head C908 RiscV cores, previously we run NuttX
on either little or big cores. This patch runs NuttX on both cores
with OpenAMP support via the RPTUN driver.

New additions:

- in arch/risc-v/src/k230
  - k230_rptun.c              K230 RPTUN driver
  - k230_rptun.h              K230 RPTUN driver header file

- in baords/risc-v/k230/canmv230
  - configs/master            Build config for master node
  - configs/remote            Build config for remote node
  - scripts/ld-rptun.script   Build script for RPTUN

Major changes:

- arch/risc-v/Kconfig         Select NUTTSBI_LATE_INIT upon NUTTSBI
- in arch/risc-v/include
  - k230/irq.h                Add UART3 IRQ defs
- in arch/risc-v/src/k230
  - Kconfig                   Add RPTUN related config items
  - Make.defs                 Add k230-rptun.c to sources
  - hardware/k230_memorymap.h Add K230 device and CSR defs
  - k230_hart.c               Add hart ctrl for RPTUN
  - k230_hart.h               Add hart ctrl for RPTUN
  - k230_mm_init.c            Add Svpmbt to support RPTUN
  - k230_start.c              Revised to support RPMsg UART
- in boards/risc-v/k230/canmv230
  - scripts/Make.defs         Add RPTUN script selection
  - src/canmv_init.c          Add RPTUN and RPMsg_UART initialization
- in Documentation/platforms/risc-v/k230/boards/canmv230
  - index.rst                 Add AMP usage information.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-13 10:34:21 -03:00
Nicolas Lemblé
4a85fbfd09 arch/xmc4: Fix CCU registers 2024-02-13 10:33:04 -03:00
Eren Terzioglu
de948babbf xtensa/esp32s2: Fix esp32s2 wdt interrupt bug 2024-02-13 10:31:35 -03:00
Roberto Bucher
4a04c22147 STM32-H745 files for pysimCoder 2024-02-10 20:01:12 -03:00
trns1997
5c118967bb build xmc4800-relax using CMake 2024-02-10 10:20:59 -03:00
Raman Gopalan
0967eb4c24 avr32dev1: Fix compilation and nsh boot-up
I recently imported NuttX version 6.0 (and nsh) into a Microchip
Studio project [1] on Windows to figure out what was going wrong with
the avr32dev1 build. I also briefly checked NuttX version 10.

I worked with the assumption that the avr32 (avr32dev1) specific
changes to the codebase were minimal across NuttX releases.

For the initial proof of concept I used Microchip Studio version 7.0
(with the recent Microchip's ASF updates). I use avr32-gcc (4.4.7)
hosted here [2] for building NuttX for avr32dev1 on GNU/Linux.

Even with the Microchip Studio project, I had initial debug problems
with just stepping through the code a line at a time. I had to bring
in crt0, a trampoline stub and the linker file from one of my older
projects to really build on the suspicion I had with the linker file.

Perhaps an older version of avr32-gcc did something differently. I am
not sure about this. I used avr32-objdump to see the output sections
of the generated elf file. I just had to tweak the linker script to
ensure correct linking of the sections.

With those changes, I was able to inspect the UART sections within
NuttX Microchip Studio project.

Second important change: the transmit pin: I had to reassign the pin
to see the nsh console.

These are the currently assigned UART pins:

RX: PA_24 -> Physical IC pin 59
TX: PB_02 -> Physical IC pin 24

For the avr32dev1 board, they are pins: J1 (berg pin 28) and J2 (berg
pin 10).

In addition, the PR fixes silly compilation problems with avr32dev1.

I have tested the nsh build with my avr32dev1 boards. I used Atmel ICE
to program one of them (flash at 0x80000000) and dfu-programmer to
test my other board (flash at 0x80002000). The other RS-232 parameters
are the same as they were.

References:
[1]: https://github.com/ramangopalan/nuttx_avr32dev1
[2]: https://github.com/ramangopalan/avr32-gnu-toolchain-linux_x86_64
2024-02-08 11:12:13 -03:00
Michal Lenc
2849cd7c6d arch/samv7: add function to retrieve reset cause from HW
SAMv7 reset controller stores the cause of last reset (SW reset, power up,
pin reset etc.) in status register. This commit adds function that allows
the board to retrieve this information. This function should be called
from board support layer either during initialization or based on
incoming ioctl call.

Adding the sam_get_reset_cause() to sam_systemreset.c also resulted in
always compiling this file by default and only putting up_systemreset()
under CONFIG_SAMV7_SYSTEMRESET option.

Also header file sam_systemreset.h was created as it defines reset types
in comfortable manner for future processing in board layer. This is done
to avoid passing boardctl dependent structure to architecture layer.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-02-07 13:26:37 -03:00
Aaron Matlock
470ad35508 cmake: Fixed nucleo-u5a5zj-q 2024-02-07 03:20:43 -08:00
Jukka Laitinen
888dc229fa arch/risc-v/src/mpfs/mpfs_serial.c: Allow switching uart output to console off
By setting "isconsole" to false, mpfs_serial stops outputting to console.

This can be used to disable output to debug console in low level.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:53:05 -08:00
Jukka Laitinen
a28f6716d5 arch/risc-v/src/mpfs/mpfs_irq.c: Fix up_irqinitialize for warm reboot
It is possible that a PLIC IRQ is claimed but not completed at warm
reset. This occurs at least if there is a fault in the middle of irq
handler execution.

To recover from such situation, we can complete all IRQ:s in PLIC;
this completes any already claimed IRQ, but has no effect on IRQs
which are not claimed or not enabled.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:52:46 -08:00
Jukka Laitinen
df01c83c25 arch/risc-v/src/mpfs/mpfs_i2c.c: Recover i2c from pending transactions in warm boot
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:52:31 -08:00
Jukka Laitinen
2b10b38c1d arch/risc-v/src/mpfs/mpfs_i2c.c: Add more i2cerr traces
Add sanity checks for debugging possible errors in the driver.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:52:31 -08:00
Jukka Laitinen
120dfbd45f arch/risc-v/src/mpfs/mpfs_i2c.c: Correct i2c reset / error recovery
- Use mpfs_i2c_deinit+mpfs_i2c_init sequence to re-initialize i2c block
- Use the i2c mutex to protect the reset; in case there are several devices
  on the same bus, and one of them resets the bus, reset must not occur in
  the middle of another device's transfer.
- Move irq attach to the i2c_init as the irq detach is in i2c_deinit

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:52:31 -08:00
Jukka Laitinen
fc4b39b1dd arch/risc-v/src/mpfs/mpfs_i2c.c: Add more error status codes
Add more error status codes to help debugging in the future.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:52:31 -08:00
Jukka Laitinen
dae31dc866 arch/risc-v/src/mpfs/mpfs_i2c.c: Clear I2C_CTRL bits when initializing/deinitializing bus
Ensure that there are no pending state or interrupts in the i2c controller. This removes
errors caused by deinitialize/initialize sequences in error cases.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:52:31 -08:00
Eero Nurkkala
bcf7aa4b63 risc-v/mpfs: i2c: perform sanity checks
Replace risky DEBUGASSERT()s with real sanity checks. Also,
do a few more checks as the system might occasionally fire an
interrupt if the system has been restarted while in middle of
an i2c transaction.

Yet, modify i2c_transfer() function so that up_disable_irq()
is always called at the end to better prevent ill-timed irqs.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-02-06 08:52:31 -08:00
Eero Nurkkala
b0cef9e008 risc-v/mpfs: i2c: prevent out of bounds read access
priv->msgid may grow past its boundaries, causing
struct i2c_msg_s *msg = &priv->msgv[priv->msgid]
to read data out of boundaris.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-02-06 08:52:31 -08:00
Rdk-T
7f01db30dc Add EtherCAT support on xmc4800-relax. 2024-02-05 22:23:30 -08:00
SPRESENSE
a303ec8653 arch: cxd56xx: Add new feature to use GNSS RAM
As long as the GNSS feature is not used, GNSS RAM can be used as general memory.
This memory is 640KByte total, which is lower performance than the application RAM.
It is possible to locate text, data and bss into GNSS RAM and to use as heap area.
2024-02-05 05:53:51 -08:00
SPRESENSE
fc5ae43dda arch: cxd56xx: Add function to control GNSS RAM clock
Add function to enable and disable GNSS RAM clock.
2024-02-05 05:53:51 -08:00
SPRESENSE
1b3b12ed00 arch: cxd56xx: update loader and gnssfw version
Update loader and gnssfw to version 2.2.20591
2024-02-05 05:53:51 -08:00
Adam Comley
399cd88e7f Support RP2040 Clock Outputs 2024-02-04 16:51:53 -08:00
Xiang Xiao
ebc6924b26 risc-v/mpfs: Remove thee unused seq[s|m] fields
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-04 09:54:05 +01:00
Xiang Xiao
1e3914ec9d rptun: Remove the unused shmemname field and argument
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-04 09:54:05 +01:00
Xiang Xiao
6a6bd30500 rptun: Remove the empty implementation of get_firmware and get_addrenv
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-04 09:54:05 +01:00
Xiang Xiao
43d51cd4fc arch: Remove the identity mapping of up_addrenv_va_to_pa and up_addrenv_pa_to_va
and reuse the reuse the implementation from:
drivers/misc/addrenv.c

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-04 09:54:05 +01:00
Yanfeng Liu
73ecd741e7 risc-v/common: add param to mmu_flush_cache interface
Current mmu_flush_cache() hook lacks the reg param which needed by
some targets. So this PR adds the param and update existing targets
using that hook.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-03 22:05:42 -08:00
Tomáš Pilný
3e85c1886e esp32/dac-one-shot: lower-half driver for ESP32 internal DAC
Enable with ./tools/configure.sh -l esp32-devkitc:dac
DAC channel 0 = GPIO 25
DAC channel 1 = GPIO 26
default path: /dev/dac0

Resolution 8 bits = values 0~255
Voltage: 0~Vref

The reference voltage 'Vref' here is input from the pin VDD3P3_RTC
which ideally equals to the power supply VDD (3.3V).
2024-02-02 09:23:28 -08:00
Ville Juven
8e4b2e8a2a arch/arm_addrenv_pgmap.c: Add minimal page map implementation for ARM 2024-02-02 09:09:55 -08:00
Ville Juven
15f19c32ac arch/addrenv: Add utility function to wipe one page
up_addrenv_page_wipe can be used to wipe a single page of memory.
2024-02-02 09:09:55 -08:00
Yanfeng Liu
6594439271 risc-v/nuttsbi: fix weak sbi_late_initialize issues
Weak function sometimes can't have strong implementation linked.
This patch uses NUTTSBI_LATE_INIT config and normal function instead
to avoid those issues.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-01 21:26:16 -08:00
Jari Nippula
e40b66bd6f risc-v/mpfs: wrapper for sdio device drivers
Additional mpfs_sdio layer on top of mpfs_emmcsd and mpfs_coremmc
block device drivers to let both block devices be enabled at the
same time.
2024-02-01 02:07:32 -08:00
Yanfeng Liu
dbe42db611 arch/Kconfig: replace RPTUN_PING with RPMSG_PING
The RPTUN_PING option has been replaced by RPMSG_PING but this
use for PERF_EVENTS is left behind, so replace it here as well.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-01 16:50:23 +08:00
Eren Terzioglu
d1db1810ad risc-v/espressif: Rename espressif/esp32c3 as esp32c3
risc-v/espressif: Rename espressif/esp32c6 as esp32c6
risc-v/espressif: Rename espressif/esp32h2 as esp32h2
2024-01-30 08:32:05 +01:00
Eren Terzioglu
c8d7c81cb9 risc-v/esp32c3: Rename legacy approach esp32c3 as esp32c3-legacy 2024-01-30 08:32:05 +01:00
Eren Terzioglu
4c4d62ff93 Rename espressif folder as common/espressif 2024-01-30 08:32:05 +01:00
Eren Terzioglu
721c37a876 risc-v/esp32c6: Remove duplicated esp32c6 implementation 2024-01-30 08:32:05 +01:00
Yanfeng Liu
0f169f50c4 risc-v/k230: add big core support
Previously NuttX runs on little core of K230, this patch allows NuttX to
run on the big core as well.

Within folder `arch/risc-v/src/k230`:

- Changes:

    - CMakeLists.txt      add k230_hart.c to sources list
    - Make.defs           add k230_hart.c to sources list
    - chip.h              add inclusion to k230_hart.h etc
    - k230_irq.c          move sbi_late_init() to k230_hart.c
    - k230_start.c        add support to run on big core
    - hardware/:
      - k230_memorymap.h  add T-Head C908 specific CSR

- Additions:

    - k230_hart.c         sbi_late_init w/ hart initialization
    - k230_hart.h         header file

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-29 09:06:28 +01:00
raiden00pl
9d761b8ca4 arch/{nrf52|nrf53|nrf91}/tim.c: fix typo
fix offset for EVENT COMPARE0
2024-01-28 09:46:34 -08:00
Yanfeng Liu
f69f0674f6 arch/risc-v: add status fields for VS and XS
add defintions for vector extension and additional user-mode
extension fields for MSTATUS and SSTATUS registers.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-28 06:38:25 -08:00
ThomasNS
fff193324d xmc4 ccu4 register map 2024-01-27 20:14:02 -08:00
Yanfeng Liu
bb63f8f36d risc-v/canmv230: add CMake support
Adding CMakeLists.txt files to support CMake build system.
Note that only FLAT build works now due to limitations of current
CMake build system.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-27 00:56:57 -08:00
Benign X
8ba74d06c6 arch/sim: fix X11 compile failed 2024-01-27 00:51:32 -08:00
chenwen@espressif.com
ba1b96e9d9 xtensa/esp32s3: Add DMA peripheral to spi driver configuration
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-01-26 19:14:04 -08:00
chenwen@espressif.com
8bef8ee9d5 xtensa/esp32s3: Fix crash issue that occurs when deleting a semaphore in WPA3
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-01-26 04:45:26 -08:00
Takeyoshi Kikuchi
8571893435 arm: sama5: sam_serial: fix to compile with "UART Flow control enabled" on SAMA5D2.
SAMA5D2 has UART (TX/RX only) and FLEXCOM USART (with control pins).
UART has only TX/RX, so if I try to use flow control with FLEXCOM USART,
there is no register definition on the UART side and get a compilation error.

Signed-off-by: Takeyoshi Kikuchi <kikuchi@centurysys.co.jp>
2024-01-26 11:25:23 +08:00