Provide initial support for audio through the I2S peripheral to the
CS4344 audio codec on ESP32-S3-DevKitC-1 board.
Please check documentation for usage examples.
The master clock frequency should be multiple of the sample rate
and bit clock at the same time. Then, check if the current master
clock satisfies such a condition and set it accordingly otherwise.
In order to gracefully stop the I2S stream, add an interface to set
a `streaming` status variable that sets the `AUDIO_APB_FINAL` flag
that will be handled by the upper layers of the audio subsystem.
According to RX/TX operation, the DMA descriptors (inlink/outlink)
should be set differently. When setting the inlink, the `suc_eof`
field must be cleared by software (it will be set by hardware when
a packet is received). Similarly, the `length` field will be set
by hardware a packet is received.
Define macros used to access the registers of the GDMA channels
according to the selected channel in the header file, enabling them
to be used by other drivers.
By splitting into two different functions the setup of the DMA
descriptors and the action of loading it to the GDMA outlink
register, it enables us to "cache" DMA descriptors ready to be send
and, then, just load them whenever we are able to actually send it.
The macro `SET_BITS` only sets the bits according to the bit mask
and, once it's being used to set the address field of the GDMA
inlink/outlink register, it's necessary to clean all the bits
corresponding to that field that were eventually setup previously
to avoid messing with the bits that correspond to the current
address being setup.
Whevenever the bit rate is going to be set, it's necessary to first
set the master clock if the underlying device supports it. If it
fails, just return the error code.
According to the struct `mclk_rate_s`, set the default sample rate
to its lowest valid value. This prevents the underlying driver from
setting unsupported values.
Create bmi160_base.h, bmi160_base.c bmi160_uorb.c files, the bmi160_base file stores
public function interfaces, and the bmi160_uorb file stores functions related to the
uorb framework. Switch the character interface and UORB interface through the
macro CONFIG_SENSORS_BMI160_UORB.
Signed-off-by: likun17 <likun17@xiaomi.com>
This option enables architecture-specific memory copy for dynamic code loading.
For example, Ambiq has MRAM regions for instruction which can't load by
the memcpy directly.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Load all sections to LMA not VMA, so the startup code(e.g. start.S) need
relocate .data section to the final address(VMA) and zero .bss section by self.
For example, SiFli and Actions: Background: Device with small sram,
Bootloader run in sram and psram, need boot to Application, with memory overlap
and without XIP. VMA of .data is in "psram" and LMA in "rom", if not enable
`ELF_LOADTO_LMA`, ELF loader will load the section to VMA (will fill bootloader
itself).
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
When the user selects the debug features it will enable
the Debug Errors, Warning and Info by default avoiding
the issue: https://github.com/apache/nuttx/issues/10452
User still need to enable individual debug for each
subsystem, so this patch didn't increase binary size.
xres and yres of video overlay buffer may not same as primay framebuffer.
so add it to check the framebuffer count of overlay
Signed-off-by: rongyichang <rongyichang@xiaomi.com>
A usbdev has only one serial string, so use a unique macro to control it.
For boards that enable board serial string using COMPOSITE_BOARD_SERIALSTR,
PL2303_BOARD_SERIALSTR, CDCACM_BOARD_SERIALSTR, USBADB_BOARD_SERIALSTR,
USBMSC_BOARD_SERIALSTR, and RNDIS_BOARD_SERIALSTR, they need to be replaced
with BOARD_USBDEV_SERIALSTR.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
SiFive document: "ECC Error Handling Guide" states:
"Any SRAM block or cache memory containing ECC functionality needs to be
initialized prior to use. ECC will correct defective bits based on memory
contents, so if memory is not first initialized to a known state, then ECC
will not operate as expected. It is recommended to use a DMA, if available,
to write the entire SRAM or cache to zeros prior to enabling ECC reporting.
If no DMA is present, use store instructions issued from the processor."
Clean the cache at this early stage so no ECC errors will be flooding later.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
After the sack is enabled and the ofosegs has gap, tcp cannot update the
tx_unacked, so the peer received packets are retransmitted after the
timer timeout.
So update tx_unacked first.
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
Check that the base address and region size are properly aligned with
relation to each other.
With NAPOT encoding the area base and size are not arbitrary, as when
the size increases the amount of bits available for encoding the base
address decreases.
Implement the previously empty mpfs_ddr_rand with adapted "seiran128" code
from https://github.com/andanteyk/prng-seiran
This implements a non-secure prng, which is minimal in size. The DDR training
doesn't need cryptographically secure prng, and linking in the NuttX crypto
would increase the code size significantly for bootloaders.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Also move the DDRC clock enablement and reset to mpfs_init_ddr. This doesn't
change the functionality, but is the cleaner place for it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Especially the write calibration must bail out if the memory test timeouts,
otherwise the device will get stuck in running the memory test in sequence,
and it will always timeout.
Negative error value was also not properly returned from mpfs_mtc_test.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
It doesn't make sense to try to auto-determine write latency, it may pass with too low value.
Keep the existing implementation if the write latency has been set to minimum
value, otherwise just set it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Commit 50a8ec6 broke many mmc devices. Only if the flag
priv->caps & SDIO_CAPS_4BIT_ONLY was set, it migth work.
Without the flag, the mmc clock is never set (mmcsd_widebus()
call is terminated early stopping the clock). This flag
is probably not very generic because most mmc hw support
1, 4 and 8 bit modes.
JEDEC specifies a bus width selection procedure, but it's
not implemented in this mmcsd_sdio.c driver. Thus, it's
not known whether the hw supports 1, 4 anf 8 bit modes or
a combination of them.
However, with priv->caps & SDIO_CAPS_4BIT_ONLY the driver
suddenly assigns priv->buswidth = MMCSD_SCR_BUSWIDTH_4BIT
making it the only way to have the driver working.
Fix this by relaxing the above mentioned restrictions.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Provide a way to only customize specific string operations,
such as for memcpy with the DMA capability by ROM.
Signed-off-by: yangdongdong <yangdongdong@xiaomi.com>
