Dave Marples
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d0cda60442
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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Gregory Nutt
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83bc1c97c3
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Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore()
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2016-02-14 16:11:25 -06:00 |
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Gregory Nutt
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f4115ab45c
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Correct LPC11xx priority definitions + fix some typos in comments
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2016-01-25 07:36:26 -06:00 |
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Gregory Nutt
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9140a0fcc4
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Initial support for the NXP LPC11 family and the LPC1115 MCU in particular. Contributed by Alan Carvalho de Assis.
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2015-05-22 14:14:09 -06:00 |
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