Commit Graph

792 Commits

Author SHA1 Message Date
Petro Karashchenko
9b7f9867aa arch/risc-v: use STACK_FRAME_SIZE for in S-mode syscall asm
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-04-04 12:05:53 +08:00
Xiang Xiao
27c80f2586 arch/riscv: Rename g_scratch to g_percpu
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
e959775397 arch/riscv: Access [m|s]scratch through CSR_SCRATCH macro
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
be2fee7d6e arch/riscv: Rename riscv_exception_macros.S to riscv_macros.S
since macro defined in this file is also used in the normal context

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
79aca28bd7 arch/riscv: Remove riscv_sbi.c since it doesn't exist
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
629d9969dd arch/riscv: Rename riscv_syscall_dispatch to riscv_dispatch_syscall
follow other function naming(e.g. riscv_dispatch_irq)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
7a209e6ee8 arch/riscv: Align the macro definition in csr.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Ville Juven
71ced1f1a9 RISC-V: Implement skeleton for a per CPU structure
It might be useful to store things in memory per CPU. The tricky part
is that all CPUs run the same code and see the same memory, so some
kind of centralized access is required.

For now, the structure contains the hart id.

Access to the structure elements is provided via sscratch, which is
unique for every hart!
2022-04-01 16:19:42 -03:00
Ville Juven
c15b6701ce RISC-V: Implement option to run NuttX in supervisor mode (S-mode)
- Add config "ARCH_USE_S_MODE" which controls whether the kernel
  runs in M-mode or S-mode
- Add more MSTATUS and most of the SSTATUS register definitions
- Add more MIP flags for interrupt delegation
- Add handling of interrupts from S-mode
- Add handling of FPU from S-mode
- Add new context handling functions that are not dependent on the trap
  handlers / ecall

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
      thus S-mode is not usable as is, yet.
2022-04-01 16:19:42 -03:00
Gustavo Henrique Nihei
c37474b5bd risc-v/esp32c3: Fix regression on IRQ handling for ECALL instruction
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-04-01 15:29:14 -03:00
Petro Karashchenko
870ca12146 arch/risc-v: get wider visibility for arch instruction macros
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-04-01 10:31:24 +08:00
Ville Juven
e6d6734db2 ARCH_ADDRENV: Add guard against mis-configuration
When process a is switched to process b, the address environment is
swapped with a call to group_addrenv(). The stack upon entry will be
a's, and upon exit b's. This will fail, so a neutral stack is required,
either a kernel stack or an IRQ stack.

Infrastructure for an IRQ stack is already in place, so give a hint
that an interrupt stack should be provided if address environments
are enabled.
2022-04-01 02:02:10 +08:00
Petro Karashchenko
44ee76dcbd arch/risc-v: fix ARCH_RV32 offset for the stub lookup table calculation
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-31 19:34:52 +08:00
Petro Karashchenko
36b0b95eb1 arch/risc-v: include csr.h indirectly through nuttx/irq.h
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-31 19:34:52 +08:00
Petro Karashchenko
5d856971db arch/risc-v: move REGLOAD/REGSTORE macro to riscv_internal.h
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-31 19:34:52 +08:00
Huang Qi
264e39e121 arch/risc-v: Remove unneeded group_addrenv call which handled by riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 19:33:08 +08:00
Huang Qi
f72ca3db5c arch/risc-v: Dont' disable/enable irq in riscv_doirq
Since these codes added to all chips but not fully tested,
so we should changd this behavior.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 19:33:08 +08:00
Huang Qi
32fe25278a arch/risc-v: Merge duplicated logic by riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 19:33:08 +08:00
Huang Qi
a6c22b722f arch/risc-v: Remove deprecated logic from riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 19:33:08 +08:00
Huang Qi
692ffb60b4 arch/risc-v: Rename up_doirq to riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 19:33:08 +08:00
Huang Qi
814c07c792 arch/risc-v: Store/Restore FPU register in exception_common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 11:49:36 +08:00
Huang Qi
379639a371 arch/risc-v/mpfs: Remove duplicated riscv_restorefpu
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-30 13:15:35 +03:00
Gustavo Henrique Nihei
06d0a9f1ad xtensa|risc-v: Make CXX exception and RTTI depend on Kconfig options
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-30 11:19:29 +08:00
Lee Lup Yuen
4456b13c19 riscv/bl602: Remove check for LCD driver
## Summary

`bl602_spi_cmddata()` implements SPI Cmd/Data `SPI_CMDDATA()` for only 3 LCD drivers: ST7735, ST7789 and GC9A01.

This patch removes the check for LCD drivers, so that SPI Cmd/Data will work for all LCD drivers.

More details: https://github.com/apache/incubator-nuttx/pull/5898

## Impact

This change impacts LCD drivers that call `SPI_CMDDATA()`.

Previously `SPI_CMDDATA()` would fail with `ENODEV` for LCD drivers other than ST7735, ST7789 and GC9A01.

After patching, `SPI_CMDDATA()` will work correctly with all LCD drivers.

## Testing

We tested with LVGL and ST7789 on PineCone BL602:

-   [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)

As for regular SPI Devices that don't require SPI Cmd/Data, we tested `CONFIG_SPI_CMDDATA=y` with Semtech SX1262 SPI Transceiver on PineCone BL602:

-   [Testing Cmd/Data](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-30)
2022-03-29 23:09:42 -03:00
Richard Tucker
6d8cd4ec92 arch/risc-v/src/litex/litex_sdio: add litesdcard peripheral driver
See the following for details on the pepheral:
https://github.com/enjoy-digital/litesdcard
2022-03-30 02:35:27 +08:00
Richard Tucker
d557b87b25 arch/risc-v/litex: add cache_invalidate 2022-03-30 02:35:27 +08:00
Lee Lup Yuen
4f885fe6bf riscv/bl602: Implement SPI Cmd/Data
## Summary

To control the Data/Command Pin on ST7789 SPI Display, the SPI Driver flips the MISO Pin as though it was a GPIO.

To implement this on BL602, we reconfigure MISO from SPI Pin to GPIO Pin on the fly inside `bl602_spi_cmddata()`.

When the SPI Port is deselected (after the SPI operation), we revert MISO back from GPIO Pin to SPI Pin. We implement this inside `bl602_spi_select()`.

[More Details Here](https://github.com/lupyuen/st7789-nuttx#spi-cmddata)

## Impact

This change impacts 3 LCD drivers that call `SPI_CMDDATA()`: ST7735, ST7789, GC9A01.

Previously the BL602 SPI Driver would fail with "SPI cmddata not supported" when the above drivers are used.

After the change, the above drivers will set the LCD Data/Command Pin correctly.

## Testing

We tested this implementation of SPI Cmd/Data with NuttX ST7789 Driver and a Logic Analyser on PineCone BL602:

-   [Testing with Logic Analyser](https://github.com/lupyuen/st7789-nuttx#spi-cmddata)

We also tested LVGL with ST7789 on PineCone BL602:

-   [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)

As for regular SPI Devices that don't require SPI Cmd/Data, we tested `CONFIG_SPI_CMDDATA=y` with Semtech SX1262 SPI Transceiver on PineCone BL602:

-   [Testing Cmd/Data](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-29)
2022-03-30 02:01:29 +08:00
Huang Qi
904f7aabda arch/risc-v: Use riscv_fpuconfig to enable FPU
Use common function instead of chip specified code.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-30 01:33:04 +08:00
Huang Qi
20c511fcf1 arch/risc-v: Rename up_fpuconfig to riscv_fpuconfig
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-30 01:33:04 +08:00
Ville Juven
43d5f60a74 MPFS: Fix issue with external interrupt detection
The bitmask overflow'd. Failing test is at mpfs_irq_dispatch / line 69
2022-03-28 22:40:11 +08:00
Huang Qi
83a5e9958f arch/risc-v: Correct comments for current implementations
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-28 13:41:57 +08:00
Huang Qi
35f9265483 arch/risc-v: Move fpu [re]store to common place
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-28 13:41:57 +08:00
Lee Lup Yuen
c67272f9c8 riscv/bl602: Enable SPI Master in SPI Poll Send
## Summary

SPI Poll Send `bl602_spi_poll_send()` doesn't send any SPI Data because it doesn't enable SPI Master and it doesn't clear the SPI FIFO. Also it hangs because it loops forever waiting for the FIFO.

We fix this problem by moving the code that enables SPI Master and clears the FIFO, from SPI Poll Exchange `bl602_spi_poll_exchange()` to SPI Poll Send. (Note that SPI Poll Exchange calls SPI Poll Send)

[More Details Here](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

## Impact

This problem affects all NuttX Drivers that call `SPI_SEND()` on BL602, including the ST7789 Display Driver.

Previously `SPI_SEND()` didn't send any SPI Data and never returns, because it loops forever waiting to receive data.

Now `SPI_SEND()` sends data and returns correctly.

[More Details Here](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

## Testing

We tested the modified SPI Poll Send with NuttX ST7789 Driver and a Logic Analyser on PineCone BL602:

-  [Testing with Logic Analyser](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

We also tested LVGL with ST7789 on PineCone BL602:

-  [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)

As for the modified SPI Poll Exchange, we tested with Semtech SX1262 SPI Transceiver on PineCone BL602:

-  [Testing SPI Poll Exchange](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-25)
2022-03-28 13:32:27 +08:00
Xiang Xiao
8c8c60f70a arch: Add -fsanitize=kernel-address to ARCHCPUFLAGS if CONFIG_MM_KASAN=y
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-27 23:01:47 +03:00
ligd
e87d262c7f arch/Toolchain.defs: add wildcard for EXTRA_LIBS
VELAPLATFO-1491

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-27 22:53:58 +03:00
Huang Qi
052c071867 arch/risc-v: Minor style change
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-26 16:52:13 +09:00
Huang Qi
494230a841 arch/risc-v: Improve performance of context switch
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-26 07:19:09 +09:00
Petro Karashchenko
7afedda89e arch/risc-v: improve style consistency accross chip variants
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-25 10:26:15 -03:00
Ville Juven
44bec4cf8e RISC-V: Add missing code to dumpstate
Just add the kernel stack dumping for completeness
2022-03-24 00:15:28 +08:00
Ville Juven
77e90d9c87 RISC-V: Include support for kernel stack
Preparation for CONFIG_BUILD_KERNEL=y, which requires that a kernel
stack is allocated for each user process.
2022-03-24 00:15:28 +08:00
Huang Qi
9cffc105c8 arch: Show assigned cpu in dump task
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-23 22:18:15 +08:00
Huang Qi
f09ea317c1 risc-v/qemu-rv: Restore FPU context after context switch
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-23 19:30:04 +08:00
Petro Karashchenko
68902d8732 pid_t: unify usage of special task IDs
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-22 21:22:32 +08:00
Petro Karashchenko
3fff4508c7 netinitialize: call xxx_netinitialize unconditionally
The xxx_netinitialize is defined to a function only if
CONFIG_NET=y and CONFIG_NETDEV_LATEINIT=n.  Otherwise it
is defined to an empty macro.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-19 17:41:33 +08:00
Huang Qi
00efcd3308 arch/risc-v: Merge riscv_getnewintctx into common
And also mask the bits which should be preserved (from ISA spec)

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-19 17:38:18 +08:00
Janne Rosberg
d72a523c00 risc-v/mpfs: add support for ethernet 2022-03-18 17:22:27 +02:00
Janne Rosberg
07aeb12b30 risc-v/common: add call to riscv_netinitialize() 2022-03-18 17:22:27 +02:00
Eero Nurkkala
ec2352a4f9 risc-v/mpfs: usb: fix ep0 read done
USB EP0 reads data from the fifo but doesn't mark the read
done which adds significant delays. Fix this unnecessary
slowdown due to operation timeouts by finishing the read
properly.

Also add a missing function description to the function
mpfs_ep_set_fifo_size().

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-18 22:47:29 +08:00
Ville Juven
15960f25a5 MPFS: Add board_memorymap.h
Move the target specific memory map to a separate file so there is no
need to copy&paste the __xxram_start etc linker symbols to each file
that needs them.

Also add MMU flags for I/O and kernel areas, they will be needed
when the kernel runs with virtual addresses also.
2022-03-18 09:35:00 -03:00
Ville Juven
ade848b60a MPFS: Use linker symbols for heap allocation 2022-03-18 18:20:12 +08:00