According to the ARMv7a/r/m and ARMv8m architecture manuals
The allowed values are
0 Data or unified cache.
1 Instruction cache.
"One CCSIDR is implemented for each cache that can be accessed by the processor. CSSELR selects which Cache Size ID Register is accessible, see c0, Cache Size Selection Register (CSSELR)."
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
When invalidate address is not aligned with cache line,
must align address and flush the cache line.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
NON-primary cpu will invalidate cpu0's cache L2, that will caused cpu0's data mismatch, and then system crash
Signed-off-by: ligd <liguiding1@xiaomi.com>
