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9e5e60ba48
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601 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
9e5e60ba48 esp32s2/esp32c3: Build MCUboot bootloader with Flash Encryption support 2022-01-01 20:37:44 +08:00
Norman Rasmussen
185de258bf Fix preprocessing directives for uart flow control 
commit 58bd873729 had a mix of
`#if defined(X)` and `#ifdef X`, but used `#if X` in its TCSETS ioctl
logic which causes compile warnings.
 2021-12-31 18:51:17 +08:00
Dong Heng
c56c58020a risc-v/esp32c3: SPI flash MTD device uses all flash space 2021-12-31 11:40:23 +08:00
Gustavo Henrique Nihei
74c02fbadb risc-v/esp32c3: Remove unavailable support for ROM Basic Console 
This feature is only available on ESP32 chips.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-12-31 00:56:08 +08:00
Huang Qi
33df35f003 arch/risc-v: Correct epc adjustment with C ISA 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-30 22:54:17 +09:00
chao.an
736add0fe8 arch/backtrace: correct the skip counter 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-30 16:57:40 +08:00
Jukka Laitinen
3beecbe905 risc-v/mpfs: Add MSSIO GPIO pinmap configuration 
Add a pinmap header for mpfs to be able to configure MSSIO GPIOs
This also adds Kconfigs for some different chip/package types of the PolarFire SOC

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-12-30 11:49:00 +08:00
Huang Qi
2de22980e5 arch/risc-v: Refine syscall interface 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-30 11:47:42 +08:00
Norman Rasmussen
091322ba4a Add backtrace to risc-v common sources 2021-12-30 01:30:08 +08:00
Huang Qi
c15195b126 arch/risc-v: Refine riscv_testset.S 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-29 06:06:01 -06:00
Huang Qi
901361be48 arch/risc-v: Move more files to common 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-29 01:19:30 -06:00
Huang Qi
22ae2e0121 arch/risc-v: Refine riscv_fpu.S 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-29 01:19:30 -06:00
chao.an
7ed0b97414 make/allsyms: skip the unnecessary link operation 
For incremental compilation, skip the stage 1 dummy link
operation if nuttx elf has been generated

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-28 23:47:10 -06:00
Xiang Xiao
dd942f0b04 sched/backtrace: Dump the complete stack regardless the depth 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-29 12:09:54 +08:00
Huang Qi
e75321e61c arch/risc-v: Move riscv_blocktask.c to common 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-28 11:32:15 -06:00
Norman Rasmussen
934a79736a Use userspace chosen channel numbers when starting bl602 pwm 
commit 2889315c20 added support for pwm
but didn't read the channel numbers provided by user-space. They should
be, otherwise it's not possible to start a sub-set of channels that are
not the first "n" channels.
 2021-12-28 06:27:51 -06:00
Huang Qi
d71cfc178a arch/risc-v: Remove unneeded kconfigs 
CONFIG_RV32IM_HW_MULDIV can be safely removed since this behavior is
controlled by M extension.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-28 05:02:42 -06:00
Norman Rasmussen
1e2f067181 pwm: add option to break the loops when using multiple PWM channels 
commit 7354ab187e added an option to break
the loops when using multiple PWM channels to arm pwm drivers. This adds
the same support to the risc-v pwm drivers.
 2021-12-28 03:01:27 -06:00
Huang Qi
c2e8c92b25 arch/risc-v: Refine Toolchain.defs 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-28 00:30:10 -06:00
chao.an
a42aa8415d compile/flags: add FRAME_POINTER into Toolchain.defs 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-27 22:31:27 -06:00
Petro Karashchenko
3ccb657dc2 nuttx: remove space befone newline in logs 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-27 21:01:19 -06:00
Eero Nurkkala
3394dca826 risc-v/opensbi: Make.defs: use a wildcard for file listing 
The source directory contents of the OpenSBI directory lib/sbi may be
listed with a one-line wildcard. This makes the Make.defs file look
simpler. The rest of the files need to be picked one at a time.

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-12-23 02:42:09 -06:00
Eero Nurkkala
b128ce334f mpfs: introduce OpenSBI 
OpenSBI may be compiled as an external library. OpenSBI commit d249d65
(Dec. 11, 2021) needs to be reverted as it causes memcpy / memcmp to
end up in the wrong section. That issue has yet no known workaround.

OpenSBI may be lauched from the hart0 (e51). It will start the U-Boot
and eventually the Linux kernel on harts 1-4.

OpenSBI, once initialized properly, will trap and handle illegal
instructions (for example, CSR time) and unaligned address accesses
among other things.

Due to size size limitations for the mpfs eNVM area where the NuttX
is located, we actually set up the OpenSBI on its own section which
is in the bottom of the DDR memory. Special care must be taken so that
the kernel doesn't override the OpenSBI. For example, the Linux device
tree may reserve some space from the beginning:

  opensbi_reserved: opensbi@80000000 {
      reg = <0x80000000 0x200000>;
      label = "opensbi-reserved";
  };

The resulting nuttx.bin file is very large, but objcopy is used to
create the final binary images for the regions (eNVM and DDR) using
the nuttx elf file.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-12-22 20:48:12 -06:00
Eero Nurkkala
491ae6cc53 mpfs: cache: assign ways to L2 zero device 
Assign ways to L2 zerodevice. L2 zero device is used for
the scratchpad functionality. The area may be used for the
harts communicating to each other.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-12-22 20:48:12 -06:00
chao.an
362fe2c6f8 arch/risc-v: enhance the task dump 
add irq stack information
add cpu loading

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-22 11:46:02 -03:00
ChenWen
6d165506d5 risc-v/esp32c3: Initialize rtc and peripheral parameters by default when chip starts 2021-12-21 10:03:58 -03:00
Gustavo Henrique Nihei
c471f0fe96 risc-v/esp32c3: Remove deprecated note about Flash Detect feature 
Flash Detect option is already available on esptool.py installed via pip

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
1c8e84b341 risc-v/esp32c3: Add Secure Boot support on top of MCUboot 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-12-21 07:02:40 -06:00
Petro Karashchenko
3e76c3266e assert: unify stack and register dump across platforms 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-20 00:02:12 -03:00
Petro Karashchenko
67d8a82393 Kconfig: fix non-string default values uniformity 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-20 00:10:57 +01:00
xiewenxiang
b1d051b651 riscv/esp32c3: Initialize the BLE Mac 2021-12-16 22:31:02 -03:00
chao.an
b11833cbba arch/assert: flush the syslog before stack dump 
flush the syslog before stack dump to avoid buffer overwrite

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-15 12:00:35 -06:00
Petro Karashchenko
51a2db6ffc Kconfig: improve uniformity 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-14 07:32:48 -06:00
Petro Karashchenko
af614ac77d tls: restore C89 compatibility for TLS 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-13 21:14:53 -06:00
chao.an
c2fd66bfab arch/arm/risc-v/xtensa: add support of all symbols for debugging 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-13 08:31:13 -06:00
chao.an
89e2f00dad arch/assert: fix the stack dump overflow 
[ EMERG] kasan_report: kasan detected a read access error, address at 0x3c24fca8, size is 4
[ EMERG] up_assert: Assertion failed at file:kasan/kasan.c line: 104 task: init
[ EMERG] backtrace|10:  0x2c334666 0x2c35f0d6 0x2c359ef6 0x2c35f830 0x2c360ed4 0x2c3615c0 0x2c324e0c 0x2c30a168
[ EMERG] up_registerdump: R0: ffffffff R1: 00000004 R2: ffffffff R3: ffffffff
[ EMERG] up_registerdump: R4: 3c20d4f0 R5: 2c35acd5 R6: 00000000 FP: 3c24fae8
[ EMERG] up_registerdump: R8: 3c20d504 SB: ffffffff SL: 2c413e7c R11: 2c411eb8
[ EMERG] up_registerdump: IP: 00000002 SP: 3c24fae8 LR: 00000003 PC: 2c35f0d6
[ EMERG] up_registerdump: xPSR: 61010000 BASEPRI: 000000e0 CONTROL: 00000004

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-13 01:43:18 -06:00
lupyuen
2a87b37a69 riscv/bl602: Swap SPI MISO and MOSI 2021-12-12 20:40:49 -06:00
Huang Qi
8ce3337e85 arch/risc-v: Implement TLS support 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-12 10:19:00 -06:00
Xiang Xiao
6357523892 arch: Add _wchar_t typedef like other basic types 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-09 16:57:23 +09:00
Huang Qi
63ab2f4308 arch/risc-v: Introduce basic support for qemu rv32 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-07 23:28:33 -06:00
chao.an
437a30d117 arch/tcbinfo: fix build break if task name disabled 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-06 00:47:58 -06:00
Dong Heng
698f1f76ff risc-v/esp32c3: Refactor SPI Flash to support umask interrupt when R/W/E SPI Flash 
This can fix BLE assert when erase SPI Flash.
 2021-12-06 13:13:11 +09:00
Xiang Xiao
a0990ee416 arch: Remove the duplicated up_tls_info implementation 
Define up_tls_info in arch/arch.h directly if the general one isn't suitable

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-05 20:59:53 -06:00
Xiang Xiao
19e5ee6ce0 arch: Remove FILE dump code from _up_dumponexit 
since the kernel build can't access the userspace memory
inside other process directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-06 11:23:58 +09:00
Xiang Xiao
b65c7c26cf arch: Dump task name through tcb_s::name instead of argv[0] 
since argv is defined in task_tcb_s not tcb_s

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-01 16:04:15 +01:00
Abdelatif Guettouche
251b8a3445 esp32xx_rtc: Include "clock/clock.h" to have a declaration of 
g_basetime.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-26 15:23:47 -03:00
Abdelatif Guettouche
af11cf6cd1 esp32xx_rtc.c: Fix a duplicated assignment. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-26 15:23:47 -03:00
Dong Heng
66023da10c risc-v/esp32c3: Refactor ADC calibration 
Use calibration parameters from efuse rather than self-calibration.
 2021-11-26 15:23:24 -03:00
Jani Paalijarvi
4dfd3c9160 arch/riscv: Add ARCH_HAVE_SPI_CS_CONTROL for mpfs 
Make it possible to override SPI CS function in board logic

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-11-24 06:50:32 -06:00
Lee Lup Yuen
6e68d55f8a Fix GPIO output 2021-11-24 06:48:50 -06:00