Commit Graph

18988 Commits

Author SHA1 Message Date
Ville Juven
a132fa38f6 riscv/bl602/chip.h: Add assembly guards for standard includes. 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
779fc6461f riscv/esp32c3: Use the common exception handler.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
e8134a8b57 riscv/riscv_exception_common.S: Allow chips to define the exception
section.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
875dd46207 riscv/riscv_exception_commin.S: Don't call riscv_hartid in single core
mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-10 08:27:10 +08:00
Huang Qi
9284770f75 arch/risc-v: Move epc adjustment to riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-10 00:52:04 +08:00
Huang Qi
833211680a arch/risc-v: Attach exception handler in common place
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-10 00:52:04 +08:00
Huang Qi
36bc8d2131 arch/risc-v: Align prototype of riscv_exception with xcpt_t
Thus we can attach it to irq handler without any cast.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-10 00:52:04 +08:00
Xiang Xiao
c235c0fa43 boards/lx_cpu: Enable up_perf API
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-08 21:02:13 -03:00
Xiang Xiao
1f7b49d700 boards/nucleo-h743zi2: Enable up_perf API
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-08 21:02:13 -03:00
Huang Qi
c6942b68d5 arch/risc-v: Add handler for misaligned load/store
Some risc-v based chips don't support unaligned data access,
it will trigger a exception and then lead to crash.

In this patch, we handle the misaligned access by software to make
system run continue.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-08 23:27:07 +08:00
chao.an
8d66dbc068 arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-08 14:28:41 +09:00
Huang Qi
b6cf1ac662 arch/riscv: Minor style change and text correction
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-08 01:07:06 +08:00
Huang Qi
4ebc581c73 esp32c3: Simplify irq dispatch logic
ESP32C3 use customized irq encoding so it's hard to share further code
with other risc-v based chips, in this patch, we keep the exception
number definition with risc-v spec.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-07 18:16:35 +02:00
Ville Juven
d38b4965f8 MPFS: Prepare support for S-mode
- Access to PLIC via S-mode registers
- Access to IRQs via S-mode registers / definitions
- Initialize S-mode registers upon boot
- Initialize per CPU area before nx_start

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
thus S-mode is not usable as is, yet.
2022-04-07 21:55:36 +08:00
Xiang Xiao
3a26cf6a02 arch/risc-v: Remove the unnecessary inclusion of board header files
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-07 11:25:12 +03:00
Jiuzhu Dong
d87cf8d4ca fs/poll: change format for type pollevent_t
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-04-07 12:14:06 +08:00
Huang Qi
53fef8d9c4 arch/risc-v: Replace riscv_fault with riscv_exception
Remove riscv_fault since its code is duplicated with riscv_exception,
and there are textual excpetion reason in riscv_exception.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-06 22:48:46 +08:00
yinshengkai
db012687f9 arch/sim: support simulator keyboard devices 2022-04-06 15:26:57 +03:00
Alan C. Assis
1090e1a8ea xtensa/esp32: Add support to TWAI/CANBus controller 2022-04-06 15:09:46 +03:00
zhuyanlin
6a761ff087 arch:tcbinfo: update tcbinfo as xcpcontext update
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-04-05 13:33:00 +02:00
Ville Juven
6c22e2894c RISC-V: Fix usage of static_assert in riscv_percpu.c
There is no alias for struct riscv_percu_s
2022-04-04 22:44:25 +08:00
Ville Juven
7db356e720 RISC-V: Fix file name of riscv_dispatch_syscall 2022-04-04 22:44:18 +08:00
Petro Karashchenko
d08fbca679 nuttx: unify FAR attribute usage across the code
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-04-04 21:32:58 +08:00
Abdelatif Guettouche
f527abc324 arch/xtensa: Build the xtensa_tcbinfo.c file for S2 and S3.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-04 21:25:47 +08:00
Xiang Xiao
bf48c6d4a8 arch/riscv: Rename SCRATCH_HARTID_OFFSET to RISCV_PERCPU_HARTID_OFFSET
and fix the typo error

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-04 08:22:08 +03:00
Petro Karashchenko
9b7f9867aa arch/risc-v: use STACK_FRAME_SIZE for in S-mode syscall asm
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-04-04 12:05:53 +08:00
Michael Jung
e3926ecb16 stm32u5: stm32_stdclockconfig fixes
Fix stm32_stdclockconfig for stm32u585xx to the extend that the
B-U585I-IOT02A board's clock tree can be configured.  This board uses
the MSIS as PLL1's input clock and the LSE to autotrim the MSIS.
2022-04-03 23:20:03 +03:00
zhanghongyu
451c53daa4 usrsock: Move event field to usrsock_message_common_s
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2022-04-03 11:38:50 +09:00
wangbowen6
bcb2530b18 arm/chip: add backtrace support for all chips that support thumb instruction set.
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-04-03 00:22:57 +08:00
raiden00pl
b487101b87 stm32: add support for up_perf 2022-04-02 10:34:35 -03:00
Xiang Xiao
27c80f2586 arch/riscv: Rename g_scratch to g_percpu
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
e959775397 arch/riscv: Access [m|s]scratch through CSR_SCRATCH macro
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
be2fee7d6e arch/riscv: Rename riscv_exception_macros.S to riscv_macros.S
since macro defined in this file is also used in the normal context

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
79aca28bd7 arch/riscv: Remove riscv_sbi.c since it doesn't exist
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
629d9969dd arch/riscv: Rename riscv_syscall_dispatch to riscv_dispatch_syscall
follow other function naming(e.g. riscv_dispatch_irq)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
7a209e6ee8 arch/riscv: Align the macro definition in csr.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Abdelatif Guettouche
11807abd4e arch/xtensa: Add xtensa_tcbinfo struct that contains helpful offsets.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-02 10:39:14 +08:00
Ville Juven
71ced1f1a9 RISC-V: Implement skeleton for a per CPU structure
It might be useful to store things in memory per CPU. The tricky part
is that all CPUs run the same code and see the same memory, so some
kind of centralized access is required.

For now, the structure contains the hart id.

Access to the structure elements is provided via sscratch, which is
unique for every hart!
2022-04-01 16:19:42 -03:00
Ville Juven
c15b6701ce RISC-V: Implement option to run NuttX in supervisor mode (S-mode)
- Add config "ARCH_USE_S_MODE" which controls whether the kernel
  runs in M-mode or S-mode
- Add more MSTATUS and most of the SSTATUS register definitions
- Add more MIP flags for interrupt delegation
- Add handling of interrupts from S-mode
- Add handling of FPU from S-mode
- Add new context handling functions that are not dependent on the trap
  handlers / ecall

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
      thus S-mode is not usable as is, yet.
2022-04-01 16:19:42 -03:00
Gustavo Henrique Nihei
c37474b5bd risc-v/esp32c3: Fix regression on IRQ handling for ECALL instruction
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-04-01 15:29:14 -03:00
Gustavo Henrique Nihei
35009c5d4d sim: Fix init of static C++ constructors when using glibc >= 2.34
glibc 2.34 changed the dynamic linker behavior during the startup
process, which makes the previous "__init_array_start" replacement trick
non-effective.
Now the dynamic linker parses the constructors/destructors information
from the DYNAMIC segment of the program.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-04-01 23:10:53 +08:00
chao.an
253562f11f arch/xtensa: add syscall note support in the flat build
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-01 21:04:51 +08:00
Jiuzhu Dong
0a111b7c96 fs/rpmsgfs: fix bug about using uninit variable "times"
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-04-01 21:02:08 +08:00
Petro Karashchenko
870ca12146 arch/risc-v: get wider visibility for arch instruction macros
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-04-01 10:31:24 +08:00
Ville Juven
e6d6734db2 ARCH_ADDRENV: Add guard against mis-configuration
When process a is switched to process b, the address environment is
swapped with a call to group_addrenv(). The stack upon entry will be
a's, and upon exit b's. This will fail, so a neutral stack is required,
either a kernel stack or an IRQ stack.

Infrastructure for an IRQ stack is already in place, so give a hint
that an interrupt stack should be provided if address environments
are enabled.
2022-04-01 02:02:10 +08:00
Petro Karashchenko
44ee76dcbd arch/risc-v: fix ARCH_RV32 offset for the stub lookup table calculation
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-31 19:34:52 +08:00
Petro Karashchenko
36b0b95eb1 arch/risc-v: include csr.h indirectly through nuttx/irq.h
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-31 19:34:52 +08:00
Petro Karashchenko
5d856971db arch/risc-v: move REGLOAD/REGSTORE macro to riscv_internal.h
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-31 19:34:52 +08:00
Huang Qi
264e39e121 arch/risc-v: Remove unneeded group_addrenv call which handled by riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 19:33:08 +08:00
Huang Qi
f72ca3db5c arch/risc-v: Dont' disable/enable irq in riscv_doirq
Since these codes added to all chips but not fully tested,
so we should changd this behavior.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 19:33:08 +08:00