Initial DMA support for STM32H7
arch/arm/src/stm32h7: SPI DMA mode
arch/arm/src/stm32h7/chip/stm32h7x3xx_memorymap.h: add base addresses for D1, D2 and D3 domain; use 2 bytes to specify memory region
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c: add D1 domain core prescaler configuration
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Improvements for H7 towards the DMA support
arch/arm/include/stm32h7/stm32h7x3xx_irq.h: fix typos and rename DMA1/2 irq names to match those from other STM32
arch/arm/src/stm32h7/chip/stm32_bdma.h: add auxiliary definitions
arch/arm/src/stm32h7/chip/stm32_dma.h: cosmetic changes
arch/arm/src/stm32h7/chip/stm32_dmamux.h: add auxliary definitions and fix some typos
arch/arm/src/stm32h7/chip/stm32_mdma.h: add auxliary definitions and fix some typos
arch/arm/src/stm32h7/chip/stm32h7x3xx_dmamux.h: add DMAMAP definitions for MDMA, DMA1, DMA2 and BDMA
arch/arm/src/stm32h7/chip/stm32h7x3xx_memorymap.h: fix AHB1 base adresses and add some address blocks
arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h: fix some definitions to match other STM32 ports
arch/arm/src/stm32h7/stm32_allocateheap.c: use SRAM from D2 domain (SRAM123) for now
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c: enable clock for MDMA and BDMA
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Fixed coding standard error in several files. Use of while( is incorrect; a space is required between while and (. Also ran tools/nxstyle and fix thoses complaints as well in most files.
Changes to comply with coding standard. Mostly focused on files with missing space after keyword in if(, switch(, and for(. Offending files also got changes to comply with tools nxstyle. If there were logs of nxstyle complaints, the file also got a taste of tools/indent.sh. Still need to fix occurrences of while( with missing space. There are a lot of them.
Master
arch/arm/src/stm32f0l0: SPI support for F0
arch/arm/src/stm32f0l0/Kconfig: L0 parts should select STM32F0L0_STM32L0
arch/arm/src/stm32f0l0/hardware: unify names for ADC/DAC/DMA/CAN
drivers/wireless/lpwan/sx127x/sx127x.c: return immediately when ISR0 is called but sx127x is not initialized
configs/nucleo-f091rc: support for sx127x
configs/nucleo-l073rz: cosmetics
configs/b-l072z-lrwan1/include/board.h: use HSI as default clock source and fix typo in SPI1 pins
Approved-by: GregoryN <gnutt@nuttx.org>
configs/launchxl-cc1312r1: Correct DIOs used to provide the UART0 serial console.
Status: Board boots to NSH prompt now. But I am not getting serial input. Things are probably not very stable in general.
arch/arm/src/tiva/cc13xx/cc13xx_prcm.c: Fix reverse bit modification: Set the bit to enabled clocking, clear the bit to dissable clocking.
arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.c: Use correct index for determining if this the SERIAL or PERIPH power domain.
Squashed commit of the following:
configs/: The few configurations that formerly set CONFIG_NFILE_DESCRIPTORS=0 should not default, rather they should set the number of descriptors to 3.
fs/: Remove all conditional logic based on CONFIG_NFILE_DESCRIPTORS == 0
tools/: Tools updates for changes to usage of CONFIG_NFILE_DESCRIPTORS.
syscall/: Remove all conditional logic based on CONFIG_NFILE_DESCRIPTORS == 0
libs/: Remove all conditional logic based on CONFIG_NFILE_DESCRIPTORS == 0
include/: Remove all conditional logic based on CONFIG_NFILE_DESCRIPTORS == 0
drivers/: Remove all conditional logic based on CONFIG_NFILE_DESCRIPTORS == 0
Documentation/: Remove all references to CONFIG_NFILE_DESCRIPTORS == 0
binfmt/: Remove all conditional logic based on CONFIG_NFILE_DESCRIPTORS == 0
arch/: Remove all conditional logic based on CONFIG_NFILE_DESCRIPTORS == 0
net/: Remove all conditional logic based on CONFIG_NFILE_DESCRIPTORS == 0
sched/: Remove all conditional logic based on CONFIG_NFILE_DESCRIPTORS == 0
sched/Kconfig: CONFIG_NFILE_DESCRIPTORS may no longer to set to a value less than 3
configs/: Remove all settings for CONFIG_NFILE_DESCRIPTORS < 3
sched/init/nx_bringup.c: Fix a naming collision.
sched/init: Rename os_start() to nx_start()
sched/init: Rename os_smp* to nx_smp*
sched/init: Rename os_bringup to nx_bringup
sched/init: rename all internal static functions to begin with nx_ vs os_
Squashed commit of the following:
Trivial, cosmetic
sched/, arch/, and include: Rename task_vforkstart() as nxtask_vforkstart()
sched/, arch/, and include: Rename task_vforkabort() as nxtask_vforkabort()
sched/, arch/, and include: Rename task_vforksetup() as nxtask_vfork_setup()
sched/: Rename notify_cancellation() as nxnotify_cancellation()
sched/: Rename task_recover() to nxtask_recover()
sched/task, sched/pthread/, Documentation/: Rename task_argsetup() and task_terminate() to nxtask_argsetup() and nxtask_terminate(), respectively.
sched/task: Rename task_schedsetup() to nxtask_schedsetup()
sched/ (plus some binfmt/, include/, and arch/): Rename task_start() and task_starthook() to nxtask_start() and nxtask_starthook().
arch/ and sched/: Rename task_exit() and task_exithook() to nxtask_exit() and nxtask_exithook(), respectively.
sched/task: Rename all internal, static, functions to begin with the nx prefix.
arch/arm/src/samv7/sam_emac.c: Fixes rxdesc index logic to handle Buffer Not Available (BNA) condition.
If a SOF is found, but no EOF, don't move past the frame. Instead, keep the index at the SOF buffer until the rest of the data is written.
This fixes a receiver lockup condition where the peripheral and this driver get out of sync with there head pointers. In this case the driver has moved past buffers it owns, without clearing ownership, which results in the peripheral and driver in a deadlock with each other.
Approved-by: GregoryN <gnutt@nuttx.org>
2./arch/arm/src/samv7/sam_qspi.c compiling error when set CONFIG_SAMV7_QSPI_DLYBCT
3. fix compiling error when set CONFIG_BOARDCTL_IOCTL/CONFIG_BOARDCTL_UNIQUEID
Improvements in STM32 ADC, PWM and TIM
arch/arm/src/stm32/chip/stm32_adc_v2.h: missing T1TRGO2 for JEXTSEL
arch/arm/src/stm32/stm32_adc: configure injected channels external trigger when ADC enabled
arch/arm/src/stm32/stm32_adc: update injected conversion queue of context after configuration
arch/arm/src/stm32/stm32_adc: fix sample time configuration for channels. The array index for channels was missing
arch/arm/src/stm32/stm32_adc: support for offset configuration
arch/arm/src/stm32/stm32_pwm: fix TRGO/TRGO2 configuration
arch/arm/src/stm32/stm32_pwm: support for advanced timers channel 5 and 6
Approved-by: GregoryN <gnutt@nuttx.org>
Improvements for STM32 PWM
arch/arm/src/stm32/stm32_pwm: fix polarity and IDLE state configuration for advanced timer PWM
include/dsp.h: raise error if math.h not present
Approved-by: GregoryN <gnutt@nuttx.org>
arch/arm/src/tiva/hardware: Add CC13xx SMPH and AUX SMPH header files. Still need DDI0 OSC header file for CC13x0 compilation.
arch/arm/src/tiva/cc13xx: A few changes toward getting the launchxl-cc1310/nsh configuration to build
Squashed commit of the following:
confgs/launchxl-cc1310: Add board support for the LaunchXL-CC1310. This is a work in progress and does not yet build error free.
arch/arm/src/tiva/cc13xx: cc13x0_trim.c now compiles; Make xxx_rom.h header files conform a little more closely to the NuttX coding style.
arch/arm/src/tiva/cc13xx: CC13x2 (V1 and V2) rom.c files now build with no errors or warnings. Still have to work through the CC13x0 version.
arch/arm/src/tiva/hardware: Add CC13x0/CC13x2_CC26x2 AON BATMON register definition header file.
arch/arm/src/tiva/cc13xx: A little more progress converting TI DriverLib ROM code to NuttX coding style. Lots of possibilities for breakage here!
arch/arm/src/tiva/cc13xx: Remove functions from cc13x._rom.c that are defined from ROM access in cc13x._rom.h; Add prototypes in cc13x._rom.h for functions in cc13x._rom.c that are not defined in cc13x._rom.h.
arch/arm/src/tiva/cc13xx: Remove some dangling whitespace at the end of lines.
arch/arm/src/tiva/cc13xx: Second (and final) round of name changes to get ROM function-like defines consistent with NuttX coding standard
arch/arm/src/tiva/cc13xx: Fix a few errors in last big name conversion.
arch/arm/src/tiva/cc13xx: First round of name changes to get ROM function-like defines consistent with NuttX coding standard
arch/arm/src/tiva/cc13xx: Remove ROM_ prefix from function-like defines.
arch/arm/src/tiva/hardware: Completes the CC13x2 AUX SYSIF header file.
arch/arm/src/tiva/hardware: Progress on the CC13x2 AUX SYSIF header file. Almost complete.
arch/arm/src/tiva/hardware: Port needs aux_sysif.h header file.
arch/arm/src/tiva/cc13xx/cc13x0_rom.h: Fix a typo
arch/arm/src/tiva/cc13xx: More changes to TI DriverLib ROM header files for NuttX coding standard.
arch/arm/src/tiva/cc13xx: Convert some (but not all) TI DriverLib ROM function names to NuttX coding standard. More to be done.
arm/src/tiva/cc13xx: ROM header files: missed a couple of conversions of sructure field names to lower case (vs CamelCase).
arm/src/tiva/cc13xx: ROM header files: type'ed names must be lower case per coding standard (not upper case); structure field names must be lower case per coding standard (not CamelCase).
arch/arm/src/tiva/cc13xx: Trim logic needs to include matching ROM DriverLib interface header file.
arch/arm/src/tiva/cc13xx: Add ROM DriverLib header files. Do not yet fully conform to the NuttX coding style.
arch/arm/src/tiva/cc13xx: Trim code now kind of looks like NuttX code. But does not yet compile.
arch/arm/src/tiva/cc13xx: The first few, feeble steps toward getting the overall trim files compatible with the requirements of the NuttX coding standard.
arch/arm/src/tiva/cc13xx: Replace last of TI hardware access macros with NuttX hardware access macros.
arch/arm/src/tiva/cc13xx: Change TI HWREGB to NuttX getreg8 or putreg8 in trim logic.
arch/arm/src/tiva/cc13xx: Change TI HWREGBITW to NuttX getreg32/putreg32 sequence in trim logic.
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h: Completes the DDIO OSC header file.
cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h: Updated, but still not finished.
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h: Add DDI0 OSC header file. Still a work in progress. Does not yet conform to the NuttX coding standard.
Change _M and _S to _MASK and _SHIFT.
Some minor improvements.
Clean up typos in some comments.
Run all new files against tools/indent.sh
arch/arm/src/tiva/cc13xx: Bring in trim files from SDK. Convert to C-style comments, lowercase hex contants. Remove Windows-style line endings.
I still observe data abort crash if I compile the code with optimization enabled.
The next steps are to investigate the optimization issue and add Watchdog module. Currently, NSH does not run for a long time ;)
arch/arm/src/am335x/am335x_irq.c: Correct interrupt processing routine
configs/beaglebone-black/nsh/defconfig: Enable debug compilation options. Otherwise data abort crash is observed
arch/arm/src/am335x/am335x_lowputc.c and arch/arm/src/am335x/chip/am335x_uart.h: UART-related cosmetic changes
arch/arm/src/am335x/am335x_timerisr.c: Make sure that Timer 1 interrupts are disabled before any access to peripheral registers
stm32f0l0: SPI and GPIO EXTI support
arch/arm/src/stm32f0l0: add support for GPIO EXTI
configs/nucleo-l073rz: support for nrf24l01
configs/b-l072z-lrwan1/include/board.h: add note about onboard Murata CMWX1ZZABZ-09 module and definitions for available peripherals
Approved-by: GregoryN <gnutt@nuttx.org>
Masayuki Ishikawa reports that this commit breaks ALL PROTECTED mode builds.
It violates the basic requirements of the use of the MPU in protected mode. Those basic requirements are:
1. The MPU region must be aligned to the base address of the memory region being mapped (it may NEVER extend before the memory region). That is, the following MUST always be zero:
(base & ((1 << l2size) - 1))
2. The MPU region must never extend beyond the end of the memory region. That is, the following must be true:
size >= (1 << l2size)
This reverts commit 8b63d02309.
Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
Many small changes related to coding style.
Author: Petro Karashchenko <petro.karashchenko@gmail.com>
configs/beaglebone-black: Adds initial support for the BeagleBone Black board.
arch/arm/src/am335x: Adds initial support for the TI AM355x family.
Fix lc823450 start
* arch/arm/src/lc823450: Use CONFIG_STACK_COLORATION instead of CONFIG_DEBUG_STACK
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Fix go_os_start() in lc823450_start.c
I found a bug in go_os_start() that it returns immediately
because it does not compare r1 to zero. This commit fixes
this bug. Also, this commit fixes its description.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: GregoryN <gnutt@nuttx.org>
Squashed commit of the following:
arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions.
arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0.
arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0.
arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts.
arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls.
arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file.
arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file.
arch/arm/include/stm32f0l0/chip.h: WIP.
arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options.
arch/arm/src/stm32f0l0: Better integrate STM32L0 header files.
nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file.
arch/arm/src/stm32f0l0: Add STM32L0 RCC driver.
arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files.
arch/arm/src/stm32f0l0: Add STM32L0 chip selections.
configs/: Hook new STM32L0 boards into the configuration system.
configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled
configs: add basic support for nucleo-l073rz
configs: add basic support for b-l072z-lrwan1
- Avoids the use of up_aesinitialize() entirely, which resolves dependency problems, because this function does not make sure that an actual hardware aes implementation was made available: each SoC is now responsible to ensure the AES hardware is initialized before first use. This applies to lpc43xx, stm32 and sam34.
- Remove definitions of the NEVER used aes_init and aes_update operations. The new AES API will be more suitable.
- Change the unusual naming in stm32 (avoiding possible naming clashes)
- Change the unusual naming in sam34 (avoiding possible naming clashes)
- Add some FAR to pointers and enforce the 80 col limit in stm32 and sam
Fix lc823450 related
* configs/lc823450-xgevk: Fix IOB params in rndis/defconfig
These prameters work for HTTP audio streaming.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Fix up_allocate_heap() in lc823450_allocateheap2.c
This change fixes heap size and also implements up_addregion().
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: GregoryN <gnutt@nuttx.org>
arch/arm/src/stm32f0l0: Some fixes for a clean build. Still have a problem with lots of error messages coming from kconfig-mconf, but the configuation looks fine. Sometimes kconfig errors are difficult to spot. I would appreciate it anyone can spot the issue.
arch/arm/src/stm32f0l0/hardware: Rename the chip directory to hardware. This will hopefully eliminate some problems that I have seen with the chip include paths not being unique in more complex configuartions.
configs/nucleo-f072rb, configs/nucleo-f091rc, configs/stm32f051-discovery, and configs/stm32f072-discovery: Update for all of the naming changes made in arch/arm/src/stm32f0l0
arch/arm/include/stm32f0l0: Rename stm32f0 to stm32f0l0 to make a speace for STM32 L0. Rename files, functions and defines, removeing the f0_ from the names in order to make them MCU agnostic.
arch/arm/src/stm32f0l0: Rename stm32f0 to stm32f0l0 to make a speace for STM32 L0. Rename files, functions and defines, removeing the f0_ from the names in order to make them MCU agnostic.
arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h: Adjust cloned CC13x9 FCFG1 header file so that it reflects reality.
arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h: Add CC13x0 FCFG1 header file. Initial commit is the same as the CC13x2/CC26x2 FCFG1 header with a few name changes.
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_fcfg1.h: Initial FCFG1 header file for the cc13xx/cc26xx family.
arch/arm/src/tiva: Add GPIO IRQ stubs for clean compile
arch/arm/src/tiva/cc13xx: Add build framework for CC13xx GPIO interrupts. Change prototypes of some GPIO IRQ interfaces so that the function prototype is common between LM3S, LM4F, TM4C, and CC13xx.
Master
configs/nucleo-f334r8: add example for the SPWM generation (custom STM32 PWM usage)
arch/arm/src/stm32/stm32_pwm: fix compilation errors if the upper-half PWM logic is not enabled
include/nuttx/drivers/pwm.h: remove dependency on CONFIG_PWM for the upper-half PWM header. This allows compilation for the lower-level PWM drivers even if the upper-half PWM logic is not used.
arch/arm/src/stm32/stm32_tim.c: fix compilation error if there is no TIM8
configs/nucleo-f334r8/highpri: remove the upper-half ADC from configuration
configs/nucleo-f302r8/highpri: remove the upper-half ADC from configuration
configs/stm32f429i-disco/highpri: remove the upper-half ADC from configuration
Approved-by: GregoryN <gnutt@nuttx.org>
arch/arm/src/tiva: Add CC13xx GPIO driver plus various fixes for clean compilation.
arch/arm/src/tiva/ and configs/launchxl-cc1312r1: Make type of the GPIO pin configuration an abstract type so that CC13xx MCUs can share the same GPIO function prototypes and usage model.
arch/arm/src/tiva: Add CC13xx logic to enable power domains needed by peripherals and to enable clocking to peripherals.
arch/arm/src/tiva: Rename some header files so that they are unique in order to avoid including the wrong file. Fix various compile issues found during some initial trial builds.
arch/arm/src/tiva: Add CC13xx clock enable and power enable macros that are backward compatible with lm/tm4c macros.
Improvements in STM32 ADC
arch/arm/src/stm32/stm32_adc.c: start conversion on startup is now possible if TIM triggering selected. This can be useful to start ADC TIM conversion for ADC IPv2 when opening ADC device.
arch/arm/src/stm32/stm32_adc.c: fix compilation errors for chips with one ADV TIM
configs/nucleo-f303re: refresh ADC example
configs/nucleo-f334r8: refresh ADC example
Approved-by: GregoryN <gnutt@nuttx.org>
