Commit Graph

25751 Commits

Author SHA1 Message Date
David Sidrane
70f2b47a0d Fix the Value Line adc IRQ number selection 2016-05-31 14:54:04 -10:00
Gregory Nutt
6eac8bf28d Update some comments 2016-05-31 17:31:15 -06:00
Gregory Nutt
15810946b1 Update some comments 2016-05-31 17:28:02 -06:00
Gregory Nutt
8ca5daf2b3 Changes from review of last PR 2016-05-31 15:52:56 -06:00
Gregory Nutt
213c1900b0 Merged in neilh20/anuttx/bugfix_rtcalarm (pull request #36)
The rtc examples "alarm 10" now runs to completion
2016-05-31 15:43:36 -06:00
neilh10
639410849e alarm 10 now runs to completion 2016-05-31 14:17:52 -07:00
Gregory Nutt
b80bf20374 Fix another bungle in the last commit 2016-05-31 11:52:40 -06:00
Gregory Nutt
b5c37f0270 LP43: Add support for more than 63 interrupts (not currently needed) 2016-05-31 11:42:21 -06:00
Gregory Nutt
828c898a80 LP43: Add support for more than 63 interrupts (not currently needed) 2016-05-31 11:39:51 -06:00
neil H
af9ef88a8a Merged nuttx/nuttx into master 2016-05-31 09:10:30 -07:00
Gregory Nutt
4f81a60ef6 Add a NAN test on 'x' in asin function of lib_asin.c. Suggested by Pierre-noel Bouteville. 2016-05-31 06:31:04 -06:00
Gregory Nutt
f06a06952f LPC43xx: 1KB is 1024, not 1025. Noted by phreakuencies. 2016-05-31 06:22:10 -06:00
Gregory Nutt
6940fe9655 Update ChangeLog 2016-05-30 13:31:19 -06:00
Pierre-noel Bouteville
39c1e3aba2 Allow to not use all channet in a lower part of PWM 2016-05-30 11:58:22 -06:00
Gregory Nutt
5ef3e3e215 Replace confusing references to uIP with just 'the network' 2016-05-30 11:52:07 -06:00
Gregory Nutt
50d640a102 Typo fix 2016-05-30 09:51:46 -06:00
Gregory Nutt
9b4cec9228 Replace confusing references to uIP with just 'the network' 2016-05-30 09:51:15 -06:00
Gregory Nutt
44353f320c Replace confusing references to uIP with just 'the network' 2016-05-30 09:37:34 -06:00
Gregory Nutt
4f208600aa Replace confusing references to uIP with just 'the network' 2016-05-30 09:31:44 -06:00
Gregory Nutt
f65616f872 Replace confusing references to uIP with just 'the network' 2016-05-30 09:16:32 -06:00
Gregory Nutt
22044edd12 Merged in ziggurat29/nuttx/stm32l4_i2c_lcd_mjkdz_001 (pull request #35)
correct bugs and add enhancements to pcf8574 lcd backpack driver
2016-05-29 14:02:39 -06:00
ziggurat29
bb7a579681 fleshed out rest of fileops interface; read now takes into consideration current file position (so the display can be read in multiple operations, and indiate EOF correctly), seek (really just to facilitate rewind), and unlink (to facilitate dropping from system at runtime). 2016-05-29 14:53:37 -05:00
Manuel Stühn
5c6c7bd60d Fix recently introduced problem with build of ADC driver with analog debug enabled. 2016-05-29 13:45:40 -06:00
Gregory Nutt
815bea77ea i.MX6: Update ECSPI header file 2016-05-29 10:23:06 -06:00
ziggurat29
4643fcdfd8 correct logic hazard in latch and load nybble; was transitioning control lines at the same time as enable, causing spurious behaviour on less-tolerant displays
improve timing parameters in init sequences for better display compatibility

correct (row,col) -> address calculation; affects 4-line displays

update comments in header and readme
2016-05-29 11:09:00 -05:00
Gregory Nutt
fa10927dcc Stefan Kolb's change to the SAMV7 Oneshot Timer (commit d44ecbcfbb) should also be applied to the SAM3/4 oneshot time since the drivers are identical. Here are the commit commits from Stefan's original change:
"This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started.

"In my fix I use the freerun count value to determine if at least one tick passed since the start of the timer and thus if the value of the oneshot counter is correct. I also tried to use the function up_timer_gettime(…) to achieve this but, at least if compiled with no optimization the problem vanishes without using the value of the function, the function call takes too long.

"Another problem treated in the fix is that if the oneshot timer/counter is canceled, we only know the remaining time with a precision of USEC_PER_TICK microseconds. This means the calculated remaining time is between 0 and USEC_PER_TICK microseconds  too long. To fix this I subtract one tick if the calculated remaining time is greater than one tick and otherwise set the remaining time to zero. By doing so the measured times are much more precise as without it."
2016-05-29 08:25:41 -06:00
Gregory Nutt
9071a22c28 Cosmetic fix to spacing 2016-05-29 08:25:05 -06:00
Gregory Nutt
0b17b1feb3 i.MX6: Add ECSPI configuration logic. Updated ECSPI header files 2016-05-28 17:42:29 -06:00
Gregory Nutt
16cb0a9205 i.MX6: Divide ported i.MX1/L CSPI header file into two header files 2016-05-28 17:10:58 -06:00
Gregory Nutt
13b53d87a9 i.MX6: Add ECSPI header file 2016-05-28 12:23:05 -06:00
Gregory Nutt
ceaad0f339 Upate TODO list 2016-05-28 12:22:35 -06:00
Gregory Nutt
607dd3bec5 Spell check TODO list 2016-05-27 14:44:39 -06:00
Gregory Nutt
9d475e4f48 Merged in K-man23/nuttx/stm32f411-fix (pull request #34)
Add support for SPI 4 and 5 on stm32f411 chips
2016-05-27 13:15:21 -06:00
Konstantin Berezenko
5c6cd17d46 Add support for SPI 4 and 5 on stm32f411 chips 2016-05-27 11:08:18 -07:00
Gregory Nutt
7d538d19bf Costmetic changes to comments and style 2016-05-27 10:53:27 -06:00
Gregory Nutt
b4354cf130 Stefan Kolb's change to the SAMV7 Oneshot Timer (commit d44ecbcfbb) should also be applied to the SAMA5 oneshot time since the drivers are identical. Here are the commit commits from Stefan's original change:
"This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started.

"In my fix I use the freerun count value to determine if at least one tick passed since the start of the timer and thus if the value of the oneshot counter is correct. I also tried to use the function up_timer_gettime(…) to achieve this but, at least if compiled with no optimization the problem vanishes without using the value of the function, the function call takes too long.

"Another problem treated in the fix is that if the oneshot timer/counter is canceled, we only know the remaining time with a precision of USEC_PER_TICK microseconds. This means the calculated remaining time is between 0 and USEC_PER_TICK microseconds  too long. To fix this I subtract one tick if the calculated remaining time is greater than one tick and otherwise set the remaining time to zero. By doing so the measured times are much more precise as without it."
2016-05-27 07:58:03 -06:00
Stefan Kolb
d44ecbcfbb This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started.
In my fix I use the freerun count value to determine if at least one tick passed since the start of the timer and thus if the value of the oneshot counter is correct. I also tried to use the function up_timer_gettime(…) to achieve this but, at least if compiled with no optimization the problem vanishes without using the value of the function, the function call takes too long.

Another problem treated in the fix is that if the oneshot timer/counter is canceled, we only know the remaining time with a precision of USEC_PER_TICK microseconds. This means the calculated remaining time is between 0 and USEC_PER_TICK microseconds  too long. To fix this I subtract one tick if the calculated remaining time is greater than one tick and otherwise set the remaining time to zero. By doing so the measured times are much more precise as without it.
2016-05-27 07:51:50 -06:00
Gregory Nutt
23f4f04448 Costmetic update to some comments 2016-05-27 07:50:06 -06:00
Pierre-noel Bouteville
55d704e3c2 ADC: In adc.h, exclude upper half fields if common upper half is not used (CONFIG_ADC not defined). 2016-05-27 07:16:30 -06:00
Pierre-noel Bouteville
41412d0ce9 * fix a bug in crc computation for ms583730
* implement POSIX read.
2016-05-27 07:05:20 -06:00
Gregory Nutt
3d3b7b5422 EFM32, STM32, TIVA: Allow lower half driver to build if any ADC is selected. Should not depend on CONFIG_ADC. 2016-05-27 06:46:33 -06:00
Gregory Nutt
3e7b2d617a All drivers that use SPI must call SPI_LOCK and SPI_UNLOCK. This is not optional. 2016-05-26 14:56:10 -06:00
Gregory Nutt
d5a4f85893 ADS1255 Driver: Must also lock the SPI bus before using it. 2016-05-26 14:00:33 -06:00
Gregory Nutt
d2caa93f1a ADS1255 Driver: Must not do SPI access from interrupt handler. Use the worker thread instead. 2016-05-26 13:44:11 -06:00
Gregory Nutt
1571575d54 Perhaps this is a little clearer 2016-05-26 13:44:10 -06:00
Gregory Nutt
5ea37bb139 Merged in paulpatience/nuttx/warnings (pull request #33)
Silence some warnings
2016-05-26 13:09:58 -06:00
Gregory Nutt
31ac3f5123 STM32 ADC: Missed on adc_receive 2016-05-26 12:42:34 -06:00
Gregory Nutt
01af4d1af1 Merge branch 'adcbind' 2016-05-26 12:40:17 -06:00
Gregory Nutt
aa05767a00 Add ADC bind method to the Tiva ADC drivers 2016-05-26 12:39:22 -06:00
Gregory Nutt
8f2a660c8b Add ADC bind method to the STM32 ADC drivers 2016-05-26 12:25:54 -06:00