Petro Karashchenko
d499ac9d58
nuttx: fix multiple 'FAR', 'CODE' and style issues
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
yinshengkai
9852428953
fs: procfs add poll support
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Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2023-12-26 19:23:13 -08:00
dulibo1
b57e43b4d0
clk:fix some issues when use rpmsg clk
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1.check the rpmsg name when clk_register.
2.clk_get rpmsg clk print error:
clk/clk.c:1231:3: runtime error: null pointer passed as argument 2, which is declared to never be null
3.fix some function miss keyword FAR.
4.clk_disable_unused may disable rpmsg clk which disable the clk that maybe used by others
Signed-off-by: dulibo1 <dulibo1@xiaomi.com>
2023-09-22 08:47:23 +08:00
zhengshaobo1
6e6ba062fd
clock flags add CLK_OPS_PARENT_ENABLE, parents need enable during gate/ungate, set rate and re-parent
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Signed-off-by: zhengshaobo1 <zhengshaobo1@xiaomi.com>
2023-09-19 10:34:48 +08:00
zhengshaobo1
be767dde01
vela fs procfs add clock procfs entry
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procfs enrty add clock feature procfs operations
Signed-off-by: zhengshaobo1 <zhengshaobo1@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-09-19 10:34:48 +08:00
zhengshaobo1
09a81017b8
To solve the problem of unordered setting of div & mux, after solving the problem, the frequency will be set to mux first, and then div
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Signed-off-by: zhengshaobo1 <zhengshaobo1@xiaomi.com>
2023-09-10 13:36:16 +03:00
dongjiuzhu1
afec562fbb
drivers/clk: support using clk function at interrupt and idle
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Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-07-28 07:12:51 -07:00
liaoao
a44f498842
rpmsgclk: allow client to disable clk of server
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Signed-off-by: liaoao <liaoao@xiaomi.com>
2023-07-28 06:57:29 -07:00
lilei19
38f64f559d
change strcpy to strlcpy
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Signed-off-by: lilei19 <lilei19@xiaomi.com>
2023-02-24 12:15:40 +08:00
anjiahao
b88a8cf39f
use rmutex inside of all repeated implementation
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Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2022-05-30 19:43:48 +08:00
zhuyanlin
565964a12f
driver: add clk framework
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N/A
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-12-07 01:35:45 -06:00
