arm-none-eabi-ld: /tools/gcc-arm-none-eabi/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libsupc++.a(eh_alloc.o): in function `_GLOBAL__sub_I__ZN9__gnu_cxx9__freeresEv':
eh_alloc.cc:(.text.startup._GLOBAL__sub_I__ZN9__gnu_cxx9__freeresEv+0x12): undefined reference to `getenv'
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Once these messages are thrown during the system's bring-up, it is
advisable them to be output by the syslog considering the file
system initialization.
The SmartFS partition needs to be formatted before being mounted.
Otherwise, it would throw an error message. The error message now
contains a suggestion to format the partition when such an error
is detected.
The code is mainly derived from the NuttX qemu-rv/rv-virt codebase.
Major changes:
- boards/Kconfig: add new BOARD_K230_CANMV
- arch/risc-v/Kconfig: add new CHIP_K230 chip and ARCH_RV_MMIO_BITS
- arch/risc-v/src/common/riscv_mtimer.c: use ARCH_RV_MMIO_BITS to
select MMIO access width
New additions:
- arch/risc-v/include/k230/: k230 SoC definitions
- arch/risc-v/src/k230/: k230 SoC sources
- boards/risc-v/k230/canmv230/: CanMV-K230 board sources and configs
- Documentation/platforms/risc-v/k230/: simple doc
Note that only FLAT build works for canmv230 now.
This PR has changes in RiscV common layer thus may affect other RiscV ports
It changes the mtime/mtimecmp access control from using config ARCH_RV64 to
newly intorduced config ARCH_RV_MMIO_BITS.
Original design uses ARCH_RV64 to select 64bit MMIO in riscv_mtimer.c, this
can't cope with the situation with K230 --- it has ARCH_RV64 but only can do
32bit MMIO. So a new ARCH_RV_MMIO_BITS config has been introduced. Its value
depicts the MMIO width in bits. The MMIO_BITS defaults to 32/64 for RV32/
RV64 respectively. This allows the macro to replace current use of ARCH_RV64
in riscv_mtimer.c.
The new MMIO_BITS config is a derived one, and for RiscV chips with
equal CPU and MMIO widths there is no need to explicitly set it as the
default rule will do that. Only chips with different CPU and MMIO widths
need set it in Kconfig.
So by design this change should be safe but RiscV ports should be checked.
"ostest" verification has been done for:
- canmv230/nsh
- rv-vivt/nsh
- rv-virt/nsh64
configuration generation and manual check of derived RV_MMIO_BITS has been
done for:
- star64/nsh
- arty_a7/nsh
- bl602evb/nsh
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This PR adds support for PINE64 Ox64 64-bit RISC-V SBC, based on Bouffalo Lab BL808 SoC (T-Head C906 Core). Most of the code is derived from NuttX for Star64 JH7110. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64
### Modified Files
`boards/Kconfig`: Added Ox64 board
### New Files in boards/risc-v/bl808/ox64
`src/bl808_appinit.c`: Startup Code
`include/board.h`: Ox64 Definitions
`include/board_memorymap.h`: Memory Map
`src/etc/init.d/rc.sysinit`, `rcS`: Startup Script
`src/.gitignore`: Ignore the tmp filesystem
`scripts/ld.script`: Linker Script
`scripts/Make.defs`: Ox64 Makefile
`src/Makefile`: Ox64 Makefile
`Kconfig`: Ox64 Config
`configs/nsh/defconfig`: Build Config for `ox64:nsh`
### Updated Documentation
`platforms/risc-v/bl808/index.rst`: New page for Bouffalo Lab BL808 SoC
`platforms/risc-v/bl808/boards/ox64/index.rst`: Building and booting NuttX for Ox64
`platforms/risc-v/jh7110/boards/star64/index.rst`: Fix typo
1.Remove RAMLOG_OVERWRITE option and related code
2.Broadcast the readability to all reader and poller
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.
We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.
Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.
use instrument_register to register entry function and exit function.
They will be called by the instrumented function
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Co-authored-by: Jari van Ewijk <jari.vanewijk@nxp.com>
Co-authored-by: David Sidrane <david.sidrane@nscdg.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
imxrt:Kconfig fix formatting
imxrt:usbphy move IMXRT_USBPHY{1|[2]}_BASE to memory map
imxrt:lpspi Fix build breakage from adding 1170
imxrt:Finish 1170 iomux and clockconfig versioning
imxrt:Remove duplicate imxrt_clock{off|all}_lpi2c4
imxrt:pmu remove duplicate dcd non 117x header
imxrt:lpspi Fix unused var warnings
imxrt:lpi2c Fix unused var warnings
imxrt:lowputs Fix unused var warnings
imxrt:imxrt117x_dmamux fix duplicate entries
imxtr:serial Use IOMUX_PULL_{UP|DOWN} and map IOMUX V1 to them
imxrt:MPU Support the 1170
imxrt:dmamux Alias IMXRT_DMAMUX0_BASE as IMXRT_DMAMUX_BASE
imx1170:ccm Alias CCM_CCGR_DMA & CCM_CCGR_SNVS_LP for compatiblity
Author: Peter van der Perk <peter.vanderperk@nxp.com>
IMXRT7 Add LPUART 9/10/11/12 support
Author: David Sidrane <david.sidrane@nscdg.com>
imxrt:1170pinmux Add QTIMER pins
imxrt:1170pinmux Add GPT pins
imxrt:1170pinmux Add FLEXPWM pins
imxrt1170:pinmap Add GPIO_ENET_1G pinning
imxrt:enet Support ENET_1G
imxrt:periphclks rt1170 does not have canX_serial clock
imxrt:flexcan:Layer imxrt_ioctl
imxrt117x:memorymap added CAN3
imxrt:ADC support ver1 and ver2 for imxrt117x
imxrt:imxrt117x_ccm Align timer naming with other imxrt QTIMERn->TIMERn
imxrt:imxrt117x_ccm align CCM names with rt106x
imxrt:XBAR support larger number of selects needed on imxrt1170
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
FlexSPI AHB Region support, PIT rename for compatiblity
imxrt:USB Analog add VBUS_VALID_3V
FlexSPI expand prefetch registers for IMXRT117X
imxrt:Support Initialization of FlexRam without Running from OCRAM
imxrt: ocotp add UNIQUE_ID register definition
imxrt: enet use ocotp unique_id
imxrt: enet fixes for imxrt117x
imxrt: ethernet pinmux sion enable
imxrt:imxrt_periphclk_configure add memory sync
Flush the pipeline to prevent bus faults, by insuring a
peripheral is clocked before being accessed on return from
this function.
imxrt:Restructure gpioN to padmux mapping
imxrt:Add imxrt1170 daisy
imxrt: correct power modes for imxrt117x fixing hang on WFI
imxrt: imxrt117x TCM MPU config
imxrt: FlexRAM clocking DIV0 setup
imxrt: 117x periphclocks wait for status bit
imxrt: iomucx set pad settings correctly and allow reconfiguration
imxrt: enet align buffers 64-byte for optimal performance
Add DSC barriers for write-through cache support
imxrt: imxrt1170 use FlexCAN FD/ECC features
imxrt:iomuxc_ver2 (117x) SD_B1 and DISP_B1 use PULL feild not PUE/PUS
imxrt:Fix 1170 SNVS addressing
imxrt: enet set mii clock after ifdown so that phy keep working
nxstyle fixes
imxrt: preprocessor and include fixes
Fix configs
imxrt1170-evk clean defconfig
1. Configurable mapping of virtual address to psram physical address
2. Access SPIRAM memory at high physical address through bank switching
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
Version 1.3.1 is the latest tagged version as of November
the 21st, 2023. This patch prepares the required changes
to make v1.3.1 work.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Enable CONFIG_DEV_SIMPLE_ADDRENV for all the qemu configs that used
the virtio driver to fix compile error when use the NuttX implemented
metal io read/write operations.
Becasue up_addrenv_pa_to_va() and up_addrenv_va_to_pa() are not
implemented by default.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Summary:
- Fixes a linker issue in https://github.com/apache/nuttx/pull/8244 by disabling compiler optimization.
- Adjusts CONFIG_DEFAULT_TASK_STACKSIZE to 4096 to ensure proper functioning of cxxtest.
Impact:
- The changes may slightly affect performance due to disabled optimizations
but are necessary for cxxtest stability.
Testing:
- Successfully tested on QEMU-8.1.2 with arm gcc 12.3.Rel1,
confirming resolution of the linker issue and stable operation of cxxtest.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
These values are board-specific properties that must be known on the application side.
Until now, these values had to be hardcoded on the application side.
1. If CONFIG_ESP32S3_PHY_INIT_DATA_IN_PARTITION and CONFIG_ESP32S3_SUPPORT_MULTIPLE_PHY_INIT_DATA are enabled,
PHY initialization data (PHY initialization data is used for RF calibration) will be loaded from a partition.
2. The corresponding PHY init data type can be automatically switched according to the country code,
China's PHY init data bin is used by default, country code can be modified through the wapi command: wapi country <ifname> <country code>.
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
This commit sets the BLE's interrupt as a IRAM-enabled interrupt,
which enables it to run during a SPI flash operation. This enables
us to create a cache to off-load semaphores and message queues
operations and treat them when the SPI flash operation is finished.
By doing that, we avoid packet losses during a SPI flash operation.
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.
It also makes the code look more similar to the ESP32-S3 SPI flash
implementation by creating a common `esp32_spiflash_init` that is
responsible to create the SPI flash operation tasks. The function
intended to initialize the SPI flash partions was, then, renamed to
`board_spiflash_init`.
During PSRAM initialization and flash operations, the Cache needs to be disabled.
So all data and code for the aforementioned scope is required to be placed in Internal RAM.
After https://github.com/apache/nuttx/pull/11007/ was merged, the
path for some files changed, requiring the linker to be fixed to
make it run from the internal memory once again.
The LINUM-STM32H753BI is a board with RS485, RS232, SD Card, CAN,
SD Card, USB, Ethernet, LCD, etc.
Signed-off-by" Jorge Guzman jorge.gzm@gmail.com
ci: correction in nsh defconfig file of LINUM-STM32H753BI
Using up_textheap_memalign to allocate memory if arch support textheap
for loading section.
The default system heap does not support execution permissions,
so up_textheap_memalign allocation is required.
this patch can fix issue about #11043
update esp32 elf config:
remove -CONFIG_ARCH_USE_TEXT_HEAP=y becuase ARCH_CHIP_ESP32 select
ARCH_HAVE_TEXT_HEAP
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
CI test for fmemopen() function was added. The test was merged with
fopencookie interface test and merged into single test_stdio.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
- migrated /README are removed from /boards
- there are a lot of READMEs that should be further converted to rst.
At the moment they are moved to Documentation/platforms and included in rst files
The STM32F401RC-RS485 is a board with RS485 support, SD Card, buttons,
leds, temperature sensor, adc and etc.
Signed-off-by: Rodrigo Sim rcsim10@gmail.com
File system CI test was not testing the correct behavior of scanf and just
checked whether program did not end with hard fault. This adds
functionality check and required configuration options to run FS test.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Scanf CI test was not testing the correct behavior of scanf and just
checked whether program did not end with hard fault. This adds
functionality check and required configuration options to run scanf
test.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
To compile arm64 NuttX, use the following command:
./tools/configure.sh -l qemu-armv8a:nsh_fiq
To run，use the following command
qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
test config: ./tools/configure.sh -l qemu-armv8a:nsh_smp
Pass ostest
No matter big-endian or little-endian, ticket spinlock only check the
next and the owner is equal or not.
If they are equal, it means there is a task hold the lock or lock is
free.
Signed-off-by: TaiJu Wu <tjwu1217@gmail.com>
Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
This commit sets the BLE's interrupt as a IRAM-enabled interrupt,
which enables it to run during a SPI flash operation. This enables
us to create a cache to off-load semaphores and message queues
operations and treat them when the SPI flash operation is finished.
By doing that, we avoid packet losses during a SPI flash operation.
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.
we can mount a zipfile in nuttx use mount command like this:
mount -t zipfs -o /data/test.zip /zip
The zipfs is a read only file system,The advantage is that it
does not occupy additional space when reading the decompressed file.
When used, reading and decompression operations are simultaneous.
The known disadvantage is that when using seek to read forward,
it will reopen and cause slow speed problems.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
External JLink is required to program the board, so the console via RTT
is available anyway. It is much more convenient to use than soldering the
P4 connector and working with an external UART converter.
