Commit Graph

22142 Commits

Author SHA1 Message Date
nuttxs
a83a569652 arch/xtensa/esp32s3: Add qspi/spi_slave/lcd DMA request return value.
Optimize DMA initialization for duplicate calls.
2024-07-23 22:48:24 +08:00
Yanfeng Liu
3b9a346fe7 riscv/nsbi: unblock up_udelay
This fixes the always zero time in NuttSBI case as the `error` field
contains the correct timestamp. This in turn also fixes the block of
`up_udelay()` which further leads to boot failure of `canmv230:master`
config.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-22 23:46:43 +08:00
Inochi Amaoto
0ddcbe62ec arch/risc-v: does not clear IPI address in S mode
According to the riscv-aclint doc, writing 0 to SSWI address
has no effect. Remove this unnecessary write for S mode.

Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-18 22:59:29 +08:00
YAMAMOTO Takashi
985d395b02 esp32s3_textheap.c: fix a build error w/o CONFIG_ESP32S3_SPIRAM 2024-07-18 16:42:52 +08:00
nuttxs
de3737cd90 arch/xtensa/esp32s3: Deinitialize ESP32-S3 QSPI GDMA engine.
Correctly releasing channels after using QSPI is crucial
to prevent issues caused by multiple requests that may lead
to DMA channel resource conflicts.
2024-07-18 13:41:04 +08:00
chao an
7780cfc5a6 tricore/cmake: add support of cmake build for tricore
Toolchain Upstream:
https://github.com/EEESlab/tricore-gcc-toolchain-11.3.0

CMake command:
$ cmake -B build -DBOARD_CONFIG=tc397/nsh -GNinja
$ cmake --build build

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-18 13:40:49 +08:00
Inochi Amaoto
000b0ec4a1 arch/risc-v: make common up_allocate_heap weak symbol
The common `up_allocate_heap` is a strong symbol, which leads to
error when building with CONFIG_DEBUG_LINK_WHOLE_ARCHIVE. Make
`up_allocate_heap` weak function to mitigate this problem.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-18 13:40:37 +08:00
Lup Yuen Lee
bdf60d7966 risc-v/bl808, sg2000: Configure MMU to cache Kernel Text, Data and Heap (T-Head C906)
This PR configures the BL808 and SG2000 MMU (inside T-Head C906) to cache the the Kernel Text, Data and Heap.  We set the MMU Flags (Shareable, Bufferable and Cacheable) as explained in this article: https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906

This PR fixes the Slow Memory Access for NuttX Kernel in BL808 and SG2000: https://github.com/apache/nuttx/issues/12696

In the next PR, we will fix the Slow Memory Access for NuttX Apps, by caching the User Text and Data.

arch/risc-v/src/bl808/bl808_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for BL808 Kernel Text, Data and Heap

arch/risc-v/src/sg2000/sg2000_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for SG2000 Kernel Text, Data and Heap
2024-07-17 12:08:04 -03:00
Yanfeng Liu
d6c67c555f riscv/trap: fix sp restore logic
This fixes stack pointer restore logic to avoid parent stack corruption
by forked child in PROTECTED build.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-17 17:20:00 +08:00
Yanfeng Liu
08c4686f47 riscv/fork: fix tp for PROTECTED
This fixes `tp` value of forked child in PROTECTED build to support
vfork. Why? the optimized `dispatch_syscall` requires `tp` to hold
the task TCB since commit e6973c764c.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-17 17:20:00 +08:00
chao an
4db1169e6f arch/tricore: fix compiler warning on GCC toolchain
tc3xx/tc3xx_timerisr.c: In function ‘up_timer_initialize’:
tc3xx/tc3xx_timerisr.c:58:39: warning: passing argument 1 of ‘tricore_systimer_initialize’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
   58 |   lower = tricore_systimer_initialize(&MODULE_STM0, 192, SCU_FREQUENCY);
In file included from tc3xx/tc3xx_timerisr.c:31:
nuttx/arch/tricore/src/common/tricore_internal.h:252:35: note: expected ‘void *’ but argument is of type ‘volatile Ifx_STM *’ {aka ‘volatile struct _Ifx_STM *’}
  252 | tricore_systimer_initialize(void *tbase, int irq, uint64_t freq);
      |                             ~~~~~~^~~~~
tc3xx/tc3xx_serial.c:177:16: warning: initialization discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
  177 |   .uartbase  = &MODULE_ASCLIN0,
      |                ^
tc3xx/tc3xx_serial.c:178:16: warning: initialization discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
  178 |   .pins      = &g_uart0_pins,
      |                ^
common/tricore_trapcall.c: In function ‘tricore_trapcall’:
common/tricore_trapcall.c:66:3: warning: passing argument 4 of ‘_assert’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
   66 |   PANIC_WITH_REGS("Trap", CURRENT_REGS);
      |   ^~~~~~~~~~~~~~~
In file included from common/tricore_trapcall.c:29:
nuttx/include/assert.h:189:45: note: expected ‘void *’ but argument is of type ‘volatile uintptr_t *’ {aka ‘volatile long unsigned int *’}
  189 |              FAR const char *msg, FAR void *regs);

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-17 17:18:02 +08:00
chao an
8e20b8d862 arch/tricore: add support of tricore gcc toolchain
Toolchain Upstream:
https://github.com/EEESlab/tricore-gcc-toolchain-11.3.0

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-17 17:18:02 +08:00
zouboan
b817db86b8 zynq-mpsoc: add support for mio/emio 2024-07-16 18:50:52 -03:00
chao an
bc7791e079 arch/tricore: synchronize instruction/data following MTCR/MFCR
Some barrier are necessary to avoid compiler optimizations

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-16 21:13:13 +08:00
GC2020
8f243d3eb7 /rp2040 Rename the RP2040-specific PWM_MULTICHAN definition to avoid confusion with the global PWM_MULTICHAN 2024-07-16 20:09:10 +08:00
shizhenghui
fea727a050 arch/sim/Makefile: add openh264 & x264 include path
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
347864152d sim codec: add dependence to Kconfig
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
61f79757f7 v4l2m2m/sim encoder: move hostencoder to x264encoder
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
7248ba0293 sim decoder: update CMakeLists.txt
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
3675cfe585 v4l2m2m/sim decoder: rename hostdecoder to openh264dec
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
Eren Terzioglu
0df037855a esp32[c3]: Add mcuboot build script for esp32c3-legacy 2024-07-16 10:30:56 +08:00
Eren Terzioglu
a9082e0882 esp32[s2]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
c9f5ae5fa4 esp32[s3]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
024e95875a esp32: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
553b1f5f5e esp32[c3|c6|h2]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
adriendesp
baf52268cc arch/xmc4: Added pwm driver 2024-07-15 16:14:55 -03:00
Peter van der Perk
622b6d234a s32k1xx: FlexIO I2C master driver 2024-07-15 10:06:55 -03:00
Raman Gopalan
ef271b8fe2 at32uc3a0: Initial work for SimpleMachines' Mizar32-A 2024-07-15 20:46:41 +08:00
Yanfeng Liu
8bdc975abb riscv/cmake: fix Toolchain.cmake issue
This fixes the following issue when configuring canmv230:master
with Ubuntu stock toolchain and cmake 3.22:

```
CMake Error at .../arch/risc-v/src/cmake/Toolchain.cmake:218 (if):
  if given arguments:
    "STREQUAL" "GNU_RVG"
  Unknown arguments specified
```

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-15 19:41:03 +08:00
hujun5
a4fece3450 spin_lock: inline spin_lock
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
2024-07-15 02:29:30 +08:00
zouboan
ae8ce535f3 arm64/arm64_boot.c: Fix exception caused by accesses to ICC_SRE_EL3 when GICv3 was not implemented 2024-07-15 02:26:40 +08:00
Huang Qi
e047ab9c70 riscv: Initial support for debug trigger module
Implement up_debugpoint_add/up_debugpoint_remove for riscv.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-14 20:32:19 +08:00
Eren Terzioglu
c15c0d1a78 esp32[h2]: Add MCUBoot support 2024-07-14 11:38:29 +08:00
Eren Terzioglu
0f0c258fa2 esp32[c6]: Add MCUBoot support 2024-07-14 11:38:29 +08:00
zouboan
ea532cb11a arch/arm64: add initial support for ZYNQ MPSOC
arch/arm64: add initial support for ZYNQ MPSOC

arch/arm64: add initial support for ZYNQ MPSOC
2024-07-13 20:51:39 -03:00
Yanfeng Liu
211e2cd8b9 riscv/k230: revise canmv230:pnsh
This revises canm230:pnsh in a few ways:

- adjusting linker scripts structure,
- asserting PMP setting results,
- adjusting configs for both k230d and k230 devices.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-13 07:21:22 -03:00
Michal Lenc
5c48944e0b samv7: fix compile warning in PWM and UART drivers
The following warnings is fixed:

chip/sam_pwm.c:961:12: warning: unused variable 'regval' [-Wunused-variable]
  961 |   uint32_t regval;

chip/sam_serial.c: In function 'sam_dma_txavailable':
chip/sam_serial.c:2264:7: warning: unused variable 'rv' [-Wunused-variable]
 2264 |   int rv;

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-13 11:37:06 +02:00
simbit18
f12c4e05cc Fix Kconfig style
Remove spaces from Kconfig files
Add TABs
Replace help => ---help---
Remove extra TABs
2024-07-12 06:37:59 +08:00
chao an
d4024c8388 arch/armv8-r: update g_running_tasks before context switch
fix invalid running_task() in assertion logic

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-12 00:39:37 +08:00
simbit18
2f8560e838 tools/ci: enable avr32dev1 build
removed in the tools/ci/testlist/other.dat file the entries
 -avr32dev1:nsh
 -avr32dev1:ostest

avr32_bringup.c
Fix  Error: ./avr32_bringup.c:54:4: error: #warning "Not Implemented"

comment out directive '#warning'
/* #warning "Not Implemented" */

avr_doirq.c

fix avr32/avr_doirq.c:117: error: assignment discards qualifiers from pointer target type
  regs = g_current_regs; -> regs = (uint32_t *)g_current_regs;
2024-07-12 00:39:21 +08:00
chao an
95a9facf3a arch/armv8-r: new config to set SPIs Configuration to edge-triggered
Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-11 15:35:41 +08:00
Henry Rovner
091372069c risc-v/bl808: Add SPI driver
This commit implements a driver for SPI0 and SPI1 on the BL808 and introduces an accompanying example configuration.
2024-07-11 11:32:24 +08:00
chao an
b191153cdc arch/armv8-r: fix typos in config
replace ARMV7R to ARMV8R

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-10 18:41:13 -03:00
Michal Lenc
a91d40e0e8 samv7: fix CAN FD configuration
Larger RX/TX buffers might be required for both FD and FD_BSW modes.
Default bit timing values are also changed since the original ones
did not provide correct results for default SAMv7 board clock selection
(150 MHz clock frequency). The current values provide correct bit timing
with sample point as close to 87.5 %.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-10 11:33:03 -03:00
Michal Lenc
e16ee4dba3 can: enhance bit timing ioctl to set both nominal and data bit timing
This adds field type to canioc_bittiming_s structure that allows
to set/obtain bit timing for both CAN CC and CAN FD.
CANIOC_GET_BITTIMING is now bidirectional: user specifies type field
and gets other fields from the controller.

The commit also updates current CAN FD capable controllers using the
ioctl. The type is not checked for classical CAN only controllers
and nominal bit timing is returned regardless of type value.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-10 11:33:03 -03:00
Eero Nurkkala
48cf91a7be arm64/imx9: ccm: add default clk init
This adds enablers for setting various clocks to some default
values. Also, this provides helpers to grant nonsecure access
to a number of clocks. Bootloader may utilize these to make
the system boot in a deterministic manner.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-07-09 21:14:11 -03:00
xuxingliang
848eca04ca arch/arm64: allow to use custom idle
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-07-09 19:36:48 +08:00
xuxingliang
94387630c9 arch/arm64: remove not used idle trace
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-07-09 19:36:48 +08:00
Lwazi Dube
b881868f19 arch/arm/sama5: Fix typos in ohci driver comments. 2024-07-09 09:20:13 +08:00
Huang Qi
d0210c1174 riscv_tcbinfo: Fix register ordering for PC
X0 is always 0 but still should be transfered to the client, but it don't existed in thread context, use any other register for it, and its value will be omitted by gdb client.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-08 21:13:25 +08:00