Commit Graph

39021 Commits

Author SHA1 Message Date
Masayuki Ishikawa
812257d058 arch: armv7-a: Fix style warnings in mmu.h
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-14 16:40:01 -08:00
Masayuki Ishikawa
4cc38caba9 sched: Fix nx_waitid(), nx_waitpid(), nxtask_exithook() for SMP
Summary:
- I noticed waitpid_test stops with lc823450-xgevk:rndis
- The condition was CONFIG_DEBUG_ASSERTION=y
- Actually, the child task sent SIGCHILD but the parent couldn't catch the signal
- Then, I found that nx_waitid(), nx_waitpid() use sched_lock()
- However, a parent task and a child task are running on different CPUs
- So, sched_lock() is not enough and need to use a critical section
- Also, signal handling in nxtask_exithook() must be done in a critical section

Impact:
- SMP only

Testing:
- Tested with ostest with the following configurations
- lc823450-xgevk:rndis (CONFIG_DEBUG_ASSERTION=y and n)
- spresense:smp
- spresense:wifi_smp (NCPUS=2 and 4)
- sabre-6quad:smp (QEMU)
- esp32-core:smp (QEMU)
- maix-bit:smp (QEMU)
- sim:smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-14 16:31:49 -08:00
Bernd Walter
0cf66149ed twi_takesem() had been changed to return an int.
Neither the prototype, nor the description had been adapted, resulting in
compiler errors.
Fix both points.
2020-11-14 19:17:14 +01:00
Nathan Hartman
1aac3d7e57 stm32/stm32_aes.c: Fix nxstyle errors
arch/arm/src/stm32/stm32_aes.c:

    * Fix nxstyle errors.
2020-11-13 16:13:58 -08:00
Sara Souza
e6b6f06d22 xtensa/esp32: added support to automonitor by capture 2020-11-13 13:01:40 -03:00
YAMAMOTO Takashi
ca9bd8be0e Remove ARCROSSDEV leftovers
It has been removed while ago.
cf. 5efa93ec26
2020-11-13 05:54:20 -08:00
Dong Heng
bfb5214ef8 xtensa/esp32: Add SPI Flash hardware encryption I/O support 2020-11-13 08:37:59 +01:00
Nathan Hartman
4977522ead stm32: Add DMAMUX register mappings and request IDs
arch/arm/src/stm32/hardware/stm32_dmamux.h,
arch/arm/src/stm32/hardware/stm32g47xxx_dmamux.h:

    * New files, based on STM32G474RE reference manual, RM0440 Rev 4.
2020-11-13 08:09:10 +01:00
Nathan Hartman
35126b31b7 stm32f0l0g0/stm32_dmamux.h: Fix errors in bitfield definitions
Used reference manual for STM32G071CB. The F0 and L0 families do not
appear to have a DMAMUX.

arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h:

    * Remove all mentions of DMAMUX12 from comments. This family has
      at most DMAMUX1 only.

    * Add missing defines DMAMUX_CCR_SPOL_NONE,
      DMAMUX_CCR_SPOL_RISING, DMAMUX_CCR_SPOL_FALLING, and
      DMAMUX_CCR_SPOL_BOTH.

    * DMAMUX_CCR_SYNCID_SHIFT: Fix comment. Was "Bits 24-26" (3 bits)
      but datasheet shows bits 24-28 (5 bits).

    * DMAMUX_CCR_SYNCID_MASK: Fix mask. Was 0x7 (3 bits) but datasheet
      shows (5 bits) 0x1f.

    * DMAMUX1_CSR_SOF(x): Add parenthesis around macro parameter
      expansion.

    * DMAMUX1_CFR_SOF(x): Rename to DMAMUX1_CFR_CSOF(x) for
      consistency with datasheet and add parenthesis around macro
      parameter expansion.

    * DMAMUX_RGCR_GPOL_MASK: Fix incorrect mask. Was 0x7 (3 bits) but
      datasheet shows only 2 bits (0x3).

    * Add missing defines DMAMUX_RGCR_GPOL_NONE,
      DMAMUX_RGCR_GPOL_RISING, DMAMUX_RGCR_GPOL_FALLING, and
      DMAMUX_RGCR_GPOL_BOTH.

    * DMAMUX_RGCR_GNBREQ_SHIFT: Fix incorrect value. Was 17 (collision
      with DMAMUX_RGCR_GPOL_SHIFT) but datasheet and comment both show
      this bitfield at bits 19-23.

    * DMAMUX_RGCR_GNBREQL_MASK: Fix incorrect mask. Was 0x7 (3 bits)
      but datasheet shows 5 bits (0x1f).

    * DMAMUX1_RGSR_SOF(x): Rename to DMAMUX1_RGSR_OF(x) for
      consistency with datasheet and add parenthesis around macro
      parameter expansion.

    * DMAMUX1_RGCFR_SOF(x): Rename to DMAMUX1_RGCFR_COF(x) for
      consistency with datasheet and add parenthesis around macro
      parameter expansion.

    * DMAMAP_MAP(d,c): Add parenthesis around macro parameter
      expansion.

    * Fix nxstyle errors.
2020-11-12 23:07:37 -08:00
Nathan Hartman
fd020fa0ae stm32h7/stm32_dmamux.h: Add missing CCR SPOL defines
arch/arm/src/stm32h7/hardware/stm32_dmamux.h:

    * Add missing defines DMAMUX_CCR_SPOL_NONE,
      DMAMUX_CCR_SPOL_RISING, DMAMUX_CCR_SPOL_FALLING, and
      DMAMUX_CCR_SPOL_BOTH.

    * Fix nxstyle errors.
2020-11-13 08:03:02 +01:00
Simon Piriou
da70eb5c56 usbdev: adb: fix missing break 2020-11-12 21:35:07 -08:00
Simon Piriou
5892927aea board: add ADB example for stm32/photon 2020-11-12 21:35:07 -08:00
Peter Bee
1f5786f5ea libc/stdlib: Fix range check in strtoul(l)
The previous implementation of strtoul(l) is flawed. The range check
assumed that when overflow happens, the truncated value is smaller than
the original value. As a counter example, passing "10000000000" to
strtol will not trigger ERANGE, but return a truncated value. This patch
adds more accurate range checks.

Change-Id: I239e034e390b4974157ed6efa17110f2e74904cf
Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
2020-11-12 06:01:33 -08:00
Nathan Hartman
87bfa24c8c stm32/stm32_spi: Add SPI register definitions for STM32G47XX
arch/arm/src/stm32/hardware/stm32_spi.h:

    * Avoid numerous ifdef on STM32 part numbers and make the
      different variations of SPI peripheral features more
      self-documenting: based on STM32_HAVE_IP_SPI_V* defines
      from chip.h, define some or all of HAVE_SPI_I2S,
      HAVE_SPI_TI_MODE, HAVE_SPI_ARB_DATA_SIZE, HAVE_SPI_FIFOS,
      HAVE_SPI_NSSP, HAVE_SPI_I2S_ASTRT, and make decisions on
      which registers and bitfields to define based on them.

    * Define registers and bitfields for STM32_HAVE_IP_SPI_V4,
      currently used only for STM32G47XX family MCUs, including
      SPI_CR1_CRCL, SPI_CR2_NSSP, SPI_CR2_FRXTH, SPI_CR2_LDMARX,
      SPI_CR2_LDMATX, SPI_CR2_DS_SHIFT/SPI_CR2_DS_MASK,
      SPI_SR_FRLVL_SHIFT/SPI_SR_FRLVL_MASK, and
      SPI_I2SCFGR_ASTRTEN.

    * SPI_I2SCFGR_I2SSTD_PHILLIPS: Was defined incorrectly as
      (xx << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
      (0 << SPI_I2SCFGR_I2SSTD_SHIFT).

    * SPI_I2SCFGR_I2SSTD_MSB: Was defined incorrectly as
      (0 << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
      (1 << SPI_I2SCFGR_I2SSTD_SHIFT).

    * Fix nxstyle errors.

arch/arm/include/stm32/chip.h:

    * Add new section "Peripheral IP versions" and specify version of
      SPI IP block for STM32F10XX, STM32F20XX, STM32F30XX, STM32F33XX,
      STM32F37XX, STM32F4XXX, STM32G47XX, and STM32L15XX.
2020-11-12 04:37:32 -08:00
Nathan Hartman
b63c0863b2 stm32h7/stm32_dmamux.h: Fix errors in bitfield definitions
arch/arm/src/stm32h7/hardware/stm32_dmamux.h:

    * DMAMUX1_CSR_SOF(x): Add parenthesis around macro parameter
      expansion.

    * DMAMUX1_CFR_SOF(x): Rename to DMAMUX1_CFR_CSOF(x) for
      consistency with datasheet and add parenthesis around macro
      parameter expansion.

    * DMAMUX_RGCR_GPOL_MASK: Fix incorrect mask. Was 7 (3 bits) but
      datasheet shows only 2 bits.

    * Add missing defines DMAMUX_RGCR_GPOL_NONE,
      DMAMUX_RGCR_GPOL_RISING, DMAMUX_RGCR_GPOL_FALLING, and
      DMAMUX_RGCR_GPOL_BOTH.

    * DMAMUX_RGCR_GNBREQ_SHIFT: Fix incorrect value. Was 17 (collision
      with DMAMUX_RGCR_GPOL_SHIFT) but datasheet and comment both show
      this bitfield at bits 19-23.

    * DMAMUX_RGCR_GNBREQL_MASK: Fix incorrect mask. Was 7 (3 bits) but
      datasheet shows 5 bits.

    * DMAMUX1_RGSR_SOF(x): Rename to DMAMUX1_RGSR_OF(x) for
      consistency with datasheet and add parenthesis around macro
      parameter expansion.

    * DMAMUX1_RGCFR_SOF(x): Rename to DMAMUX1_RGCFR_COF(x) for
      consistency with datasheet and add parenthesis around macro
      parameter expansion.

    * DMAMAP_MAP(d,c): Add parenthesis around macro parameter
      expansion.
2020-11-12 08:04:23 +01:00
Matias N
14d14bce05 pm.h: nxstyle fixes; change License to Apache (Greg and myself authors) 2020-11-12 08:01:25 +01:00
Matias N
13619ea0df nrf52: add SPI PM support (disable/enable SPI peripheral on sleep) 2020-11-12 08:01:25 +01:00
Matias N
a806ca9577 nrf52 SPI: rework support for undefined MOSI/MISO; add support for list DMA mode 2020-11-12 08:01:25 +01:00
Matias N
18be4198e1 Revert "nrf52_spi: support not defining MISO/MOSI pins"
This reverts commit e91a806ab6.
2020-11-12 08:01:25 +01:00
Xiang Xiao
e5ab2e56f8 sim: Remove cxxtest specifial Make.defs
since the special c++ setup doesn't need anymore

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-11-12 14:37:59 +08:00
chao.an
6aee468d72 eventfd: remove the unique minor limit
The unique minor limit of 255 will overflow easily in
some scenarios where eventfd needs to be create/destroy
frequently:

  while (1)
    {
      fd = eventfd(0, 0);  // minor++
      sleep(1);
      close(fd);
    }

remove the unique minor limit.

Change-Id: I0ea1c825ce9b542c883166cb3e72574455ffdd0d
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-11 18:26:59 -08:00
dongjiuzhu
089b1c17f6 driver/sensor: add fetch api to read sensor data directly
1.use userspace buffer rather than intermediate buffer of upperhalf driver
2.support block and non-block ways.

Change-Id: I1d0cecfaa20ce54961c58713d8f2f8857e349791
Signed-off-by: dongjiuzhu <dongjiuzhu1@xiaomi.com>
2020-11-11 18:25:22 -08:00
dongjiuzhu
2cda16b606 driver/sensor: add new feature about sensor driver
1.support for multi-user access
2.support special cmd to control sensor
3.support userspace to set size of intermediate buffer
  by ioctl: SNOIC_SET_BUFFER_SIZE

Change-Id: I9ce3a65b88b12c28388ec397431f1a277b120c2a
Signed-off-by: dongjiuzhu <dongjiuzhu1@xiaomi.com>
2020-11-11 18:25:22 -08:00
dongjiuzhu
2482052228 driver/sensor: user specifies device register number
N/A

Change-Id: Idd11461f933dd21b7271cd3ca87a2e33127a9d34
Signed-off-by: dongjiuzhu <dongjiuzhu1@xiaomi.com>
2020-11-11 18:25:22 -08:00
dongjiuzhu
0d92e50c42 sim/sensor: add sensor defconfig
Change-Id: Ib9b6866951b46f34aa9faaa1c9a6edb0b217b719
Signed-off-by: dongjiuzhu <dongjiuzhu1@xiaomi.com>
2020-11-11 18:25:22 -08:00
Xiang Xiao
84b90e00f0 libc/stdio: Preallocate the stdin, stdout and stderr
to handle the uninitialized stdin/stdout/stderr gracefully
report here:
https://github.com/apache/incubator-nuttx/issues/2203

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-11-11 09:56:10 -08:00
Masayuki Ishikawa
1dad55d4be sched: sched: Remove sched_tasklistlock.c for SMP
Summary:
- sched_tasklistlock.c was introduced to stabilize NuttX SMP
- However, the current SMP implementation is stable by recent fixes
- So I decided to remove the file finally

Impact:

- SMP only

Testing:
- Tested with ostest with the following configurations
- spresense:smp
- spresense:wifi_smp (NCPUS=2 and 4)
- sabre-6quad:smp (QEMU)
- esp32-core:smp (QEMU)
- maix-bit:smp (QEMU)
- sim:smp
- lc823450-xgevk:rndis

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-10 23:18:08 -08:00
Masayuki Ishikawa
f0bf2143f6 sched: pthread: Fix pthread_join() for SMP
Summary:
- I noticed 'pthread_rwlock test' in ostest sometimes stops
- This issue happened with spresense:wifi_smp (NCPUS=4) and sim:smp
- Finally, I found an issue in pthread_join()
- In pthread_join(), sched_lock() is used to avoid pre-emption
- However, this is not enough for SMP
- Because another CPU would continue the pthread and exit sequences
- So we need to protect it with a critical section

Impact:
- Affect SMP only

Testing:
- Tested with ostest with the following configurations
- spresnese:smp
- spresense:wifi_smp (NCPUS=2, NCPUS=4)
- sabre-6quad:smp (QEMU)
- esp32-core:smp (QEMU)
- maix-bit:smp (QEMU)
- sim:smp
- lc823450-xgevk:rndis

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-10 19:41:46 -08:00
chao.an
73d5700183 net/udp: fix nxstyle warning
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-10 19:40:41 -08:00
chao.an
95be9eaf4b net/callback: remove the assert check of conn instance
remove the connection assertion since the instance will be invalid
if the network device has been taken down.

net/netdev/netdev_ioctl.c:

1847 void netdev_ifdown(FAR struct net_driver_s *dev)
1848 {
...
1871       /* Notify clients that the network has been taken down */
1872
1873       devif_dev_event(dev, NULL, NETDEV_DOWN);
...
1883 }

Change-Id: I492b97b5ebe035ea67bbdd7ed635cb13d085e89c
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-10 19:40:41 -08:00
YAMAMOTO Takashi
5dd5174722 testbuild.sh: Add -C option to skip tree cleanness check
Build-testing a dirty tree is convenient during development.
2020-11-10 18:07:51 -08:00
YAMAMOTO Takashi
c79bda6e4f sim inttypes.h: Remove PRI/SCN macros for fast and least types
I forgot to remove some of them
in https://github.com/apache/incubator-nuttx/pull/2227 .
This commit removes them.
2020-11-10 00:03:35 -08:00
YAMAMOTO Takashi
f307d999e6 lib_libvsprintf.c: Implement "t" modifier for printf
Introduced by C99 for ptrdiff_t.
2020-11-10 00:03:06 -08:00
chao.an
e29a0d9dc6 boards/lpc31xx/pgnsh: disable environment variable support
locked region is unenough to accommodate more text in PASS1 phase

Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 23:42:46 -08:00
chao.an
f6cd23e9d2 sched/init: init the default home directory to environment
Change-Id: Ib08a7702ce2256d48b210a70fa181591bbe8abe8
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 23:42:46 -08:00
chao.an
27932faf1a sys/epoll: sync the epoll define with linux
Change-Id: If876e0c0b44de73cf2847a9d3c21ac138dd4f879
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 18:53:48 -08:00
chao.an
8b1f93af01 syscall/eventfd: correct the syscall prototype of eventfd(2)
proxies/PROXY_eventfd.c:12:14: error: conflicting types for 'eventfd'
   12 | unsigned int eventfd(int parm1)
      |              ^~~~~~~
In file included from proxies/PROXY_eventfd.c:7:
nuttx/include/sys/eventfd.h:63:5: note: previous declaration of 'eventfd' was here
   63 | int eventfd(unsigned int count, int flags);
      |     ^~~~~~~

Change-Id: I7ed0b8b442eac72592dea0e5754a36fb60ca5f8d
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 18:53:22 -08:00
chao.an
c6fe82bfa1 boards/sim: enable run-time type identification
BTW, correct some cxx compilation options

Change-Id: Id3e3eab2020ef1991d2760426d81b40e6e5eff4e
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 18:52:28 -08:00
chao.an
80e372ad14 boards/sim: correct the ARCHDEFINES definition
ARCHDEFINESXX -> ARCHDEFINES

Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 18:51:21 -08:00
chao.an
8b42e6abd2 pthread/spinlock: move the structure prototype out of the definition
pthread/pthread_spinlock.c: In function ‘pthread_spin_init’:
pthread/pthread_spinlock.c:114:11: error: dereferencing pointer to incomplete type ‘pthread_spinlock_t’ {aka ‘struct pthread_spinlock_s’}
  114 |       lock->sp_lock   = SP_UNLOCKED;
      |           ^~

Change-Id: I49dbb2682e36a17bb25a647c6468b7fb511e4a76
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 18:45:48 -08:00
Nathan Hartman
616b3e7436 include/nuttx/spi/spi.h: Fix typos in comments 2020-11-09 18:20:15 -08:00
Matias N
f55a2879ca nrf52 GPIO/GPIOTE: better expose pin interrupt capability
This change improves upon current support for pin interrupts. Before,
a pin interrupt was handled (with nrf52_gpiote_setevent) using one
of the eight available GPIOTE channels. Moreover, it didn't event let
the user specify which channel to use (simply tried to get a free one).
Also, it was buggy since it did not consider unsetting the callback.

Besides GPIOTE channels, there is another way to deal with pin interrupts.
The GPIO peripheral is capable of generating a PORT event
(for the whole GPIO port) depending on the pin SENSE configuration
(HIGH or LOW, or NONE) and GPIO DETECTMODE register
(latching or non-latching).

This change then renames nrf52_gpiote_setevent into nrf52_gpiote_set_ch_event,
maintaining functionality of original function, but now allows specifying
channel (and correctly handles unsetting the callback). Then, a
new nrf52_gpiote_set_pin_event is added, which allows to set a callback
for a given pin. During initialization, interrupt for the PORT event is
enabled and handled in such way that for each pin whose corresponding
bit in LATCH register (indicates the result of pin SENSEing) the
callback for this pin will be invoked. This mechanism means that
every pin can get an ISR. It also avoids using GPIOTE channels for this
purpose which carry higher current consumption.

This new per-pin callback mechanism has some added memory requirement
so it can be disabled and its default is dependant on DEFAULT_SMALL.
When disabled, a callback for the PORT event can be set directly
with nrf52_gpiote_set_port_event

There was only one use of nrf52_gpio_setevent() which was migrated
into nrf52_gpio_set_ch_event() passing channel zero.
2020-11-09 20:23:29 +01:00
chao.an
723698c787 sched/timer: add support of CLOCK_MONOTONIC
Reference here:
https://pubs.opengroup.org/onlinepubs/009695399/functions/timer_create.html

DESCRIPTION
...
  Each implementation shall define a set of clocks that can be
  used as timing bases for per-process timers. All implementations
  shall support a clock_id of CLOCK_REALTIME.

  *** If the Monotonic Clock option is supported, implementations shall
  support a clock_id of CLOCK_MONOTONIC. ***
...

Change-Id: Ia8e7302ed4a7e9ec11a0059bd68e9674ea942001
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 15:01:36 -03:00
raiden00pl
728c3fc409 nrf52840-dk: add sx127x example configuration 2020-11-09 08:07:13 -08:00
Sara Souza
8a1960fdf4 Documentation for Watchdog Timer Driver 2020-11-09 08:06:10 -08:00
chao.an
8604e98196 unistd/sched_sporadic: correct the disable value
Reference here:
https://github.com/openbsd/src/blob/master/include/unistd.h

Change-Id: Ifb08a69c9a2a2b68179bcfd716fb180ec3577e54
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 09:11:51 -03:00
chao.an
182507f325 boards/sim: add atexit(2) into naming list
(gdb) b longjmp
Breakpoint 1 at 0x8270
(gdb) r
Starting program: /home/chao/code/m3/nuttx/nuttx
[    0.000000] Assertion failed at file:task/task_onexit.c line: 99

Breakpoint 1, 0xf7b905e0 in siglongjmp () from /lib/i386-linux-gnu/libc.so.6
(gdb)
(gdb) bt
|#0  0xf7b905e0 in siglongjmp () from /lib/i386-linux-gnu/libc.so.6
|#1  0xf7f9c3dc in siglongjmp_alias () from /lib/i386-linux-gnu/libpthread.so.0
|#2  0x5655d668 in up_assert (filename=0x56641018 "task/task_onexit.c", line=99) at sim/up_head.c:132
|#3  0x56567413 in _assert (filename=0x56641018 "task/task_onexit.c", linenum=99) at assert/lib_assert.c:36
|#4  0x565f8cfd in on_exit (func=0x565f8c12 <exitfunc>, arg=0x565fd780 <simuart_restoremode>) at task/task_onexit.c:99
|#5  0x565f8c89 in atexit (func=0x565fd780 <simuart_restoremode>) at task/task_atexit.c:109
|#6  0x565fd819 in simuart_start () at sim/up_simuart.c:112
|#7  0x5656c844 in up_uartinit () at sim/up_uart.c:496
|#8  0x5656ba7a in up_initialize () at sim/up_initialize.c:234
|#9  0x5655da56 in nx_start () at init/nx_start.c:701
|#10 0x5655d5e9 in main (argc=1, argv=0xffffd6f4, envp=0xffffd6fc) at sim/up_head.c:96

Change-Id: Ifd7196b2de7bf9fc7cea764c19a5c0eacf08fdb6
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 09:08:03 -03:00
chao.an
54d0c1c296 sys/uio: fix nxstyle warning
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 02:33:52 -08:00
chao.an
176d850445 sys/uio: include-able from C++ files
Change-Id: I4b512851fa96e1d696dbc886b25af4ab043da8dd
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 02:33:52 -08:00
chao.an
06d93828af sys/resource: fix nxstyle warning
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 02:22:34 -08:00