Commit Graph

145 Commits

Author SHA1 Message Date
hujun5
a96c6f1abf arch/arm: Add the secure handling to gic
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-08-21 00:06:25 +08:00
Xiang Xiao
7bb563dfe9 arch/arm: Remove CONFIG_ARCH_TRUSTZONE_BOTH related stuff
represent tee by CONFIG_ARCH_TRUSTZONE_SECURE instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-08-21 00:06:25 +08:00
chenrun1
709301cbfd hostfs:support SEEK_CUR
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2023-08-19 01:48:48 +08:00
Xiang Xiao
14563aa48c arch/armv7r: Sync gic/timer with armv7-a and armv8-a
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-14 14:51:01 -03:00
wangming9
c928acc9ff perf: The new configuration supports hardware performance counting
Adding the CONFIG_ARCH_PERF_EVENTS configuration to enable
hardware performance counting,solve the problem that some platform
hardware counting support is not perfect, you can choose to use
software interface.

This is configured using CONFIG_ARCH_PERF_EVENTS, so weak_functions
are removed to prevent confusion

To use hardware performance counting, must:
1. Configure CONFIG_ARCH_PERF_EVENTS, default selection
2. Call up_perf_init for initialization

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-12 02:20:44 +08:00
liaoao
dffab1e0c6 qemu: add devicetree support for arm64
Signed-off-by: liaoao <liaoao@xiaomi.com>
2023-08-11 00:46:50 +08:00
qinwei1
37e69cdeb0 arch/arm64: enable for arm64 virt to choice CPU core
Summary
    Qemu virt board can choice CPU core with boot parameter
and we need to add Konfig option for choice
    the change do this

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-10 20:48:19 +08:00
qinwei1
d8e1022b6f arm64: add hostfs support
Sumary
   add hostfs support for arm64, it's a copy
from arm32.

Note:
   it's not support for opendir and readdir, command
like ls will not work.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-10 17:58:34 +08:00
wangming9
f4e33e488d arch/arm64: Fixed arm64 backtrace support for other processes
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-10 13:35:59 +08:00
wangbowen6
9aa57b6c53 virtio: add virtio framework in NuttX
1. virtio devics/drivers match and probe/remote mechanism;
2. virtio mmio transport layer based on OpenAmp (Compatible with both
   virtio mmio version 1 and 2);
3. virtio-serial driver based on new virtio framework;
4. virtio-rng driver based on new virtio framework;
5. virtio-net driver based on new virtio framework
   (IOB Offload implementation);
6. virtio-blk driver based on new virtio framework;
7. Remove the old virtio mmio framework, the old framework only
   support mmio transport layer, and the new framwork support
   more transport layer and this commit has implemented all the
   old virtio drivers;
8. Refresh the the qemu-arm64 and qemu-riscv virtio related
   configs, and update its README.txt;

New virtio-net driver has better performance
Compared with previous virtio-mmio-net:
|                        | master/-c | master/-s | this/-c | this/-s |
| :--------------------: | :-------: | :-------: | :-----: | :-----: |
| qemu-armv8a:netnsh     |  539Mbps  |  524Mbps  | 906Mbps | 715Mbps |
| qemu-armv8a:netnsh_smp |  401Mbps  |  437Mbps  | 583Mbps | 505Mbps |
| rv-virt:netnsh         |  487Mbps  |  512Mbps  | 760Mbps | 634Mbps |
| rv-virt:netnsh_smp     |  387Mbps  |  455Mbps  | 447Mbps | 502Mbps |
| rv-virt:netnsh64       |  602Mbps  |  595Mbps  | 881Mbps | 769Mbps |
| rv-virt:netnsh64_smp   |  414Mbps  |  515Mbps  | 491Mbps | 525Mbps |
| rv-virt:knetnsh64      |  515Mbps  |  457Mbps  | 606Mbps | 540Mbps |
| rv-virt:knetnsh64_smp  |  308Mbps  |  389Mbps  | 415Mbps | 474Mbps |
Note: Both CONFIG_IOB_NBUFFERS=64, using iperf command, all in Mbits/sec
      Tested in QEMU 7.2.2

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
2023-08-10 03:39:39 +08:00
zhangyuan21
79242cc1e7 arm64: set cpuid according to mpidr
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-08-03 03:19:19 -07:00
zhangyuan21
dc55205ee5 arch/arm64: get_cpu_id according to the correct affinity level
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-08-03 03:19:19 -07:00
yanghuatao
51240c658f fix warning: [-Wunknown-pragmas]
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:33: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   33 | #pragma clang diagnostic push
      |
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:34: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   34 | #pragma clang diagnostic ignored "-Wpadded"
      |
In file included from /mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/types.h:4,
                 from /mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/IBase.h:4,
                 from android/hidl/base/1.0/BaseAll.cpp:1:
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:40: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   40 | #pragma clang diagnostic pop
      |
In file included from /mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/IBase.h:4,
                 from android/hidl/base/1.0/BaseAll.cpp:1:
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/types.h:188: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
  188 | #pragma clang diagnostic push
      |
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/types.h:189: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
  189 | #pragma clang diagnostic ignored "-Wc++17-extensions"
      |
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/types.h:195: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
  195 | #pragma clang diagnostic pop
      |
CXX:  LightRefBase.cpp In file included from base/HidlSupport.cpp:18:
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:33: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   33 | #pragma clang diagnostic push
      |
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:34: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   34 | #pragma clang diagnostic ignored "-Wpadded"
      |
In file included from base/HidlSupport.cpp:18:
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:40: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   40 | #pragma clang diagnostic pop

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2023-08-03 00:52:53 -07:00
zhangyuan21
8f39ba6ae4 arch: update g_running_tasks when context switch occurred
When supporting high-priority interrupts, updating the
g_running_tasks within a high-priority interrupt may be
cause problems. The g_running_tasks should only be updated
when it is determined that a task context switch has occurred.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-08-01 09:35:18 -07:00
Bowen Wang
28cb5e7984 arm64: add kasan support for arm64
Add kasan compiler option in arm64 Toolchain.defs

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2023-07-31 05:45:46 -07:00
zhangyuan21
f9cab5b9dc arch/arm64: add ARM64_DCACHE_DISABLE and ARM64_ICACHE_DISABLE config
Enable dcache and icache when ARM64_DCACHE_DISABLE and ARM64_ICACHE_DISABLE
disabled at __start.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-07-31 05:33:23 -07:00
Bowen Wang
d24622888f arm64_backtrace: use running_task if arch_get_current_tcb return NULL
In the init phase of the OS, arch_get_current_tcb return NULL. Enable
the memory backatrace default will crash in backtrace function.

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2023-07-31 04:52:49 -07:00
hujun5
68187b68af arch: move [enter|leave]_critical_section
move [enter|leave]_critical_section to the same place for easy to understand
and call matching

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-07-27 11:34:09 +02:00
guoshichao
3524f4b9ce libs/libc/fork: add lib_fork implementation
1. add lib_fork api in libs/libc, we need a fork() api to implement the
fork relative method, such as pthread_atfork
2. rename the assembly fork entry function name to up_fork(), and rename
the up_fork() to arch specific name, such as
sim_fork()/arm_fork()/mips_fork() etc.

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2023-07-26 10:41:52 +02:00
Xiang Xiao
46b25b3849 arch: Compute the array size by nitems
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-07-26 09:33:38 +02:00
Xiang Xiao
f3269a6caa sched: Rename DEBUG_TCBINFO to ARCH_HAVE_TCBINFO
and select if the arch support to define g_tcbinfo variable

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-07-26 09:33:38 +02:00
anjiahao
d5347d8915 arm64:fix ostest failed to run
The reason for the failure is incorrect sp,
resulting in the failure to restore the register

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-07-25 16:37:49 -03:00
anjiahao
8abf803a1d arm64:Need to store native sp pointer to tcb
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-07-23 21:59:35 -07:00
anjiahao
ceb6bb6650 arm64:support arm64 for tcb info
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-07-23 21:59:35 -07:00
chao an
4b94dc3092 toolchain/gcc: fix linker error if enable STACK_CANARIES/LTO at same time
If -fstack-protector-all is enabled, gcc linker will need GCC
SSP(Stack Smashing Protector) support, Since the implement of SSP
is related to the OS, most of embedded toolchain does not provide
ssp support, so an error will be reported when linking:

enable CONFIG_LTO_FULL && CONFIG_STACK_CANARIES

arm-none-eabi/bin/ld: cannot find -lssp_nonshared: No such file or directory
arm-none-eabi/bin/ld: cannot find -lssp: No such file or directory

https://github.com/gcc-mirror/gcc/blob/master/gcc/gcc.cc#L983-L985

Since nuttx has already implemented SSP related hook functions,
so in this PR, we filter out this option in the link phase to ensure that
the implementation of lssp/lssp_nonshared will not be referenced

Signed-off-by: chao an <anchao@xiaomi.com>
2023-07-21 01:13:34 +08:00
zhangyuan21
b7216d54ff arm64: Use the correct cpu id for fpu idle task init
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-07-14 01:17:02 +08:00
simbit18
b0965ab963 Fix nuttx coding style
Remove TABs
Fix indentation
Fix Multi-line comments
Fix Comments to the Right of Statements.
2023-07-14 01:16:06 +08:00
zhangyuan21
601202ee4a arm64: Use the correct aff in up_affinity_irq function
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-07-14 01:13:01 +08:00
guoshichao
c33d1c9c97 sched/task/fork: add fork implementation
1. as we can use fork to implement vfork, so we rename the vfork to
fork, and use the fork method as the base to implement vfork method
2. create the vfork function as a libc function based on fork
function

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2023-07-12 02:27:37 +08:00
yanghuatao
4d9f67940c nuttx/toolchain: Add macro _LDBL_EQ_DBL to nuttx/arch/arm64/src/Toolchain.defs
Fix goldfish build toolchain math library error:
/mnt/yang/vela_Goldfish/nuttx/include/libcxx/cmath:454:9: error: 'nexttowardf' has not been declared in '::'
  454 | using ::nexttowardf;
      |         ^~~~~~~~~~~
/mnt/yang/vela_Goldfish/nuttx/include/libcxx/cmath:472:9: error: 'acosl' has not been declared in '::'
  472 | using ::acosl;
      |         ^~~~~
/mnt/yang/vela_Goldfish/nuttx/include/libcxx/cmath:473:9: error: 'asinl' has not been declared in '::'
  473 | using ::asinl;
      |         ^~~~~

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2023-07-11 00:44:45 +08:00
Masayuki Ishikawa
9861d49cd4 arch: arm64: Add arm64_gic_raise_sgi() for SMP
Summary:
- I noticed that arm64_gic_raise_sgi() is not implemented for
  GICv2 which is used for SMP + hypervisor such as qemu + kvm.
- This commit fixes this issue

Impact:
- None

Testing:
- Tested with qemu-7.1 + kvm (linux) and qemu-7.1 + hvf (macOS)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-06-30 16:10:26 +08:00
Masayuki Ishikawa
745f443cbf arch: arm64: Fix to access psci with hypervisor
Summary:
- I noticed that pcsi version can not be obtained with qemu + kvm.
- Also, pci_detect hangs with qemu + hvf.
- This commit fixes this issue by using hvc (hypervisor call).

Impact:
- None

Testing:
- Tested with qemu-7.1 + kvm (linux) and qemu-7.1 + hvf (macOS)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-06-30 16:10:26 +08:00
Masayuki Ishikawa
cf6a134684 arch: arm64: Do not set cntfrq_el0 in qemu_boot.c
Summary:
- During testing with qemu + kvm, I noticed that nuttx hangs
  when setting cntfrq_el0. With qemu + kvm, it starts from
  EL1 because we can not specify virtualization=on
- However, I noticed that it works without setting cntfrq_el0
- This commit fixes this issue

Impact:
- None

Testing:
- Tested with qemu-7.1 (both with kvm and without kvm)
- NOTE: to work with kvm, GICv2 must be used.

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-06-29 20:11:29 +08:00
zhangyuan21
6f8cb7edd3 arch/arm64: Save FPU context when a context switch occurs in SMP mode
In SMP mode, the fpu owner may switch from core0 to core1,
so it is necessary to force saving the FPU context when a
context switch occurs.

This PR fixed the crash issue mentioned in #8799.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-06-13 13:23:28 +09:00
Peter Bee
59450bf9a9 arch/arm64: use adrp instead adr in bss init code
To support address offset larger than 1MB

Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
2023-06-02 11:02:14 -03:00
Masayuki Ishikawa
ec788d9398 arch: fvp-v8r: Fix warning when configuring fvp-armv8r:nsh_smp
Summary:
- I noticed that ./tools/configure.sh fvp-armv8r:nsh_smp shows
  warning: (ARCH_CHIP_FVP_R52 && ARCH_CHIP_FVP_R82) selects ARMV8R_HAVE_GICv3 which has unmet direct dependencies (ARCH_ARM && ARCH_ARMV8R)
- I think ARMV8R_HAVE_GICv3 is only used for aarch32.
- This commit fixes this issue.

Impact:
- None

Testing:
- Tested with nsh_smp on FVP

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-06-02 12:08:27 +08:00
zhangyuan21
9b882b46be arch/arm64: move sgi attach and enable to gic init
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-21 09:58:34 -03:00
zhangyuan21
f8b5fd2a9a arch/arm64: send sgi with correct aff and target list
armv8r and armv8a have different process affinity,
and sgi affinity needs to be able to adapt all of them.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-21 09:58:34 -03:00
qinwei1
ea98e5a92e arm64: gicv3 add arm64_gic_irq_trigger to set irq type
Summary
    For ARM64, it need to set IRQ type(EDGE or LEVEL). it's specific
 for ARM64 PPI or SPI.
    The change add arm64_gic_irq_trigger to set IRQ type

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-05-21 09:58:34 -03:00
qinwei1
ca6cdd16e9 arm64: gicv3 add up_affinity_irq/up_trigger_irq/up_prioritize_irq
Summary
  add up_affinity_irq/up_trigger_irq/up_prioritize_irq for gicv3
these interface is necessary for some drivers

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-05-21 09:58:34 -03:00
qinwei1
28a354f276 arm64: gicv3, add power up sequence for gc600/gc700
Summary:
   GICR_PWRR is a IMPLEMENTATION-DEFINED register for gc700/gc600, which
is following gic v3 and v4.
   Please check GICR_PWRR define at TRM of GIC600/GIC700 for more detail

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-05-21 09:58:34 -03:00
Xiang Xiao
7990f90915 Indent the define statement by two spaces
follow the code style convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-21 09:52:08 -03:00
zhangyuan21
36acd4fce5 arch/arm64: .bss initialization using assembly language
The compiler will optimize boot_early_memset to memset,
but memset in libc cannot be used before MMU is enabled.
Therefore, assembly language is used to implement the
initialization of bss to avoid this problem.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-19 21:38:07 -07:00
zhangyuan21
548424713b arch/arm64: Each core initializes its own idle stack in SMP
When the MMU/MPU of core0 is enabled while those of other cores are not,
it is unsafe to operate the idle stack simultaneously. The idle stack
of other cores will be flushed by the contents in the cache of core0,
therefore it is necessary to initialize the idle stack and let each
core handle it on its own.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-19 17:41:48 +08:00
zhangyuan21
4466c3d6e9 arm64/cache: Support unalign cache clean.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-18 15:45:42 +03:00
Xiang Xiao
7dc0d70092 arch: Save sigdeliver into xcp in the case of signal self delevery
to avoid the infinite recusive dispatch:
*0  myhandler (signo=27, info=0xf3e38b9c, context=0x0) at ltp/testcases/open_posix_testsuite/conformance/interfaces/sigqueue/7-1.c:39
*1  0x58f1c39e in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:167
*2  0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*3  0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:115
*4  0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:435
*5  0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*6  0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*7  0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*8  0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:115
*9  0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:435
*10 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*11 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*12 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*13 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:115
*14 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:435
*15 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*16 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*17 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*18 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:115
*19 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:435
*20 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*21 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*22 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*23 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:115
*24 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:435
*25 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*26 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*27 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*28 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:115
*29 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:435
*30 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*31 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-17 11:53:18 -06:00
Lee Lup Yuen
4ed48c33e9 arm64/a64: Add support for Multiple UART Ports
Currently only Port UART0 is supported for Allwinner A64. This PR adds support for all UART Ports: UART1 to UART4. (Except R-UART, which is a special low-power UART)

This is required for the upcoming LTE Modem Driver (Quectel EG25-G) for PINE64 PinePhone, which uses UART3. [(Details here)](https://lupyuen.github.io/articles/lte2)

The code was adapted from the NuttX UART Driver for Allwinner A1X: [`a1x_serial.c`](https://github.com/apache/nuttx/blob/master/arch/arm/src/a1x/a1x_serial.c)

`arch/arm64/src/a64/a64_serial.c`: Added ports UART1 to UART4, based on [`a1x_serial.c`](https://github.com/apache/nuttx/blob/master/arch/arm/src/a1x/a1x_serial.c)

`arch/arm64/src/a64/a64_serial.h`: Added IRQs for UART1 to UART4. Moved UART Base Addresses to `a64_memorymap.h`

`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added UART Base Addresses for UART0 to UART4

`arch/arm64/src/a64/Kconfig`: Added UART1 to UART4 to Allwinner A64 Peripheral Selection menu

`boards/arm64/a64/pinephone/configs/lcd/defconfig`, `lvgl/defconfig`, `nsh/defconfig`, `sensor/defconfig`: Fixed `UART1_SERIAL_CONSOLE` to `UART0_SERIAL_CONSOLE`
2023-05-11 09:41:18 +02:00
hujun5
6e71527af2 arch/arm64: 64 bit platform compile error reported
compile error log:
common/arm64_arch_timer.c: In function 'arm64_tick_max_delay':
common/arm64_arch_timer.c:178:12: error: conversion from 'long unsigned int' to 'clock_t' {aka 'unsigned int'} changes value from '18446744073709551615' to '4294967295' [-Werror=overflow]
  178 |   *ticks = UINT64_MAX;
      |            ^~~~~~~~~~

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-10 09:06:59 +02:00
hujun5
7f4cb3057a arch/arm64: merge serial_pl011.c and qemu_serial.c
At present, the serial drivers qemu_serial.c and serial_pl011.c on the fvp-v8r and qemu platforms in arm64 are duplicated
and need to be merged. The plan is to place them under the drivers\serial directory to create a common code module,
so that both fvp-v8r and qemu can use the same code.
In the future, if new platforms use pl011 serial ports, they can also be directly reused

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-10 09:06:59 +02:00
qinwei1
2eac660ff6 arm64: Updating ARCH_EARLY_PRINT support
Summary:
  Keeping this option out of depend on any common serial.
Using the option, need to implement xxx_lowputc.S/c.
  You can also logging the booting message through rewriting
fake arm64_lowputc with other debug method (eg semihosting,
ARM debug channel etc).

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-05-09 21:00:48 +08:00