4 Commits

Author	SHA1	Message	Date
Ville Juven	74702085f0	defconfigs: Add SCHED_HAVE_PARENT=y to configs with WAITPID && BUILD_KERNEL ... The added depencendy broke some of the defconfigs	2024-06-03 18:00:40 +02:00
Stuart Ianna	1f02c05c6d	arch/litex/litex_arch_alarm: Support tickless schedular with arch alarm. ... This provides an alternate tickless scheduling method, which uses the riscv mtimer as a timebase, allowing the time and timeh registers to used throughout an application. The exiting tickless method, using Litex's timer0 has been left in place, as it is a more performant option, but currently has the potential issue identified in #11189.	2024-05-31 10:21:44 +08:00
Stuart Ianna	50f0fd4df2	risc-v/litex: Add system reset and access to core control registers.	2023-08-25 17:16:28 +08:00
Stuart Ianna	34bfa2f7ba	arch/risc-v/litex: Add platform specific tickless implementation. ... Adds a platform specific implementation for tickless schedular operation. This includes: - Tickless operation for vexriscv cores. - Tickless operation for vexriscv-smp cores. - Ticked operation for vexriscv-smp cores. Ticked operation for vexriscv core has been refactored. Additional default configuration added to demonstrate operation. Both tickless and ticked options use Litex timer0 for scheduling intervals. This is significantly faster than interfaceing with the risc-v mtimer through opensbi.	2023-08-16 16:59:27 +08:00