Reproduce:
configure:
./tools/configure.sh qemu-armv7a:nsh -j8
open kasan:
CONFIG_MM_KASAN=y
run:
qemu-system-arm -cpu cortex-a7 -nographic -machine virt,virtualization=off,gic-version=2 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
error:
run hanged
Rootcause:
In Qemu armv7a, the ram-end reserved for MMU PGTABLE:
And the up_allocate_heap() directly use the ram-end for heap in arch/arm/src/common/arm_allocateheap.c
*heap_size = CONFIG_RAM_END - g_idle_topstack;
Then they are conflict.
Usually, we won't use the heap end, so can't find the error.
BUT, the KASAN will use the heap end for shadow, so found the error.
Resolve:
up_allocate_heap() consider of MMU, re-define the RAM_END at chip.h
Signed-off-by: ligd <liguiding1@xiaomi.com>
This commit adds support for TX DMA transfers for USART peripheral. Code
refactor in sam_serial.h was also required in order to have correct
defines for all possible cases (both RX and TX DMA used, just one used,
none used).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
When an application is being loaded `up_addrenv_create ` calls
`create_region` to create the address environment. Only the first
entry is mapped when the region is created. Virtual memory that is
not mapped will trigger an exception when accessed. Other memory
pages are allocated and mapped on-demand. This enables setting
larger heap and stack for the process without compromising the
overall system memory.
Current `CONFIG_PAGING` refers to an experimental implementation
to enable embedded MCUs with some limited RAM space to execute
large programs from some non-random access media.
On-demand paging should be implemented for the kernel mode with
address environment implementation enabled.
Previously we need turn off the PMP locks in K230 vendor u-boot to use
NuttX, this complicates the setup process. This patch supports running
NuttX with original vendor u-boot so that to reduce setup complexity.
It also enables empty NSH prompt string in AMP master config as the apps
side support is ready.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
cpu0 thread0: cpu1:
sched_yield()
nxsched_set_priority()
nxsched_running_setpriority()
nxsched_reprioritize_rtr()
nxsched_add_readytorun()
up_cpu_pause()
IRQ enter
arm64_pause_handler()
enter_critical_section() begin
up_cpu_paused() pick thread0
arm64_restorestate() set thread0 tcb->xcp.regs to CURRENT_REGS
up_switch_context()
thread0 -> thread1
arm64_syscall()
case SYS_switch_context
change thread0 tcb->xcp.regs
restore_critical_section()
enter_critical_section() done
leave_critical_section()
IRQ leave with restore CURRENT_REGS
ERROR !!!
Reason:
As descript above, cpu0 swith task: thread0 -> thread1, and the
syscall() execute slowly, this time cpu1 pick thread0 to run at
up_cpu_paused(). Then cpu0 syscall execute, cpu1 IRQ leave error.
Resolve:
Move arm64_restorestate() after enter_critical_section() done
This is a continued fix with:
https://github.com/apache/nuttx/pull/6833
Signed-off-by: ligd <liguiding1@xiaomi.com>
Use private naming to avoid conflicts with user applications
In file included from libuv/src/unix/internal.h:25,
from libuv/src/unix/udp.c:23:
libuv/src/uv-common.h:57: warning: "container_of" redefined
57 | #define container_of(ptr, type, member) \
|
In file included from nuttx/include/nuttx/list.h:47,
from nuttx/include/nuttx/tls.h:40,
from nuttx/include/nuttx/sched.h:48,
from nuttx/include/nuttx/arch.h:87,
from nuttx/include/nuttx/userspace.h:35,
from nuttx/include/nuttx/mm/mm.h:30,
from nuttx/include/nuttx/kmalloc.h:34,
from nuttx/include/nuttx/lib/lib.h:31,
from nuttx/include/stdio.h:35,
from apps/system/libuv/libuv/include/uv.h:59,
from libuv/src/unix/udp.c:22:
nuttx/include/nuttx/nuttx.h:48: note: this is the location of the previous definition
48 | #define container_of(ptr, type, member) \
|
Signed-off-by: chao an <anchao@lixiang.com>
change optimization to -Os for CONFIG_DEBUG_FULLOPT to be compatible with other architectures
and add an option to select CONFIG_DEBUG_CUSTOMOPT
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
enable FPU and implement up_fpucmp to pass ostest
With aggressive optimization enabled (-O2/-O3), ostest FPU test will fail.
This is because the compiler will generate additional vector
instructions between subsequent up_fpucmp() calls (loop vectorization
somewhere in usleep() call), which will consequently overwrite
the expected FPU context (XMM registers).
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
1. Fix issue of system blocking due to disable dcache.
2. Support Ext-SRAM-Cache mmu mapping in SMP mode.
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
__revoke_low_memory() is called in intel64_lowsetup()
fixes b4b96a6435 (PR #11758) in which the multiboot2 header was accessed
after revoking the low memory which caused page fault.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
BSS nulling can now be optimized by the compiler, so it is necessary
to enable SSE instructions early in __nxstart
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
The stack pointer must be aligned to 16 bytes, otherwise the system crash on the first unaligned data access with vector instruction.
The problem is only observable with optimization enabled, when vector instructions are generated.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
this is a follow up to the change from 2335b69120 which missed
updating stack frame length for this memset
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
During removal of F1 related stuff, code that configures FLASH
latency was removed, which rendered some of the F3 line unbootable.
It was done by mistake, since previous removed block was
'#ifdef VALUE_LINE', and block with FLASH code was '#ifndef VALUE_LINE'
and so it should not have been removed.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
Add support for tricore TC397
1. Porting based on AURIX TC397 KIT_A2G_TC397_5V_TFT evaluation board
https://www.infineon.com/cms/en/product/evaluation-boards/kit_a2g_tc397_5v_tft/
2. In order to avoid license and coding style issues, The chip-level code
still uses the implementation of AURIX Development Studio SDK.
The SDK package will be downloaded as a third-party package during compilation:
https://github.com/anchao/tc397_sdk
3. Single core only, SMP implementation will be provided in the future.
4. Implemented the basic System Timer, ASCLIN UART driver.
5. Only the Tasking tool chain is supported (ctc/ltc, license maybe required)
6. 'ostest' can be completed on the TC397 development board.
How to run?
1. Setup the tasking toolchain and license
$ export TSK_LICENSE_KEY_SW160800=d22f-7473-ff5d-1b70
$ export TSK_LICENSE_SERVER=192.168.36.12:9090
2. Build nuttx ELF
$ ./tools/configure.sh tc397/nsh
$ make -j
...
artc I800: creating archive libc_fpu.a
LD: nuttx
3. Switch to windows PC, setup AURIX-studio to Debugger Launcher
4. Replace runing ELF to nuttx, and re-download ELF
Signed-off-by: chao an <anchao@lixiang.com>
This patch adds inter-processor interrupt support using K230 mailbox
device to improve the RPMsg efficiency. The polling logic has been
dropped.
Major changes:
- in arch/risc-v/include/k230:
- irq.h add IRQ for IPI devices
- in arch/risc-v/src/k230:
- Kconfig add IPI related config, increase polling delay
- Make.defs add k230_ipi.c to CHIP_SRCS
- k230_hart.c fix typo, add notes of zero MISA reading w/ NUTTSBI
- k230_irq.c use K230_PLIC_IRQS as ext IRQ limit to support IPI
- k230_rptun.c use IPI instead of polling
- in boards/risc-v/k230/canmv230/configs
- master enable IPI support
- remote enable IPI, TMPFS, RPMSGFS etc
New additions:
- in arch/risc-v/src/k230:
- k230_ipi.h add K230 IPI related defintions
- k230_ipi.c add K230 IPI driver
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
-- Detecting CXX compile features
-- Detecting CXX compile features - done
arm-none-eabi-gcc: error: -Wstrict-prototypes: No such file or directory
arm-none-eabi-gcc: error: -Wstrict-prototypes: No such file or directory
-- Configuring done
-- Generating done
Signed-off-by: chao an <anchao@lixiang.com>
The board's microphone uses 24-bit i2s and this commit also fixes
the segmentation fault caused by the audio buffer overflow.
arch/xtensa/src/esp32/esp32_i2s.c: Fix bug regarding 24-bit audio and add AUDIOIOC_STOP to ioctl
drivers/audio/audio_i2s.c: Report number of channels on AUDIOIOC_GETCAPS
in boards/xtensa/esp32/esp32-sparrow-kit:
/configs/nsh/defconfig: Add I2S configs
/src/esp32-sparrow-kit.h: Add the signature of esp32_i2sdev_initialize()
/src/esp32_bringup.c: Add call to esp32_i2sdev_initialize()
Signed-off-by: simonatoaca <simona.alexandra2000@gmail.com>
This commit implements the RMT peripheral for all the supported
Espressif's RISC-V devices. It also implements the support for the
WS2812 addressable RGB LED using the RMT peripheral.
WS2812 data is encoded into RMT items according to the RMT clock
source. This commit makes it by using the actual clock source in
spite of a pre-defind value.
- remove read-write logic - this should be handled by radio protocol implementation
- remove EVENTS and TASKS bit definitions - we can just use a signle definition
- add more radio ops
- fix frequency configuration
- fix printf warnings
- fix radio reset
I noticed when executing pwm STOP command in
multichannel mode, the channel still outputting.
This commit fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
I noticed when executing pwm STOP command in
multichannel mode, the channel still outputting.
This commit fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
I noticed when executing pwm STOP command in
multichannel mode, the channel still outputting.
This commit fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
This patch revises `k230_hart.[ch]` by:
- revising big core boot/stop control.
- making k230_hart_is_big() available in S-mode.
- adding more comments.
This patch also revises the `ld-kernel.script` so that to match the
latest MMU pgtable design.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
K230 chip has two T-Head C908 RiscV cores, previously we run NuttX
on either little or big cores. This patch runs NuttX on both cores
with OpenAMP support via the RPTUN driver.
New additions:
- in arch/risc-v/src/k230
- k230_rptun.c K230 RPTUN driver
- k230_rptun.h K230 RPTUN driver header file
- in baords/risc-v/k230/canmv230
- configs/master Build config for master node
- configs/remote Build config for remote node
- scripts/ld-rptun.script Build script for RPTUN
Major changes:
- arch/risc-v/Kconfig Select NUTTSBI_LATE_INIT upon NUTTSBI
- in arch/risc-v/include
- k230/irq.h Add UART3 IRQ defs
- in arch/risc-v/src/k230
- Kconfig Add RPTUN related config items
- Make.defs Add k230-rptun.c to sources
- hardware/k230_memorymap.h Add K230 device and CSR defs
- k230_hart.c Add hart ctrl for RPTUN
- k230_hart.h Add hart ctrl for RPTUN
- k230_mm_init.c Add Svpmbt to support RPTUN
- k230_start.c Revised to support RPMsg UART
- in boards/risc-v/k230/canmv230
- scripts/Make.defs Add RPTUN script selection
- src/canmv_init.c Add RPTUN and RPMsg_UART initialization
- in Documentation/platforms/risc-v/k230/boards/canmv230
- index.rst Add AMP usage information.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
I recently imported NuttX version 6.0 (and nsh) into a Microchip
Studio project [1] on Windows to figure out what was going wrong with
the avr32dev1 build. I also briefly checked NuttX version 10.
I worked with the assumption that the avr32 (avr32dev1) specific
changes to the codebase were minimal across NuttX releases.
For the initial proof of concept I used Microchip Studio version 7.0
(with the recent Microchip's ASF updates). I use avr32-gcc (4.4.7)
hosted here [2] for building NuttX for avr32dev1 on GNU/Linux.
Even with the Microchip Studio project, I had initial debug problems
with just stepping through the code a line at a time. I had to bring
in crt0, a trampoline stub and the linker file from one of my older
projects to really build on the suspicion I had with the linker file.
Perhaps an older version of avr32-gcc did something differently. I am
not sure about this. I used avr32-objdump to see the output sections
of the generated elf file. I just had to tweak the linker script to
ensure correct linking of the sections.
With those changes, I was able to inspect the UART sections within
NuttX Microchip Studio project.
Second important change: the transmit pin: I had to reassign the pin
to see the nsh console.
These are the currently assigned UART pins:
RX: PA_24 -> Physical IC pin 59
TX: PB_02 -> Physical IC pin 24
For the avr32dev1 board, they are pins: J1 (berg pin 28) and J2 (berg
pin 10).
In addition, the PR fixes silly compilation problems with avr32dev1.
I have tested the nsh build with my avr32dev1 boards. I used Atmel ICE
to program one of them (flash at 0x80000000) and dfu-programmer to
test my other board (flash at 0x80002000). The other RS-232 parameters
are the same as they were.
References:
[1]: https://github.com/ramangopalan/nuttx_avr32dev1
[2]: https://github.com/ramangopalan/avr32-gnu-toolchain-linux_x86_64
SAMv7 reset controller stores the cause of last reset (SW reset, power up,
pin reset etc.) in status register. This commit adds function that allows
the board to retrieve this information. This function should be called
from board support layer either during initialization or based on
incoming ioctl call.
Adding the sam_get_reset_cause() to sam_systemreset.c also resulted in
always compiling this file by default and only putting up_systemreset()
under CONFIG_SAMV7_SYSTEMRESET option.
Also header file sam_systemreset.h was created as it defines reset types
in comfortable manner for future processing in board layer. This is done
to avoid passing boardctl dependent structure to architecture layer.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
By setting "isconsole" to false, mpfs_serial stops outputting to console.
This can be used to disable output to debug console in low level.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
It is possible that a PLIC IRQ is claimed but not completed at warm
reset. This occurs at least if there is a fault in the middle of irq
handler execution.
To recover from such situation, we can complete all IRQ:s in PLIC;
this completes any already claimed IRQ, but has no effect on IRQs
which are not claimed or not enabled.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
- Use mpfs_i2c_deinit+mpfs_i2c_init sequence to re-initialize i2c block
- Use the i2c mutex to protect the reset; in case there are several devices
on the same bus, and one of them resets the bus, reset must not occur in
the middle of another device's transfer.
- Move irq attach to the i2c_init as the irq detach is in i2c_deinit
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Ensure that there are no pending state or interrupts in the i2c controller. This removes
errors caused by deinitialize/initialize sequences in error cases.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Replace risky DEBUGASSERT()s with real sanity checks. Also,
do a few more checks as the system might occasionally fire an
interrupt if the system has been restarted while in middle of
an i2c transaction.
Yet, modify i2c_transfer() function so that up_disable_irq()
is always called at the end to better prevent ill-timed irqs.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
priv->msgid may grow past its boundaries, causing
struct i2c_msg_s *msg = &priv->msgv[priv->msgid]
to read data out of boundaris.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
As long as the GNSS feature is not used, GNSS RAM can be used as general memory.
This memory is 640KByte total, which is lower performance than the application RAM.
It is possible to locate text, data and bss into GNSS RAM and to use as heap area.
Current mmu_flush_cache() hook lacks the reg param which needed by
some targets. So this PR adds the param and update existing targets
using that hook.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Enable with ./tools/configure.sh -l esp32-devkitc:dac
DAC channel 0 = GPIO 25
DAC channel 1 = GPIO 26
default path: /dev/dac0
Resolution 8 bits = values 0~255
Voltage: 0~Vref
The reference voltage 'Vref' here is input from the pin VDD3P3_RTC
which ideally equals to the power supply VDD (3.3V).
Weak function sometimes can't have strong implementation linked.
This patch uses NUTTSBI_LATE_INIT config and normal function instead
to avoid those issues.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
The RPTUN_PING option has been replaced by RPMSG_PING but this
use for PERF_EVENTS is left behind, so replace it here as well.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Previously NuttX runs on little core of K230, this patch allows NuttX to
run on the big core as well.
Within folder `arch/risc-v/src/k230`:
- Changes:
- CMakeLists.txt add k230_hart.c to sources list
- Make.defs add k230_hart.c to sources list
- chip.h add inclusion to k230_hart.h etc
- k230_irq.c move sbi_late_init() to k230_hart.c
- k230_start.c add support to run on big core
- hardware/:
- k230_memorymap.h add T-Head C908 specific CSR
- Additions:
- k230_hart.c sbi_late_init w/ hart initialization
- k230_hart.h header file
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
add defintions for vector extension and additional user-mode
extension fields for MSTATUS and SSTATUS registers.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Adding CMakeLists.txt files to support CMake build system.
Note that only FLAT build works now due to limitations of current
CMake build system.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
SAMA5D2 has UART (TX/RX only) and FLEXCOM USART (with control pins).
UART has only TX/RX, so if I try to use flow control with FLEXCOM USART,
there is no register definition on the UART side and get a compilation error.
Signed-off-by: Takeyoshi Kikuchi <kikuchi@centurysys.co.jp>
Commit 03e5c02 introduced option to have both standard SPI and QSPI
in SPI mode on one system. However this change broke the appearance of
QSPI driver configuration menu entry in menuconfig as it was dependent
on !SAMV7_QSPI_IS_SPI (which is now true for all MCUs having standard
SPI ability in QSPI driver).
This change makes sure the menu is correctly shown when QSPI driver
used.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This adds support for creating an early frame buffer and primatives for
writing to this frame buffer as a console. This does require the font
infrastructure as well as multiboot2.
Additionally this can now be used with a UEFI bootloader long as it
boots NuttX via Multiboot2. There does seem to be a PCI interrupt
issue when running in UEFI mode.
I was able to boot my laptop using this and see PCI devices enumerate.
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
x86_64: Add conditionals around the multiboot framebuffer
After warm reset the interrupt source in the HW block is not explicitly
cleared, thus once the interrupt source is enabled the old / stale interrupt
fires immediately.
This causes a DEBUGASSERT() failure on line 808 mpfs_spi_unload_rx_fifo:
DEBUGASSERT(nwords > 0);
This commit fixes building native MCUboot from sources by getting
the required sources from `esp-hal-3rdparty` repository and enable
building MCUboot and using it as the 2nd stage bootlaoder.
- A pre-built IDF bootloader is used by default;
- `ESP32C3_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32C3_PARTITION_TABLE.
- A pre-built IDF bootloader is used by default;
- `ESP32S3_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32S3_PARTITION_TABLE.
- A pre-built IDF bootloader is used by default;
- `ESP32S2_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32S2_PARTITION_TABLE.
- A pre-built IDF bootloader is used by default;
- `ESP32_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32_PARTITION_TABLE.
Simple boot is a method of booting that doesn't depend on a 2nd
stage bootloader. Please note that some of the ESP-IDF bootloader
features are not available using simple boot, such as partition
tables and OTA: most of these features are implemented in NuttX
and MCUboot.
This commit refactors DAC driver. The functionality remains the same
but driver start up is now done in dac_setup (after application called
open function) instead of sam_dac_initialize (called from BSP). This
ensures that driver does not take resources (timer, interrupt) until
opened. Implementation of dac_shutdown is also provided, therefore
the driver frees resources once closed.
This change is consistent with other drivers implementation.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
USART peripheral can work in SPI mode as well. This commit adds support
for such functionality. Only 1 slave device is supported by the
peripheral therefore board level does not have to ensure correct CS
setup.
The usage of the peripheral is the same as with other SPI drivers.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.
This commit also makes this bootloader configuration as default
for esp32c3-generic target and removes the need for running
'make bootloader' command for it.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
Ox64 BL808 crashes with a Page Fault when we run `getprime` then `hello`. This is caused by the T-Head C906 MMU incorrectly accessing the MMU Page Tables of the Previous Process (`getprime`) while starting the New Process (`hello`).
To fix the problem, this PR flushes the MMU Cache whenever we point the MMU SATP Register to the New Page Tables. We execute 2 RISC-V Instructions that are specific to T-Head C906:
- DCACHE.IALL: Invalidate all Page Table Entries in the D-Cache
- SYNC.S: Ensure that all Cache Operations are completed
This is derived from the T-Head Errata for Linux Kernel. More details here: https://lupyuen.github.io/articles/mmu#appendix-flush-the-mmu-cache-for-t-head-c906
Modified Files:
- `arch/risc-v/src/common/riscv_mmu.h`: If needed, `mmu_write_satp()` calls `mmu_flush_cache()` (weak function) to flush the MMU Cache. (Like for T-Head C906)
- `arch/risc-v/src/bl808/bl808_mm_init.c`: Flush the MMU Cache for T-Head C906. Extend `mmuflags` from 32-bit to 64-bit to be consistent with `mmu_ln_setentry()`.
- `boards/risc-v/bl808/ox64/configs/nsh/defconfig`: Enable `ostest` in the Build Config. Update `CONFIG_BOARD_LOOPSPERMSEC` according to `calib_udelay`.
Ubuntu stock toolchain `gcc-riscv64-unknown-elf` complains about
current CMake system (see issue#11573). This tries to fix it so
that both newer XPack and stock toolchains can be used with CMake.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
If a TX DMA completion interrups a forground write.
The TX DMA completion can start a dma_send and it will
then followed by the forground write's dma_send
stoping the,then in progress DMA.
By atomicaly marking the tx dma busy, the forground
write will not perform the dma_send, and will only
enqueue the data. At the next TX dma completion any
data pending in the tx queue will be sent
ESP32 is supported on NuttX starting from chip revision 3.0. This,
however, didn't prevent the user from using older chip revisions,
which caused unexpected behaviors. This commit checks chip revision
before finishing booting NuttX.
This commit is intended to update the EFUSE's register content and
update related configs:
- Remove duplicated configs from `esp32_soc.h`;
- Add missing header files from APB registers;
- Add missing macro definitions from EFUSE;
- Update related code to use the new macros;
The logic of the conditional expression that determines whether
the QH is a target QH or not is reversed in the process of canceling
a transfer in INPROGRESS state.
Therefore, the QH in INPROGRESS state is not released and subsequent
communication is not successful.
Checked with CDC-ACM driver and cu command.
Signed-off-by: Takeyoshi Kikuchi <kikuchi@centurysys.co.jp>
To avoid build break:
ld: riscv-none-elf/lib/rv64imafdc_zicsr/lp64d/crt0.o: in function `.L0 ':
(.text+0x8): undefined reference to `__bss_start'
ld: (.text+0x10): undefined reference to `_end'
ld: (.text+0x36): undefined reference to `main'
collect2: error: ld returned 1 exit status
Signed-off-by: chao an <anchao@lixiang.com>
Newly added logging in `sched/task_exit.c` obsoletes the existing
ones in `arch/up_exit()`, thus remove the latter to reduce duplications.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Previously k230 kernel build needs OpenSBI wrapping for use on
target, thus leading to larger program and memory overheads.
This patch adds alternative small overhead kernel build support.
Changes:
- in arch/risc-v/src/k230:
- k230_head.S entrance renamed for sake of NUTTSBI
- k230_irq.c add M-mode handling for NUTTSBI case
- k230_mm_init.c add L3 table for smaller RAM case
- hardware/k230_plic.h add PLIC_CTRL definition
- Make.defs use CHIP_ASRCS to fix entrance selection
- in boards/risc-v/canmv230/scripts:
- Make.defs add support for NUTTSBI case
Additions:
- in boards/riscv/canmv230/:
- scripts/ld-nuttsbi.script link script for NUTTSBI case
- configs/nsbi/defconfig config for NUTTSBI case
The artifact nuttx.bin from this configuration can be used directly
on target as OpenSBI wrapping is not needed.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
fix typo
new options to enable toolchain support for quadruple precision
(128 bits or 16 bytes) floating point if both the toolchain and
the hardware support it.
Signed-off-by: chao an <anchao@lixiang.com>
Some devices have special preparations before entering S-mode, thus
a hook is needed from NUTTSBI to give them the chance.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Chips like K230 has ARCH_RV64 but only supports 32-bit MMIO. So using
ARCH_RV_MMIO_BITS is more proper here.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This is not the right place to modify DMA memory protection values.
Why not? These are designed to protect other AMP mode instances. Opening
the entire SoC's memory for the USB DMA kind of defeats this purpose.
Also, the driver cannot know how to configure these registers correctly,
only opening up the whole SoC "works".
armv8-r/arm_gicv3.c: In function 'gic_validate_dist_version':
armv8-r/arm_gicv3.c:730:9: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'uint32_t' {aka 'long unsigned int'} [-Wformat=]
730 | sinfo("GICD_TYPER = 0x%x\n", typer);
| ^~~~~~~~~~~~~~~~~~~~~ ~~~~~
| |
| uint32_t {aka long unsigned int}
armv8-r/arm_gicv3.c:730:26: note: format string is defined here
730 | sinfo("GICD_TYPER = 0x%x\n", typer);
| ~^
| |
| unsigned int
| %lx
Signed-off-by: chao an <anchao@lixiang.com>
Fully linked apps take less storage and are efficient to load. This
is to enable them for rv-vrit configurations in KERNEL build.
Changes:
- arch/risc-v/Kconfig select BINFMT_ELF_EXECUTABLE for QEMU-RV
- boards/risc-v/qemu-rv/rv-virt/configs
- knsh32/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
- knsh64/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
- ksmp64/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
- knetnsh64/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
- knetnsh64_smp/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
Additions:
- boards/risc-v/qemu-rv/rv-virt/scripts/
- gnu-elf.ld apps linker script
The ARCH_TEXT_VBASE of knsh32 is set to same as that of 64bit to reuse
the apps linker script.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Previously apps in kernel build are partially linked, thus are
big and inefficient. This enables full link for kernel mode apps
to reduce size and speed up loading.
Changes:
- arch/risc-v/Kconfig select HAVE_ELF_EXECUTABLE for K230
- boards/../scripts/Make.defs adjust LDELFLAGS
- boards/../knsh/defconfig enable BINFMT_ELF_EXECUTABLE
Additions:
- boards/../scripts/gnu-elf.ld apps linker script
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
The RT-Timer thread may call the `start_rt_timer` function. This
function gets the spinlock with interrupts disabled to ensure
exclusive access. However, this was already being performed in the
RT-Timer thread, causing a deadlock.
Following up the 'Espressif HAL fullly integration for ESP32s2/s3'
changes in https://github.com/apache/nuttx/pull/11428
There are few missing interrupt type constants need update. So
update them to avoid the build error.
Usually the startup script is placed under /etc. The contents of the etc directory
are compiled and linked with Nuttx binary in the form of romfs. After startup,
it will be mounted by Nsh.
etc is generated by the different boards, that use genromfs and xxd tools to generate
and compile it into the Nuttx, for example: boards/arm/at32/at32f437-mini/tool/mkromfs.sh
The more common method is etc image generated from the content in the corresponding
board/arch/board/board/src/etc directory, and added by Makefile for example:
boards/sim/sim/sim/src/etc.
But in kernel/protected mode, Nuttx kernel and apps are run in different privileged/
non-privileged mode or the isolated binarys, so as that nsh should use syscall to
access Nuttx kernel by exported API. In this scenario, nsh can not mount the etc image
content, because that is generated in board and as a part of Nuttx kernel.
changes:
- move etc romfs mount from nsh to Nuttx, but keep the script to parse and execute.
- move and rename the related CONFIG, move customized nsh_romfsimg.h to etc_romfs.c
in boards, and no need declaration for romfs_img/romfs_img_len.
This commit changes and updates all configurations in Nuttx arch/board as much as possible,
but if any missing, please refer to the following simple guide:
- rename CONFIG_NSH_ROMFSETC to CONFIG_ETC_ROMFS, and delete CONFIG_NSH_ARCHROMFS in defconfig
- rename the etc romfs mount configs, for example CONFIG_NSH_FATDEVNO to CONFIG_ETC_FATDEVNO
- move customized nsh_romfsimg.h to etc_romfs.c in board/arch/board/board/src and no need
declaration for romfs_img/romfs_img_len.
- delete default nsh_romfsimg.h, if ROMFSETC is enabled, should generate and compile etc_romfs.c
in board/arch/board/board/src.
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
Note: This implementation is a bit more relaxed than what we do for
non-cmake builds. Mainly because I'm not familiar enough with cmake
to mirror what the non-cmake version does.
Current LITEX_LAST_IRQ looks like a typo that blocks compilation of
`arty_a7/knsh` configuration.
This fixes the build but I have no such device for test.
Found it was LITEX_IRQ_LAST before commit #ee84ea3 so likely typo was
introduced by then.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Add ARCH_CHIP_QEMU_TRUSTZONE to enable/disable the TrustZone
support beacause qemu also support enable/disable Arm Security
Extensions: https://qemu-project.gitlab.io/qemu/system/arm/virt.html
when launch.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
The implementation of the RISC-V Timer for BL808 SoC is incomplete. This PR implements the BL808 RISC-V Timer by calling OpenSBI. The code is derived from NuttX for RISC-V QEMU.
The implementation of `up_timer_initialize` with OpenSBI is explained in this article: https://lupyuen.github.io/articles/nim#appendix-opensbi-timer-for-nuttx
Changes:
- Documentation/platforms/risc-v/k230 revised for both modes
- arch/risc-v/include/k230/irq.h add S-mode IRQs
- under arch/risc-v/src/k230 folder:
- Make.defs drop use of k230_exception_m.S
- hardware/k230_clint.h add S-mode defs, revised freq
- k230_head.S unified flat/kernel mode support
- k230_irq.c add S-mode support with debug dump
- k230_mm_init.c revised for K230 S-mode
- k230_start.c revised for flat/s-mode,
- arch/risc-v/src/k230/k230_timerisr.c unified flat/s-mode support.
- under boards/risc-v/k230/canmv230 folder:
- configs/nsh/defconfig fix RAM size
- include/board_memorymap.h cleanup for S-mode
- src/.gitignore ignore romfs_boot.c
- src/Makefile add romfs support
Renames:
- under boards/risc-v/k230/canmv230/src/ folder:
- canmv_init.c from k230_appinit.c making room for more k230 devices
Dropped:
- under arch/risc-v/src/k230/
- k230_exception_m.S as hybrid mode not ready yet.
New files in boards/riscv/k230/canmv230:
- configs/knsh/defconfig S-mode config
- scripts/ld-kernel.script S-mode linker script
- src/romfs.h User space ROMFS defs needed in S-mode
- src/romfs_stub.c Stub ROMFS image
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
hostfs has its copies of some of nuttx definitions with different
names to avoid conflicting with the host OS definitions.
sometimes people only modifies one of them and forgets updating
another. eg. https://github.com/apache/nuttx/pull/11445
this commit introduces some assertions to detect that kind of
mistakes.
This is to align with ARCH_KMAP_VBASE by source codes.
It also fixes fake warnings from `tools/refresh.sh`.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
By integrating the Espressif`s HAL repository into the current
ESP32-S2 implementation on NuttX, it is possible to call functions
that makes it easier to setup the registers of the ESP32-S2,
enabling the usage of common Espressif drivers.
By integrating the Espressif`s HAL repository into the current
ESP32-S3 implementation on NuttX, it is possible to call functions
that make it easier to set up the registers of the ESP32-S3 and
enables the usage of common Espressif drivers. Please note that
Espressif's HAL repository was already being used for the Wi-Fi
driver. Then, this commit includes other source files to be used
by other drivers other than Wi-Fi and reorganize the build process.
This lower-half WS2812 LED driver uses the RMT peripheral of the
Espressif's SoCs to drive the RGB addressable LEDs. Compared to
the SPI-based implementation, it is faster!
The lower-half implementation of the RMT character driver based on
Espressif HAL enables using the RMT peripheral of ESP32, ESP32-S2
and ESP32-S3 as a common xtensa-based Espressif driver.
The RMT packages on Espressif SoCs are 4-byte long and are known as
"items". Please check the Techinal Reference Manual of the chip to
obtain more details.
Summary:
- I noticed that qemu-armv8a:netnsh_smp_hv does not detect
GICv2 on Raspi4B (ubuntu 22.04 server + qemu-8.1.2)
- According to the GIC-400 TRM, it says that the architecture
version can be obtained from GICC_IIDR (See Table 3-7)
- This commit fixes this issue.
Impact:
- Should be none
Testing:
- Tested with qemu-armv8a:netnsh_smp_hv on
- Raspi3B+ (ubuntu 22.04 server + qemu-8.1.2)
- Raspi4B (ubuntu 22.04 server + qemu-8.1.2)
- M1/MacBook Pro 2021 (macOS 13.6 + qemu-8.1.2)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
1. Solve wifi may not work bug for bbpll not lock or not stable when enable RF.
2. Improved timing tuning stability on ESP32-S3.
The root cause of the issue:
The application won't re-calibrate the BBPLL clock if it's already enabled.
We add a force-recalib function in the app startup code to make sure even if
the patch is applied by OTA, the clock is still re-calibrated.
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
since gcc report the false alarm if the pointer offset from zero address:
inlined from 'up_vectormapping' at chip/dm320_boot.c:162:7,
inlined from 'arm_boot' at chip/dm320_boot.c:211:3:
Error: chip/dm320_boot.c:117:17: error: array subscript 0 is outside array bounds of 'uint32_t[0]' {aka 'long unsigned int[]'} [-Werror=array-bounds=]
117 | ctable[index] = (paddr | mmuflags);
| ~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
The opening and closing of the window has been associated with the opening and closing of fb, but the LCD has not yet been optimized. The window will only open when sim_x11openwindow is called, and similarly, the window will only close when sim_x11closewindow is called.
Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
The code is mainly derived from the NuttX qemu-rv/rv-virt codebase.
Major changes:
- boards/Kconfig: add new BOARD_K230_CANMV
- arch/risc-v/Kconfig: add new CHIP_K230 chip and ARCH_RV_MMIO_BITS
- arch/risc-v/src/common/riscv_mtimer.c: use ARCH_RV_MMIO_BITS to
select MMIO access width
New additions:
- arch/risc-v/include/k230/: k230 SoC definitions
- arch/risc-v/src/k230/: k230 SoC sources
- boards/risc-v/k230/canmv230/: CanMV-K230 board sources and configs
- Documentation/platforms/risc-v/k230/: simple doc
Note that only FLAT build works for canmv230 now.
This PR has changes in RiscV common layer thus may affect other RiscV ports
It changes the mtime/mtimecmp access control from using config ARCH_RV64 to
newly intorduced config ARCH_RV_MMIO_BITS.
Original design uses ARCH_RV64 to select 64bit MMIO in riscv_mtimer.c, this
can't cope with the situation with K230 --- it has ARCH_RV64 but only can do
32bit MMIO. So a new ARCH_RV_MMIO_BITS config has been introduced. Its value
depicts the MMIO width in bits. The MMIO_BITS defaults to 32/64 for RV32/
RV64 respectively. This allows the macro to replace current use of ARCH_RV64
in riscv_mtimer.c.
The new MMIO_BITS config is a derived one, and for RiscV chips with
equal CPU and MMIO widths there is no need to explicitly set it as the
default rule will do that. Only chips with different CPU and MMIO widths
need set it in Kconfig.
So by design this change should be safe but RiscV ports should be checked.
"ostest" verification has been done for:
- canmv230/nsh
- rv-vivt/nsh
- rv-virt/nsh64
configuration generation and manual check of derived RV_MMIO_BITS has been
done for:
- star64/nsh
- arty_a7/nsh
- bl602evb/nsh
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
The `xxx_ipv6multicast` function in each driver is not adapted to
multiple IPv6 addresses yet, and they're redundant, so try to take them
into common code.
Change:
1. Add MAC `g_ipv6_ethallnodes` and `g_ipv6_ethallrouters` in
`icmpv6_devinit` and call them in `netdev_register`
2. Add multicast MAC for Neighbor Solicitation when adding any IPv6
address, and remove them when IPv6 address is removed
3. Select `NET_MCASTGROUP` when `NET_ICMPv6` because now we need
`d_addmac` when we have ICMPv6
Note:
We want modules outside net stack to call functions like
`netdev_ipv6_add` and never touch the related MAC address, so these MAC
functions are added as internal functions to `net/netdev/netdev.h`
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
DMA directly to user (virtual) memory won't work, as the DMA engine(s)
don't do address translations, i.e. they require a physical address.
Using kernel heap is fine as it is mapped vaddr=paddr. Also, the USB DMA
engine does not have any alignment requirements.
The hack just opens the entire SoC memory unconditionally, which is not
a good idea.
Test features can be used ad-hoc, they don't need to be supported by the
build.
There is a problem with the current elf loader for risc-v: when a pair of
PCREL_HI20 / LO12 relocations are encountered, it is assumed that these
will follow each other immediately, as follows:
label:
auipc a0, %pcrel_hi(symbol) // R_RISCV_PCREL_HI20
load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S
With this assumption, the hi/lo relocations are both done when a hi20
relocation entry is encountered, first to the current instruction (addr)
and to the next instruction (addr + 4).
However, this assumption is wrong. There is nothing in the elf relocation
specification[1] that mandates this. Thus, the hi/lo relocation always
needs to first fixup the hi-part, and when the lo-part is encountered, it
needs to find the corresponding hi relocation entry, via the given "label".
This necessitates (re-)visiting the relocation entries for the current
section as well as looking for "label" in the symbol table.
The NuttX elf loader does not allow such operations to be done in the
machine specific part, so this patch fixes the relocation issue by
introducing an architecture specific cache for the hi20 relocation and
symbol table entries. When a lo12 relocation is encountered, the cache
can be consulted to find the hi20 part.
[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
The macro LOG2_CEIL is intended to be used in the pre-processor phase. If
used run-time it will generate a massive amount of extra code (~3.5K) which
is a problem, as the PMP configuration is quite often executed from a first
stage bootloader with a limited amount of code memory.
Code size differences pre- and post:
Memory region Used Size Region Size %age Used
envm: 112064 B 112384 B 99.72%
Memory region Used Size Region Size %age Used
envm: 108952 B 112384 B 96.95%
This PR adds support for the Bouffalo Lab BL808 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for PINE64 Ox64 SBC.
Most of the code was derived from NuttX for Star64 JH7110. The UART Driver was derived from BL602 NuttX. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64
`Kconfig`: Added ARCH_CHIP_BL808 for BL808 SoC
`include/bl808/chip.h`: BL808 Definitions
`include/bl808/irq.h`: External Interrupts
`src/bl808/chip.h`: Interrupt Stack Macro
`src/bl808/bl808_allocateheap.c`: Kernel Heap
`src/bl808/bl808_head.S`: Linux Header and Boot Code
`src/bl808/bl808_irq.c`: Configure Interrupts
`src/bl808/bl808_irq_dispatch.c`: Dispatch Interrupts
`src/bl808/bl808_memorymap.h`: Memory Map
`src/bl808/bl808_mm_init.c`, `bl808_mm_init.h`: Memory Mgmt
`src/bl808/bl808_pgalloc.c`: Page Allocator
`src/bl808/bl808_serial.c`, `bl808_serial.h`: UART Driver
`src/bl808/bl808_start.c`: Startup Code
`src/bl808/bl808_timerisr.c`: Timer Interrupt
`src/bl808/hardware/bl808_memorymap.h`: PLIC and UART Base Address
`src/bl808/hardware/bl808_plic.h`: PLIC Register Addresses
`src/bl808/hardware/bl808_uart.h`: UART Register Addresses
`src/bl808/Kconfig`: BL808 Config
`src/bl808/Make.defs`: Makefile
Currently RISC-V NuttX supports 32-bit MMU Flags inside a Page Table Entry. This PR extends the MMU Flags to 64-bit, to support T-Head C906 Core and the new RISC-V Svpbmt Extension.
T-Head C906 uses Bits 59 to 63 in a Leaf Page Table Entry to configure the Memory Type: Cacheable / Bufferable / Strongly-Ordered. For the upcoming port of NuttX to PINE64 Ox64 BL808 SBC, we need to set the Memory Type to Strongly-Ordered for I/O Memory, which requires 64-bit MMU Flags.
Details of C906 MMU: https://lupyuen.github.io/articles/plic3#t-head-errata
Newer RISC-V Cores will use the Svpbmt Extension to configure the Memory Type (Cacheable / Strongly-Ordered). Svpbmt uses Bits 61 to 62 in a Leaf Page Table Entry to define the Memory Type. This also requires 64-bit MMU Flags.
Details of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/main/src/supervisor.adoc#svpbmt
Usage:
1. CONFIG_FS_PROCFS_MAX_STACK_RECORD > 0, such as 32,
2. add '-finstrument-functions' to CFLAGS for What you want to check
stack.
3. mount porcfs
4. cat /proc/<pid>/stack will print backtace & size
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.
We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.
Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.
use instrument_register to register entry function and exit function.
They will be called by the instrumented function
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
The ADC peripheral can only support up to
50MHz on rev V silicon and 36MHz on Y silicon.
The existing driver always used no prescaler
and kept boost setting at 0.
