Current `CONFIG_PAGING` refers to an experimental implementation
to enable embedded MCUs with some limited RAM space to execute
large programs from some non-random access media.
On-demand paging should be implemented for the kernel mode with
address environment implementation enabled.
cpu0 thread0: cpu1:
sched_yield()
nxsched_set_priority()
nxsched_running_setpriority()
nxsched_reprioritize_rtr()
nxsched_add_readytorun()
up_cpu_pause()
IRQ enter
arm64_pause_handler()
enter_critical_section() begin
up_cpu_paused() pick thread0
arm64_restorestate() set thread0 tcb->xcp.regs to CURRENT_REGS
up_switch_context()
thread0 -> thread1
arm64_syscall()
case SYS_switch_context
change thread0 tcb->xcp.regs
restore_critical_section()
enter_critical_section() done
leave_critical_section()
IRQ leave with restore CURRENT_REGS
ERROR !!!
Reason:
As descript above, cpu0 swith task: thread0 -> thread1, and the
syscall() execute slowly, this time cpu1 pick thread0 to run at
up_cpu_paused(). Then cpu0 syscall execute, cpu1 IRQ leave error.
Resolve:
Move arm64_restorestate() after enter_critical_section() done
This is a continued fix with:
https://github.com/apache/nuttx/pull/6833
Signed-off-by: ligd <liguiding1@xiaomi.com>
Use private naming to avoid conflicts with user applications
In file included from libuv/src/unix/internal.h:25,
from libuv/src/unix/udp.c:23:
libuv/src/uv-common.h:57: warning: "container_of" redefined
57 | #define container_of(ptr, type, member) \
|
In file included from nuttx/include/nuttx/list.h:47,
from nuttx/include/nuttx/tls.h:40,
from nuttx/include/nuttx/sched.h:48,
from nuttx/include/nuttx/arch.h:87,
from nuttx/include/nuttx/userspace.h:35,
from nuttx/include/nuttx/mm/mm.h:30,
from nuttx/include/nuttx/kmalloc.h:34,
from nuttx/include/nuttx/lib/lib.h:31,
from nuttx/include/stdio.h:35,
from apps/system/libuv/libuv/include/uv.h:59,
from libuv/src/unix/udp.c:22:
nuttx/include/nuttx/nuttx.h:48: note: this is the location of the previous definition
48 | #define container_of(ptr, type, member) \
|
Signed-off-by: chao an <anchao@lixiang.com>
During removal of F1 related stuff, code that configures FLASH
latency was removed, which rendered some of the F3 line unbootable.
It was done by mistake, since previous removed block was
'#ifdef VALUE_LINE', and block with FLASH code was '#ifndef VALUE_LINE'
and so it should not have been removed.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
-- Detecting CXX compile features
-- Detecting CXX compile features - done
arm-none-eabi-gcc: error: -Wstrict-prototypes: No such file or directory
arm-none-eabi-gcc: error: -Wstrict-prototypes: No such file or directory
-- Configuring done
-- Generating done
Signed-off-by: chao an <anchao@lixiang.com>
- remove read-write logic - this should be handled by radio protocol implementation
- remove EVENTS and TASKS bit definitions - we can just use a signle definition
- add more radio ops
- fix frequency configuration
- fix printf warnings
- fix radio reset
I noticed when executing pwm STOP command in
multichannel mode, the channel still outputting.
This commit fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
I noticed when executing pwm STOP command in
multichannel mode, the channel still outputting.
This commit fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
I noticed when executing pwm STOP command in
multichannel mode, the channel still outputting.
This commit fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
SAMv7 reset controller stores the cause of last reset (SW reset, power up,
pin reset etc.) in status register. This commit adds function that allows
the board to retrieve this information. This function should be called
from board support layer either during initialization or based on
incoming ioctl call.
Adding the sam_get_reset_cause() to sam_systemreset.c also resulted in
always compiling this file by default and only putting up_systemreset()
under CONFIG_SAMV7_SYSTEMRESET option.
Also header file sam_systemreset.h was created as it defines reset types
in comfortable manner for future processing in board layer. This is done
to avoid passing boardctl dependent structure to architecture layer.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
As long as the GNSS feature is not used, GNSS RAM can be used as general memory.
This memory is 640KByte total, which is lower performance than the application RAM.
It is possible to locate text, data and bss into GNSS RAM and to use as heap area.
SAMA5D2 has UART (TX/RX only) and FLEXCOM USART (with control pins).
UART has only TX/RX, so if I try to use flow control with FLEXCOM USART,
there is no register definition on the UART side and get a compilation error.
Signed-off-by: Takeyoshi Kikuchi <kikuchi@centurysys.co.jp>
Commit 03e5c02 introduced option to have both standard SPI and QSPI
in SPI mode on one system. However this change broke the appearance of
QSPI driver configuration menu entry in menuconfig as it was dependent
on !SAMV7_QSPI_IS_SPI (which is now true for all MCUs having standard
SPI ability in QSPI driver).
This change makes sure the menu is correctly shown when QSPI driver
used.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit refactors DAC driver. The functionality remains the same
but driver start up is now done in dac_setup (after application called
open function) instead of sam_dac_initialize (called from BSP). This
ensures that driver does not take resources (timer, interrupt) until
opened. Implementation of dac_shutdown is also provided, therefore
the driver frees resources once closed.
This change is consistent with other drivers implementation.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
USART peripheral can work in SPI mode as well. This commit adds support
for such functionality. Only 1 slave device is supported by the
peripheral therefore board level does not have to ensure correct CS
setup.
The usage of the peripheral is the same as with other SPI drivers.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
If a TX DMA completion interrups a forground write.
The TX DMA completion can start a dma_send and it will
then followed by the forground write's dma_send
stoping the,then in progress DMA.
By atomicaly marking the tx dma busy, the forground
write will not perform the dma_send, and will only
enqueue the data. At the next TX dma completion any
data pending in the tx queue will be sent
The logic of the conditional expression that determines whether
the QH is a target QH or not is reversed in the process of canceling
a transfer in INPROGRESS state.
Therefore, the QH in INPROGRESS state is not released and subsequent
communication is not successful.
Checked with CDC-ACM driver and cu command.
Signed-off-by: Takeyoshi Kikuchi <kikuchi@centurysys.co.jp>
