Commit Graph

19236 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
aefe78a884 xtensa: Add missing input operand on sys_call6 inline ASM
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-18 15:46:57 +02:00
Xiang Xiao
b30e0a26ef Move "-nostartfiles -nodefaultlibs" from Make.defs to Toolchian.defs
and replace "-nostartfiles -nodefaultlibs" with "-nostdlib"

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-18 08:26:02 -04:00
Ville Juven
d7f7867f76 risc-v/opensbi: Generalize the SBI variable handling in makefile
- Remove most of the ifeq-conditions and replace them with variables.
- Move the -I flag for 3rd party headers to opensbi/Make.defs

This clean-up / generalization makes it much simpler to add a new SBI
implementation, without the need to add a bunch of ifeq / elif conditions
to the makefile.
2022-05-18 08:35:04 -03:00
Gustavo Henrique Nihei
4f31c89963 esp32c3-devkit: Rename linker script to indicate use for Flat mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-18 11:43:52 +08:00
Gustavo Henrique Nihei
c778f35f08 risc-v/esp32c3: Add support for Protected Mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-18 11:43:52 +08:00
Eero Nurkkala
817919ebb6 risc-v/mpfs: IHC: allow hart configuration
Let the user pick what runs on the harts. For example, the
default configuration now supports NuttX on hart2 and Linux
kernel on harts 3 and 4. Also fix a few issues in the code.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-18 01:34:33 +08:00
Abdelatif Guettouche
06f2c67fc2 xtensa.h: Remove old prototype.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-05-16 23:38:09 +08:00
zhuyanlin
883337c3a0 xtensa:fpu: add up_fpucmp and enable CONFIG_ARCH_FPU macro
For arch with CP_NUM > 0, enable ARCH_FPU

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-05-16 12:30:39 +03:00
Xiang Xiao
5958d3ac62 risc-v: Move "LDFLAGS += -melf32lriscv" from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-16 11:17:08 +03:00
Xiang Xiao
d3524d4f8b arch/i2c: Change xxx_i2c_tousecs to xxx_i2c_toticks
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 23:22:01 +03:00
Xiang Xiao
f311228f80 arm/efm32: Fix typo error: CONFIG_EFM32_I2C_DYNTIMEOUT to CONFIG_EFM32_I2C_DYNTIMEO
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 19:18:09 +03:00
Xiang Xiao
1f920e55d3 Move warning option from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 15:40:35 +03:00
Xiang Xiao
8b7c5b039d arch: Move -fsanitize=kernel-address to ARCHOPTIMIZATION
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 15:40:35 +03:00
Xiang Xiao
4f090eb7fd arch/sparc: Move toolchain macro from board's Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 15:40:35 +03:00
Xiang Xiao
51cf7ba05a Remove FAR from arm/risc-v/xtensa/sim/x86
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 13:55:58 +03:00
Xiang Xiao
2976accd9f arch: Remove the extra space before the function prototype
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 13:55:58 +03:00
Xiang Xiao
1fb8c13e5e Replace nxsem_timedwait_uninterruptible with nxsem_tickwait_uninterruptible
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 13:55:58 +03:00
Xiang Xiao
816ce73ab4 Replace nxsem_timedwait with nxsem_tickwait
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 13:55:58 +03:00
Petro Karashchenko
0fee5a2b84 nuttx: fix typos in comments
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-05-14 23:45:52 +08:00
Gustavo Henrique Nihei
be9fc59b07 xtensa: Implement syscalls required for Protected Mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-14 21:38:12 +08:00
Eero Nurkkala
0178792a01 risc-v/mpfs: IHC: clarify semaphore usage
g_mpfs_ack_sig and g_mpfs_rx_sig are better used with
SEM_INITIALIZER(0) (signalling) rather than with
SEM_INITIALIZER(1) (mutual exclusion).

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-13 19:07:40 +03:00
Michal Lenc
6f6338cea0 imxrt/flexpwm: set number of modules based on configuration options
Number of channels are now set based on enabled modules (channels) in
configuration instead of the usage of static 4.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2022-05-13 12:55:45 -03:00
Michal Lenc
bdcf8b2b66 samv7/pwm: set number of channels based on configuration options
Number of channels are now set based on enabled channels in configuration
instead of the usage of static 4.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2022-05-13 12:55:45 -03:00
chao.an
701e56d4ae arm/cortex-[a|r]: add performance counter implement
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-05-13 12:55:31 -03:00
chao.an
4da48c84ff arm/cortex-[a|r]: add more functions of Performance Monitors Unit
Reference:
https://developer.arm.com/documentation/ddi0433/a/performance-monitoring-unit/performance-monitoring-register-descriptions

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-05-13 12:55:31 -03:00
chao.an
920e826a80 arm/cortex-r: rename PCMR_* to PMCR_*
It should be PMCR (Performance Monitors Control Register)

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-05-13 12:55:31 -03:00
chao.an
34b124bc14 arm/cortex-r: add _pmu_* perfix for performance monitor functions
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-05-13 12:55:31 -03:00
Petro Karashchenko
f095bf8f39 arch/arm/samv7/sam_afec: fix ADC pin for channel 9
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-05-13 11:17:37 -03:00
zhuyanlin
ad57791fe0 arch:xtensa: remove struct xtensa_cpstate_s as no need used
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-05-13 15:28:45 +02:00
zhuyanlin
f423f94d08 arch:xtensa: modify xtensa_context_save/restore function
with FPU registers in xcp context, use pointer instead of double
pointer

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-05-13 15:28:45 +02:00
zhuyanlin
1dc39689ff xtensa: move fpu register to XCPTCONTEXT_REGS
1 move fpu register to XCP_REGS
2 move save & restore fpu register to context_save/restore

Consistency with other archs.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-05-13 15:28:45 +02:00
wangbowen6
f23ba7e761 arm/tlsr82: add hardware aes encrypt and decrypt support.
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-05-13 20:24:46 +08:00
Eero Nurkkala
0a75a9556d risc-v/mpfs: apply IHC review fixes
PR#6249 was already merged without the review fixes. Provide the
fixes here on a separate patch.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-13 10:38:51 +03:00
Gustavo Henrique Nihei
ba2829adb2 xtensa: Fix argument passing for sys_call5 and sys_call6 functions
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-13 10:43:00 +09:00
Xiang Xiao
1ba316b5c7 arch: Remove board/libboard$(LIBEXT) from the rerequest of export_startup
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-12 23:34:31 +03:00
Xiang Xiao
23200471df arch/riscv: Remove & ~1 before assign signal_handler to REG_EPC
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-12 23:31:50 +03:00
Masayuki Ishikawa
3193aa3c97 arch: risc-v: Add MMU support for qemu-rv
Summary:
- This commit adds MMU support for qemu-rv
- Please note that mtimer is disabled for S-mode because
  the mtimer needs to be accessed in M-mode

Impact:
- qemu-rv only

Testing:
- Tested with rv-virt:knsh64 (will be pushed later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-13 04:14:01 +08:00
Eero Nurkkala
77e36d1acc risc-v/mpfs: introduce IHC driver
This provides an example of Asymmetric Multiprocessing (AMP). The
master from Linux sends pings that this NuttX echoes back. The system
uses RPMsg from OpenAMP.

The Inter-Hart Communication module is present in the vendor's software
stack with the tag "2021.11". The software is present on github at the
polarfire-soc project. The following conditions must be met:

 1. FPGA programmed with 2021.11 software
 2. HSS (Vendor bootloader) with 2021.11 software
 3. U-boot and Linux kernel from 2011.11 software

Currently the IHC works as a slave only on the hart number 4.

On the NuttX side, this patch uses rptun that incorporates rpmsg and
virtio. If it used only rpmsg and virtio, the future maintenance would
likely be much heavier. Using rptun also simplifies many things.

Upon success, the master side from Linux may issue an example test:

root@icicle-kit-es-amp:/opt/microchip/amp/rpmsg-pingpong# ./rpmsg-pingpong

However, the rpmsg-pingpong.c (compiled on target with gcc), may need to
be modified as seen below to match the device id:
 - char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.0";
 + char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.1024";

This work uses a separate linker script. Due to a bug yet unknown to date,
a small NuttX, when loaded by the vendor HSS bootloader, will cause the
Linux kernel to hang at boot. Thus, the binary size is increased with
a section 'filler_area' whose only purpose is to increase the image size
so that the Linux kernel will boot up.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-12 22:56:12 +08:00
wangbowen6
bc61e71b94 crypto: change type uint32_t to size_t in aes_cypher() arguments.
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-05-12 22:28:54 +08:00
Ville Juven
47e85b68fe arch/addrenv: Change text write enable/disable to generic mprot
Implement a generic access rights modification procedure instead
of the procedures that only do one thing (enable/disable write)
to one section (text).
2022-05-12 22:28:31 +08:00
Matthew Trescott
f6f826c09a Fix broken tiva_gpioirqclear 2022-05-12 14:49:35 +08:00
chao.an
04f7beea83 arm/tlsr82: fix kconfig warning
arch/arm/src/tlsr82/Kconfig:272:warning: leading whitespace ignored

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-05-12 14:58:47 +09:00
wangbowen6
c39d3fa9e4 tlsr82/tc32: optimize the irq process
1. using armv6-m arm_irq();
2. simplify the interrupt number get process;
3. To improve the performance, move common exception code to ram_code.

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-05-12 02:07:52 +08:00
wangbowen6
6caa8f1075 arm_createstack: fix warning for tc32 compiler.
fix warning:
common/arm_createstack.c: In function 'up_create_stack':
common/arm_createstack.c:154:11: warning: format '%d' expects type 'int', but argument 3 has type 'size_t'

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-05-11 20:14:30 +03:00
Masayuki Ishikawa
45beda286b arch: risc-v: Enable FPU for qemu-rv only if EXPERIMENTAL=y
Summary:
- Because a context switch issue still exists with FPU,
  it should be enabled only if EXPERIMENTAL=y

Impact:
- None

Testing:
- Tested with ostest

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-11 21:57:16 +08:00
wangbowen6
db1e6656dd arm/tc32/Make.defs: filter-out arm_udelay.c
tc32 architecture implement up_udelay by itself, so filter
out arm_udelay.c.

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-05-11 21:57:01 +08:00
wangbowen6
28684f24b7 arm/tlsr82: pwm driver optimize and add pulse count support.
1. add pulse count support for pwm0;
2. add more detailed config for pwm;
3. pwm configuration and start process optimize;
4. tlsr82/Kconfig format;

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-05-11 13:15:44 +03:00
zhuyanlin
b99ba04a8c arch:xtensa: Add SYS_flush_context syscall
This syscall do nothing as flush context was done in interrupt handler.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-05-11 10:48:53 +02:00
Xiang Xiao
6e93b440fe arch/sim: Fix warning: overriding recipe for target 'config.h'
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-11 17:39:33 +09:00
Xiang Xiao
0cf2330e41 arch/arm: Fix target 'arm_vectortab.o' given more than once in the same rule 2022-05-11 17:39:33 +09:00