Summary:
Adding virtual evaluate platform FVP. This FVP board configuration
will be used to emulate generic ARM64v8-R (Cotex-R82)series hardware
platform and provide support for these devices:
- GICv3 interrupt controllers for ARMv8-r
- PL011 UART controller(FVP)
Note:
1. ostest is PASSED at fvp ( single core and SMP)
2. the FVP tools can be download from ARM site, please check FVP
board readme.txt
TODO: merge PL011 UART driver to common place
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
This commit adds configurable fault protection to SAMv7 PWM driver.
The fault input can be used from peripherals as ADC or GPIO inputs.
Inputs from GPIO have configurable polarity (high or low). The PWM output
is automatically set to zero if fault input is active and restored
if fault input is not actived.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Summary
Different ARM64 Core will use different Affn define, the mpidr_el1
value is not CPU number, So we need to change CPU number to mpid
and vice versa, the patch change the mpid define into platform
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary
For ARM64 architecture, the arch timer is 64-bit,
the CONFIG_SYSTEM_TIME64 need to be enabled just like
x86_64 and risc-v 64
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary
VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID.
From architecture manual of AArch64, the behave is:
-reading register MPIDR_EL1 in EL2, it's return real MPIDR_EL1
-reading register MPIDR_EL1 in EL1, it's return VMPIDR_EL2
So since NuttX for SMP is running at EL1 to read MPIDR_EL1 for
identify CPU id, it's need to set VMPIDR_EL2 to MPIDR_EL1 for
every CPU at boot EL2 stage.
For some platform, the bootloader or hypervisor will do that at
the EL2 stage, but not all.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
Adding armv8-r(Cortex-R82) support and modify some common code to
fit the change, the change including:
1. ARM Single Security State Support, ARMv8-R support only single
security state, and some GIC configure need to change and fit
2. For ARMv8-R, only have EL0 ~ EL2, the code at EL3 is not necessary
and system register for EL3 is not accessible(gcc will failed when
access these registers)
3. add base MPU configure for the platform.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
The aarch64 have EL0~El3 execute level and NS/S (security state),
the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R)
state. but booting NuttX have different ELs and state while with
different platform, if NuttX runing at wrong ELs or state it will
be not normal anymore. So we need to print something in arm64_head.S
to debug this situation.
Enabling this option will need to implement up_earlyserialinit and
up_lowputc functions just you see in qemu, if you not sure,
keeping the option disable.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summory
This Power State Coordination Interface (PSCI) defines a standard
interface for power management. the PCSI need to implement handling
firmware at EL2 or EL3 for ARM64. the PSCI maybe not applicable
for arm core without PCSI firmware interface implement.
Add configure option for it.
Note:
1. ostest is PASSED at qemu and fvp ( single core and SMP)
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
- Add retry timeout to prevent inifinite loop
- Change the register operation of power control
- Add exclusive control by semaphore into some functions
- Add short delay until power control is reflected
* 32-bit time_t should be unsigned because otherwise it wraps too
soon. (in 2038)
* 64-bit time_t should be unsigned because it should be consistent
within NuttX.
* While signed time_t seems more popular among other OSes, the
consisitency within NuttX outweighs, IMO.
NuttX only treat \n as new line after https://github.com/apache/nuttx/pull/8628,
so need this conversion to interact with terminal emulator.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
