Commit Graph

14080 Commits

Author SHA1 Message Date
Petro Karashchenko
af614ac77d tls: restore C89 compatibility for TLS
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-13 21:14:53 -06:00
chao.an
c2fd66bfab arch/arm/risc-v/xtensa: add support of all symbols for debugging
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-13 08:31:13 -06:00
chao.an
89e2f00dad arch/assert: fix the stack dump overflow
[ EMERG] kasan_report: kasan detected a read access error, address at 0x3c24fca8, size is 4
[ EMERG] up_assert: Assertion failed at file:kasan/kasan.c line: 104 task: init
[ EMERG] backtrace|10:  0x2c334666 0x2c35f0d6 0x2c359ef6 0x2c35f830 0x2c360ed4 0x2c3615c0 0x2c324e0c 0x2c30a168
[ EMERG] up_registerdump: R0: ffffffff R1: 00000004 R2: ffffffff R3: ffffffff
[ EMERG] up_registerdump: R4: 3c20d4f0 R5: 2c35acd5 R6: 00000000 FP: 3c24fae8
[ EMERG] up_registerdump: R8: 3c20d504 SB: ffffffff SL: 2c413e7c R11: 2c411eb8
[ EMERG] up_registerdump: IP: 00000002 SP: 3c24fae8 LR: 00000003 PC: 2c35f0d6
[ EMERG] up_registerdump: xPSR: 61010000 BASEPRI: 000000e0 CONTROL: 00000004

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-13 01:43:18 -06:00
chao.an
0b7b8d274f arm/cortex-m: enhance the crash dump
1. add irq stack information to list
2. add cpu loading into list

before:

Idle Task: PID=0 PRI=0 Stack Used=512 of 3048
hpwork: PID=1 PRI=224 Stack Used=304 of 2016
lpwork: PID=2 PRI=100 Stack Used=304 of 2016
rptun: PID=4 PRI=224 Stack Used=856 of 2008

after:

[ EMERG] [ap] up_showtasks:    PID    PRI      USED     STACK   FILLED       CPU   COMMAND
[ EMERG] [ap] up_showtasks:   ----   ----       928      2048    45.3%      ----   irq
[ EMERG] [ap] up_dump_task:      0      0       512      3048    16.7%     99.4%   Idle Task
[ EMERG] [ap] up_dump_task:      1    224       304      2016    15.0%      0.0%   hpwork
[ EMERG] [ap] up_dump_task:      2    100       304      2016    15.0%      0.0%   lpwork
[ EMERG] [ap] up_dump_task:      4    224       856      2008    42.6%      0.0%   rptun

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-12 21:40:29 -06:00
Matheus Castello
294694bb2f arch: arm: select LIBC_ARCH_ATOMIC when config ARCH_CHIP_RP2040
Use the common atomic operations when needed.

Signed-off-by: Matheus Castello <matheus@castello.eng.br>
2021-12-11 11:32:17 -06:00
Juha Niskanen
a35d205f3b arch/arm/src/stm32l4/stm32l4_pwm.c: fix printf format
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2021-12-10 12:30:26 -06:00
Daniel Agar
efc949bceb arch/arm/src/stm32/Kconfig STM32_STM32F412 add SPI2 & SPI3 2021-12-09 21:30:41 -06:00
chao.an
3d75c25737 cortex-m/hardfault: enhance the dump information of mem/hard-fault
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
66e604b40e cortex-m/hardfault: add usage-fault handler
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
2f449245cc cortex-m/hardfault: add bus-fault handler
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
99fa58c871 arm/cortex-m23: armv8-m baseline do not support mem-fault
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 05:36:00 -06:00
chao.an
3e812dd88c cortex-m/fault: add CFSR(Configurable Fault Status Register) Definitions
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 04:30:06 -06:00
Xiang Xiao
6357523892 arch: Add _wchar_t typedef like other basic types
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-09 16:57:23 +09:00
chao.an
9b502dca05 arm/backtrace: disable the sanitize address check
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 01:05:46 -06:00
chao.an
7a61588b00 cortex-m/backtrace: remove the push process to simplify backtrace
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 01:05:46 -06:00
chao.an
437c81f8d0 cortex-m/assert: dump all registers with alias
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 00:16:04 -06:00
Michal Lenc
ae57492189 samv7: enable MCAN driver support for both rev A and rev B
This commit enables the MCAN driver to function with both rev A and rev B
version of the chip. The version of the chip is selected automtically from
SAM_CHIPID_CIDR register so there is no need to predefined it in the
configuration.

The functonality was tested on rev B version of the chip. The rev A was
not tested since I do not have the functional board but the code remains
the same as in the previous NuttX version so it should not cause any
additional troubles.

The code is co-authored by Miloš Pokorný who wrote the initial transition
to rev B of the chip.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Co-authored-by: Miloš Pokorný <milos.pokorny@seznam.cz>
2021-12-07 23:36:11 -06:00
Huang Qi
58e0781e2e arch/arm: Implement TLS support
Signed-off-by: Huang Qi <no1wudi@qq.com>
2021-12-07 23:31:41 -06:00
Masayuki Ishikawa
bec9058b4c arch: lc823450: Replace the critical section with spinlock in lc823450_serial.c
Summary:
- This commit replaces the critical section with spinlock
- The logic is the same as cxd56_serial.c

Impact:
- None

Testing:
- Tested with lc823450-xgevk:bt

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-12-07 23:28:54 -06:00
fenghang
c39ef4420e 1.phyplus update files to accord with the requirement of chcekpatch.sh
2.fix some files to fix compile warning

3.remove blueteeth header files, which are not used in nuttx core.

4.fix configs and add lost files

5.update defconfig, remove useless items

6.fix compile warning for nuttx phyplus

7.delete useless: ble, h4, zblue defconfig files form phyplus configure folder

8.fix file format check error on phyplus source code

9.fix phyplus kconfig param error

10.update configure file for nuttx
2021-12-07 01:37:29 -06:00
fenghang
073c9880a3 phyplus first submit 2021-12-07 01:37:29 -06:00
chao.an
437a30d117 arch/tcbinfo: fix build break if task name disabled
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-06 00:47:58 -06:00
Xiang Xiao
a0990ee416 arch: Remove the duplicated up_tls_info implementation
Define up_tls_info in arch/arch.h directly if the general one isn't suitable

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-05 20:59:53 -06:00
Xiang Xiao
19e5ee6ce0 arch: Remove FILE dump code from _up_dumponexit
since the kernel build can't access the userspace memory
inside other process directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-06 11:23:58 +09:00
Xiang Xiao
b65c7c26cf arch: Dump task name through tcb_s::name instead of argv[0]
since argv is defined in task_tcb_s not tcb_s

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-01 16:04:15 +01:00
Gerson Fernando Budke
c3307fce6b arch/arm/Kconfig: Add ARCH_HAVE_PROGMEM config
The Atmel samv7 implements progmem functionality. However, there is
missing ARCH_HAVE_PROGMEM Kconfig symbol. This add missing symbol.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2021-11-29 21:31:08 -06:00
Petro Karashchenko
31809724e1 boards/same70-xplained: disable systick before loading MCUboot application
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-28 20:33:53 -06:00
Petro Karashchenko
fae27cc945 arch/samv7: fix unaligned address write for progmem interface
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-28 11:04:28 -06:00
Michal Lenc
ce53ea5da6 arch/arm/src/samv7: add DMA and TC trigger support to AFEC driver
This commit adds DMA and TC support to SAMV7 AFEC driver. The AFEC (ADC)
can now be triggered by Timer/counter at chosen frewuency and samples can
be transfered via DMA with configurable number of samples. Timer/counter
trigger is now set as a default option with the possibility to change it
to software generated trigger.

DMA is inspired by SAMA5 driver and also uses ping pong buffers.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-11-27 06:17:45 -06:00
Michal Lenc
6f2e23ad0c arch/arm/src/samv7/sam_tc.c: fix compile warnings and errors
Just a minor change fixing some compile warnings and errros, does not have
any impact on functionality.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-11-27 06:17:45 -06:00
Petro Karashchenko
0d9425676d arch/arm/src/samv7: add flash progmem erasestate ioctl support
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-26 14:55:34 -03:00
Petro Karashchenko
134b2e6ec9 arch/arm/include/samv7: fix typo in samv7 irq header files
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-26 14:55:34 -03:00
Petro Karashchenko
dd647d200e arch/samv7/sam_progmem: fix page size flash writing
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-26 08:47:08 -06:00
zhuyanlin
1b3005accf arch:cache_invalidate: fix unalign cacheline invalidate
Only invalidate may corrupt data in unalign start and end.
Use writeback and invalidate instead.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-24 22:48:13 -06:00
zhuyanlin
4db5016d83 arch:hostfs: add cache coherence config for semihosting option
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-24 22:48:13 -06:00
David Sidrane
ad7e36d83f stm32f7:sdmmc defer invalidate until after DMA completion
The FAT was not coherent. Resulting in a write failed
   with errno:28 No space left on device.

   It is unclear how the memory is acesses prior to the DMA
   completion. But this restructuring ensures the data
   is coherent.

   This issue was not detected on the stm32h7
2021-11-24 20:38:23 -06:00
chao.an
7cbb8da692 binfmt/elf: add bare metal coredump support
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-11-23 20:48:00 -06:00
chao.an
4c76c356ef arch/arm: add more arch elf define
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-11-23 20:34:56 +09:00
Xiang Xiao
a29ee19af4 driver/motor: Remove the unnecessary critical section operation
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-11-18 19:27:07 -06:00
Xiang Xiao
a799835ec6 arch/arm: Remove EXPERIMENTAL from ARCH_TRUSTZONE_XXX
since it work on the product device

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-17 08:59:14 -03:00
Andres Sanchez
064f6c8c55 add MTDIOCTL_PROGMEM_ERASESTATE support
Signed-off-by: Andres Sanchez <tito97_sp@hotmail.com>

solve style check errors.
2021-11-16 14:45:03 -03:00
Alin Jerpelea
6deaba896d arch: Haltian Ltd: update licenses to Apache
Gregory Nutt has submitted the SGA
Haltian Ltd has submitted the SGA
Uros Platise has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-11-15 06:49:32 -06:00
Xiang Xiao
2262ddfa6d arch: Remove fflush(stdout) from driver code
it's wrong to call stdio function inside driver

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-15 00:04:12 +01:00
zhuyanlin
012bd1494c arch:debug: add struct for task aware debug.
When enable DEBUG_TCBINFO config, a global struct will
provide, then debuggers can aware nuttx task infomation.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-10 14:31:10 -03:00
Juha Niskanen
201c67acbd stm32l4 dfumode: enable for STM32L4+ chips 2021-11-10 11:18:37 -06:00
Michal Lenc
e0cef411e1 arch/arm/src/samv7: add support for AFEC (ADC) driver
This commit adds microcontroller support for Analog Front End driver to
samv7 MCUs. Only software trigger via IOCTL is currently supported,
averaging can be set by configuration option CONFIG_SAMV7_AFECn_RES.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-11-07 21:04:56 -06:00
Yuichi Nakamura
3a0cd56623 rp2040: support I2C_RESET 2021-11-07 03:43:22 -08:00
Yuichi Nakamura
c109262a7f rp2040: add rp2040_gpio_get_function_pin() 2021-11-07 03:43:22 -08:00
raiden00pl
7b595ab73a arch/arm/stm32/stm32_qencoder: add support for Qenco index pin 2021-11-07 03:52:48 -06:00
David Sidrane
4b96c28ed4 stm32h7:Support SPI SPI_DELAY_CONTROL 2021-11-06 05:14:05 -05:00