Make a separate config flag for enabling L2 cache. This is on by
default when compiling a standalone/bootloader configuration, but
can also be disabled for special cases, such as memory testing
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This change moves the static vars to the appropriate place to follow the coding standard. It also adds comments as sections and `static` where necessary.
Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
The default size in QEMU system is 128MB, and the size specified in chip.h is also 128MB. However, the region size for MMU was 512MB, so fixed it.
Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
Summary:
- This commit refactors the entry point name for BUILD_KERNEL
to avoid misunderstanding the name
Impact:
- None
Testing:
- Tested with rv-virt:ksmp64
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that the OS timer sometimes proceeds fast when
a task is scheduled to run on CPUO via IPI.
- Actually, qemu-rv implementation shares supervisor software
interrupt for both timer and IPI on CPU0.
- This commit fixes this issue.
Impact:
- qemu-rv only
Testing:
- Tested with qemu-6.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit adds SMP support for BUILD_KERNEL
Impact:
- RISC-V: BUILD_KERNEL + SMP only
Testing:
- Tested with rv-virt:ksmp64 (will be added later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Run-time check for L3 page table size, to ensure it is large enough
to map all of the kernel memory.
NOTE: The check has to be run-time, as KFLASH_SIZE/KSRAM_SIZE are really
linker relocation symbols, and thus cannot be utilized compile-time.
L3 table maps 2MB of memory, this brings an implicit requirement for
any L3 region to be aligned to 2MB. This commit adds build time sanity
checks to ensure this requirement is met.
For other SvXX architectures the boundary requirement (might be) is
different.
Summary:
- This commit introduces g_percpu_spin to avoid deadlock
in riscv_percpu.c instead of using the global spinlock.
Impact:
- None
Testing:
- Tested with rv-virt:knsh64 and rv-virt:ksmp64 (will be added later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This allows properly using 10/100Mbps also with 1G phy. Some gigabit PHYs
come out of reset with 1G advertisement enabled, causing other devices to
set up link with 1G. If, after this, the link is set to 10/100 on the mpfs,
the link won't work.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Summary:
- In RISC-V, BUILD_KERNEL uses S-mode and to use M-mode timer
we need to handle it by using OpenSBI or self-implementation.
- This commit adds M-timer self-implementation for BUILD_KERNEL.
Impact:
- qemu-rv only
Testing:
- Tested with rv-virt:knsh64 on qemu-6.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I found inappropriate SET_CSR() usage in the function.
- This PR fixes this issue.
Impact:
- None
Testing:
- tested with rv-virt:knsh64
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Add initial support for the I2S peripheral on ESP32.
Add I2S character driver and generic I2S audio driver.
Include i2schar defconfig for ESP32-DevKitC board.
In SMP mode, if all cores start at same time, all from __start(),
then only primary need do initialize, so others core should wait
primary, use 'sev' let the non-primary continue to __cpuN_start().
Signed-off-by: ligd <liguiding1@xiaomi.com>
Summary:
- I noticed that the OpenSBI library depends on the BSD license
- This commit fixes this issue
Impact:
- CONFIG_OPENSBI=y only
Testing:
- Build with icicle:opensbi (will be updated later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
NON-primary cpu will invalidate cpu0's cache L2, that will caused cpu0's data mismatch, and then system crash
Signed-off-by: ligd <liguiding1@xiaomi.com>
The IDMA needs to have 32 bit word alignment, in fact it will
AND off the lower 2 bits of the value stored in IDMABASE0R.
This bug was masked by CONFIG_ARMV7M_DCACHE causing proper word alignment
and also FAT_DMAMEMORY being aligned.
This commit extends the unaligned logic (used for dcache) to take into account
the need for a buffer copy when the buffer is ot 32 bit word.
It leverages the fact that when CONFIG_ARMV7M_DCACHE is not defined the up_xxxxx_dcache are nops.
Fix build break:
Error: L6218E: Undefined symbol _sbss (referred from arm_head.o).
Error: L6218E: Undefined symbol _ebss (referred from arm_head.o).
Error: L6218E: Undefined symbol _eronly (referred from arm_head.o).
Error: L6218E: Undefined symbol _sdata (referred from arm_head.o).
Error: L6218E: Undefined symbol _edata (referred from arm_head.o).
Signed-off-by: chao an <anchao@xiaomi.com>
Summary:
- I noticed that lc823450-xgevk does not boot due to the recent
changes on g_current_regs
- This PR fixes this issue
Impact:
- None
Testing:
- Tested with lc823450-xgevk:rndis
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
1. some arm instructions are not compatible with arch tlsr:
{standard input}: Assembler messages:
{standard input}:53: Error: bad instruction `svc #0'
2. remove unsupport compile option
cc1: error: unrecognized command line option "-mlittle-endian"
Signed-off-by: chao an <anchao@xiaomi.com>
Reference:
https://developer.arm.com/documentation/dui0474/m/image-structure-and-generation/section-placement-with-the-linker/section-placement-with-the-first-and-last-attributes
CAUTION:
FIRST and LAST must not violate the basic attribute sorting order. For example, FIRST RW is placed after any read-only code or read-only data.
arm-none-eabi-readelf -aS arm_vectors.o
1. Without const:
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 3] .vectors PROGBITS 00000000 000034 00011c 00 WA 0 0 4
2. const symbol:
[ 3] .vectors PROGBITS 00000000 000034 00011c 00 A 0 0 4
Regression by:
| commit 229b57d6cb
|
| arch/armv[6|7|8]-m: Move _vectors to arm_internal.h to avoid the duplication
|
| and change the type of _vectors from uint32_t to const void *
|
| Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: chao an <anchao@xiaomi.com>
In file included from ./armv7-r/arm_l2cc_pl310.c:41:
./armv7-r/l2cc_pl310.h:38:10: fatal error: chip/chip.h: No such file or directory
38 | #include "chip/chip.h"
| ^~~~~~~~~~~~~
Signed-off-by: chao an <anchao@xiaomi.com>
stderr is a file stream pointer not a function name. Having
it in the renaming list may introduce linking error.
Signed-off-by: gaojiawei <gaojiawei@xiaomi.com>
Config option IMXRT_ADCx_ETC can now be used to select an external HW
trigger to be used instead of continous trigger. Continous trigger is
used if IMXRT_ADCx_ETC = -1 (default option). Otherwise the source signal
is routed through XBAR and used as a trigger.
Hardware triggering is currently limited to maximum of 8 channels.
HW trigger is automatically disabled if there are more than 8 channels.
The external triggering was tested with PWM signal as a source.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
1.
make[1]: *** No rule to make target 'tms570_spi.c', needed by '.depend'. Stop.
2.
In file included from armv7-r/arm_gicv2.c:36:
armv7-r/gic.h: In function 'arm_gic_nlines':
armv7-r/mpcore.h:63:29: error: 'CHIP_MPCORE_VBASE' undeclared (first use in this function)
63 | #define MPCORE_ICD_VBASE (CHIP_MPCORE_VBASE+MPCORE_ICD_OFFSET)
| ^~~~~~~~~~~~~~~~~
Signed-off-by: chao an <anchao@xiaomi.com>
since armv7-r does not support kernel mode
./armv7-r/arm_syscall.c:36:10: fatal error: addrenv.h: No such file or directory
36 | #include "addrenv.h"
| ^~~~~~~~~~~
Signed-off-by: chao an <anchao@xiaomi.com>
Summary:
- Currently, CONFIG_ARCH_PGPOOL_MAPPING=y is necessary for
CONFIG_BUILD_KERNEL=y.
- This commit removes the code for CONFIG_ARCH_PGPOOL_MAPPING=n
Impact:
- None
Testing:
- Tested with sabre-6quad:netknsh_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This commit supplements commit 7d877fbb. External sync mode is now
disabled if XBAR connection fails and config options are used directly
in sync_src variable and passed to XBAR macro only when needed. The first
option could caused an undefined behaviour when sync_src was equal to -1
(external sync not used)
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Summary:
- Because a context switch issue still exists with FPU
the configs should be removed until it works.
Impact:
- None
Testing:
- Tested with ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Otherwise, after the rx error occur, the tx output will be
out of sequence, for example:
normal log:
[ 30.163000] 12345678abcdefgh
[ 30.666000] 12345678abcdefgh
[ 31.169000] 12345678abcdefgh
[ 31.672000] 12345678abcdefgh
[ 32.175000] 12345678abcdefgh
[ 32.678000] 12345678abcdefgh
[ 33.181000] 12345678abcdefgh
error log:
he 7 .20]0003 127456c8abgdefch
gde [6.707002] 16345b78afcde
fcde
fghe10010] 5234a678ebcd
77 713 00]41238567dabchefgd
che 7 .21]0003 127456c8abgdefch
gde [8.709002] 16345b78afcde
fcde
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Since tlsr arch support A/B bank, the hardware support
relative addr to load or store, but for flash read,
must use absolute addr. also combine with flash_<*>_method.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
Fix Compile error from Armclang compiler(AC6):
Error: L6218E: Undefined symbol arm_vectoraddrexcption (referred from arm_vectoraddrexcptn.o).
Signed-off-by: chao an <anchao@xiaomi.com>
undeclare TCGETS on esp32c3 when enable usbserial and termios
error:
chip/esp32c3_usbserial.c: In function 'esp32c3_ioctl':
chip/esp32c3_usbserial.c:411:10: error: 'TCGETS' undeclared (first use in this function)
Situation:
Assume we have 2 cpus, and busy run task0.
CPU0 CPU1
task0 -> task1 task2 -> task0
1. remove task0 form runninglist
2. take task1 as new tcb
3. add task0 to blocklist
4. clear spinlock
4.1 remove task2 form runninglist
4.2 take task0 as new tcb
4.3 add task2 to blocklist
4.4 use svc ISR swith to task0
4.5 crash
5. use svc ISR swith to task1
Fix:
Move clear spinlock to the end of svc ISR
Signed-off-by: ligd <liguiding1@xiaomi.com>
Add support for MCUBoot.
Two new configurations are added:
- mcuboot-loader: mcuboot-loader app used as a bootloader.
main_mcuboot_loader as entrypoint
- mcuboot-app: used as mcuboot agent app. Needs to be
signed manually through "imgtool sign --pad --align 4 -v 0 -s
auto -H 0x200 --pad-header -S 0xc0000 nuttx.hex nuttx_sign.bin"
Signed-off-by: Andres Sanchez <tito97_sp@hotmail.com>
This commit allows the PWM modules to be synchronized by an external
signal (other PWM module for example). The sync source can be selected
from configuration.
PWM module can also now generate a trigger when its timer reaches the duty
cycle. This trigger is used for the synchronization of other modules. It
can also be used for triggering ADC for example in the future.
Thanks to Rastislav Pavlanin and Jan Spurek from NXP support for
suggestion which helped to solve the inter-module PWM synchronization
task.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Simplify the clock mode from the board.h -files. Also make the
SD clock definable as well.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
