SAMv7 PWM driver supports complementary PWM output if both pins (H and L)
are defined and configured. This commit adds a configuration option to
configure the complementary L pin.
The pin definition has to be provided by board level support.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Summary:
- I noticed that there are two kinds of descriptors for imxrt_enet.c
- The first one is the legacy descriptor and its size is 8bytes.
- The second one is the enhanced descriptor and its size is 32bytes.
- In both cases, we can not use a descriptor chain like stm32.
- Considering cache line alignment, the second one is perfect because
one descriptor fits the Cortex-M7 cache line which would fix networking
stability issues in d-cache write-back mode.
Impact:
- imxrt ethernet in d-cache write-back mode
Testing:
- Tested with ixmrt1060-evk:netnsh_dcache_wb (will be added later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that CONFIG_IMXRT_ENET_ENHANCEDBD is not correctly
used though it is defined in Kconfig.
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with imxrt1060-evk:netnsh_dcache_wb (will be added later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This reverts commit 62c15c03d3.
Fix warning: the choice symbol STM32_FLASH_CONFIG_G (defined at arch/arm/src/stm32/Kconfig:1275) is selected by the following symbols, but select/imply has no effect on choice symbols
- ARCH_CHIP_STM32F412ZG (defined at arch/arm/src/stm32/Kconfig:1014)
Generic drivers shoud not use architecture related config options like
CONFIG_SAMV7_PWM. This commit adds PWM pin overwrite under generic
configuration option CONFIG_PWM_OVERWRITE.
Now the overwrite can be used on other architectures as well or can be
completely disabled for SAMv7.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Commit d07792a caused a build error in sam_mcan.c file. This commit fixes
the build. The file now succesfully compiles and CAN works.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
In the lower half UART driver for PIC32MZ architecture, adding the
TIOCxBRK ioctl calls, which allow an application to transmit a UART
line BREAK signal.
This architecture does not support BSD-style BREAK in hardware so our
implementation follows the precedent set in STM32, GD32, and Kinetis
architectures: By default, if only PIC32MZ_UART_BREAKS is configured,
we produce the hardware-native BREAK, which lasts for 12 bit lengths;
if, in addition, PIC32MZ_SERIALBRK_BSDCOMPAT is configured, we
generate a BSD-style BREAK by putting the TX pin in GPIO mode and
driving it low "manually" until told to stop.
* arch/mips/src/pic32mz/Kconfig
(config PIC32MZ_UART_BREAKS): New. Appears as
CONFIG_PIC32MZ_UART_BREAKS in code.
(config PIC32MZ_SERIALBRK_BSDCOMPAT): New. Appears as
CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT in code.
* arch/mips/src/pic32mz/hardware/pic32mz_pps.h
(__PPS_OUTPUT_REGADDR_TO_GPIO, PPS_OUTPUT_REGADDR_TO_GPIO): New
macros to automatically determine the GPIO port and pin from the
corresponding PPS (Peripheral Pin Select) define. Since there is a
one-to-one correspondence between PPS output mappings and a single
port and pin, these macros avoid writing redundant pin mappings. We
use this when switching the TX pin from UART to GPIO to generate
the BREAK and we could use it in other peripheral drivers in the
future to override hardware behavior.
* arch/mips/src/pic32mz/pic32mz_serial.c
(struct up_dev_s): Add new field 'brk' to indicate line break in
progress when built with PIC32MZ_UART_BREAKS. If generating BSD-
compatible BREAKs, also add tx_gpio, tx_pps_reg, and tx_pps_val, to
let us toggle the pin between UART and GPIO modes.
(up_ioctl): Add cases for TIOCSBRK and TIOCCBRK to turn BREAK on and
off, with both hardware-native and BSD-compatible implementations.
This is similar to the STM32F7 implementation.
(up_txint): Block enabling TX interrupt if line break in progress.
This is similar to the STM32F7 implementation.
Updating Simulator for macOS
macOS requires genromfs and X11 Libraries to run Simulators.
* Added instructions to install genromfs
* Added instructions to install X11
Adding Xorg Server
The linker was unable to identify the location of X11 libraries.
removed -L/opt/X11/lib from ln 145
Updating Changes to streamline with other Hosts
The PIC32MZ architecture provides a Peripheral Pin Select (PPS) which
allows mapping peripherals to different GPIO pins. To map a peripheral
output, a value is programmed to a register called RPnxR, where n is
the GPIO port (A thru K) and x is the GPIO pin (0 thru 15). The names
of these registers in code are PIC32MZ_RPnxR. However, in various
definitions, these were mistakenly written as PI32MZ_RPnxR (missing C
in PIC32). This prevents using any of the affected mappings. This
issue is fixed by repairing the define names.
* arch/mips/src/pic32mz/hardware/pic32mzec_pps.h,
arch/mips/src/pic32mz/hardware/pic32mzef_pps.h:
(): s/PI32MZ/PIC32MZ/g
The defines for Peripheral Pin Select (PPS) register RPE5R were called
RPE4R inadvertently; however, mappings elsewhere in the file used the
correct name of RPE5R, so the build would break if anyone attempted to
map those peripherals to GPIO pin E5. This issue is now fixed.
* arch/mips/src/pic32mz/hardware/pic32mzec_pps.h,
arch/mips/src/pic32mz/hardware/pic32mzef_pps.h:
(PIC32MZ_RPE4R_OFFSET): Rename to PIC32MZ_RPE5R_OFFSET.
(PIC32MZ_RPE4R): Rename to PIC32MZ_RPE5R.
When I checked how this register was set I discovered that 128 was not
accepted by the H7 but 64 was ok. Looking at the STM32Cube's HAL it
seems to be only 64 words long, however, the reference manual claims
otherwise.
I have opened a discussion on the ST community forum
https://community.st.com/s/question/0D73W000001nzqFSAQ
but unfortunately not received an answer yet.
In the meantime, I think, we should update this to what I found to be
working though.
Signed-off-by: Julian Oes <julian@oes.ch>
user_main: vfork() test
=================================================================
==3754757==ERROR: AddressSanitizer: stack-buffer-underflow on address 0xae9126f0 at pc 0x56845661 bp 0xae912570 sp 0xae912560
READ of size 1 at 0xae9126f0 thread T0
#0 0x56845660 in memcpy string/lib_memcpy.c:44
#1 0x56b70f61 in up_vfork sim/sim_vfork.c:133
#2 0x567c0b85 in vfork (/home/ligd/platform/sim/nuttx/nuttx+0x26bb85)
0xae9126f0 is located 73456 bytes inside of 73728-byte region [0xae900800,0xae912800)
allocated by thread T0 here:
#0 0xf7ab1c2f in __interceptor_posix_memalign ../../../../../src/libsanitizer/asan/asan_malloc_linux.cpp:226
SUMMARY: AddressSanitizer: stack-buffer-underflow string/lib_memcpy.c:44 in memcpy
Signed-off-by: ligd <liguiding1@xiaomi.com>
Current implementation supports the trigger generation only from timer
capture on period value. This is sufficient for PWM synchronization but
may not be enough for other purposes as ADC triggering for example.
This change adds an option to generate the trigger based on a duty
cycle value.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
The function call dac_txdone(&g_dac1dev) was not contained in ifdef
section. This was cousing compilation error if only DAC1 was configured
as the structure g_dac1dev is defined only if DAC0 is used.
This commit fixes the error and ensures the function is called only if
corresponding DAC is configured.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
First decoupling changes related to CMAKE
BINDIR/APPSBINDIR:
Output path of Kconfig which dynamically generated by NuttX Kernel/Apps
This option is consistent with the TOPDIR/APPSDIR by default, and will
be changed when out-of-tree compilation is supported
Signed-off-by: chao an <anchao@xiaomi.com>
sim/sim_doirq.c: In function 'sim_doirq':
Error: sim/sim_doirq.c:79:10: error: function may return address of local variable [-Werror=return-local-addr]
79 | return regs;
| ^~~~
sim/sim_doirq.c:44:14: note: declared here
44 | xcpt_reg_t tmp[XCPTCONTEXT_REGS];
| ^~~
Signed-off-by: ligd <liguiding1@xiaomi.com>
