This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.
It also makes the code look more similar to the ESP32-S3 SPI flash
implementation by creating a common `esp32_spiflash_init` that is
responsible to create the SPI flash operation tasks. The function
intended to initialize the SPI flash partions was, then, renamed to
`board_spiflash_init`.
During PSRAM initialization and flash operations, the Cache needs to be disabled.
So all data and code for the aforementioned scope is required to be placed in Internal RAM.
After https://github.com/apache/nuttx/pull/11007/ was merged, the
path for some files changed, requiring the linker to be fixed to
make it run from the internal memory once again.
Using up_textheap_memalign to allocate memory if arch support textheap
for loading section.
The default system heap does not support execution permissions,
so up_textheap_memalign allocation is required.
this patch can fix issue about #11043
update esp32 elf config:
remove -CONFIG_ARCH_USE_TEXT_HEAP=y becuase ARCH_CHIP_ESP32 select
ARCH_HAVE_TEXT_HEAP
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
- migrated /README are removed from /boards
- there are a lot of READMEs that should be further converted to rst.
At the moment they are moved to Documentation/platforms and included in rst files
This commit sets the BLE's interrupt as a IRAM-enabled interrupt,
which enables it to run during a SPI flash operation. This enables
us to create a cache to off-load semaphores and message queues
operations and treat them when the SPI flash operation is finished.
By doing that, we avoid packet losses during a SPI flash operation.
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.
The board-level GPIO support is different from the already existing
button and LEDC support because it enable us to register the GPIO
pins as devices in `/dev/gpioX`. Some applications are able to use
this interface to read and write the GPIO pins.
Documentation was added regarding its usage. Please check
`Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst`
Provide initial support for audio through the I2S peripheral to the
CS4344 audio codec on ESP32-S3-DevKitC-1 board.
Please check documentation for usage examples.
