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18111 Commits

Author SHA1 Message Date
Abdelatif Guettouche
5b350f3a0f arch/*_reprioritizertr.c: Fix typos in comments. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-14 11:19:34 -07:00
Gustavo Henrique Nihei
1dfcc6ab49 xtensa/esp32: Enable boot from Espressif's port of MCUboot 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-08-13 08:44:20 -03:00
zhuyanlin
1a1b1cc2b4 arch:xtensa: replace include file from src/chip_xxx to chip.h 
Use chip.h as a standard include file, replace chip_xxx in src dir
 2021-08-12 16:18:35 +02:00
zhuyanlin
30a2338e92 arch:esp: create chip.h header for chip src code. 
Create chip.h header for esp src code.
 2021-08-12 16:18:35 +02:00
zhuyanlin
6d592256fb arch:xtensa: add __ASSEMBLY__ for espxxx_soc.h 
Those header contain syntax not be recognize by gnu assembler.
 2021-08-12 16:18:35 +02:00
Alexander Vasiljev
4229099944 arch/arm/stm32h7: dma and serial: add TRBUFF flag. It is obligatory for uart. 2021-08-12 08:07:18 -03:00
Xiang Xiao
6b6c11f0ad mtd: Replace MTDIOC_XIPBASE with BIOC_XIPBASE 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-12 08:01:29 -03:00
Xiang Xiao
d1687418db mtd: Remove the empty MTDIOC_XIPBASE implmentation 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-11 09:50:51 -03:00
zhuyanlin
e333733053 xtensa:coproc: fix XTENSA_CP_ALLSET error in some case 
Consider follow coprocessor configuration case:

\#define XCHAL_CP_NUM                    1       /* number of coprocessors */
\#define XCHAL_CP_MAX                    2       /* max CP ID + 1 (0 if none) */
\#define XCHAL_CP_MASK                   0x02    /* bitmask of all CPs by ID */
\#define XCHAL_CP_PORT_MASK              0x00    /* bitmask of only port CPs */
\
\#define XCHAL_CP1_NAME                  "AudioEngineLX"
\#define XCHAL_CP1_IDENT                 AudioEngineLX
\#define XCHAL_CP1_SA_SIZE               208     /* size of state save area */
\#define XCHAL_CP1_SA_ALIGN              8       /* min alignment of save area */
\#define XCHAL_CP_ID_AUDIOENGINELX       1       /* coprocessor ID (0..7) */

In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors
bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all
vaild coprocs.

Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f
 2021-08-10 19:44:55 -07:00
Abdelatif Guettouche
054e284785 *_cpustart.c: Fix typos in function description. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-11 11:06:27 +09:00
Fotis Panagiotopoulos
5b7ff03f40 lpc17_40: Fixed I2C port sanity check. 2021-08-10 09:04:33 -07:00
raiden00pl
2b3106fb47 Qencoder implementations for imxrt, stm32f7, stm32h7, stm32l4 and tivia don't support QEIOC_SETPOSMAX 2021-08-10 11:19:05 -03:00
raiden00pl
51b24c4bad stm32/qenco: add support for QEIOC_SETPOSMAX 2021-08-10 11:19:05 -03:00
raiden00pl
092a0c8453 stm32/qenco: add an option to disable encoder timer extension from 16-bit to 32-bit 
Previous implementation has always expanded the width of the timer to 32-bit.
This feature is not always needed and should be configurable from Kconfig.
 2021-08-10 11:18:40 -03:00
raiden00pl
b0c9a6133e stm32/qenco: fix TIM2 width for STM32F3 which is 32-bit not 16-bit 
STM32F3 has timers of the same length as in STM32F4.
 2021-08-10 11:18:40 -03:00
raiden00pl
3dd385ac0c stm32/qenco: add support for STM32G4 
This required generalization of RCC definitions that are not compatible with previous chips
 2021-08-10 11:18:40 -03:00
raiden00pl
21f59c874f stm32/qenco: fix compilation for STM32F1. GTIM_CCER_CCxNP bits are not present in F1 2021-08-10 11:18:40 -03:00
Sara Souza
af6c311fd1 risc-v/esp32-c3: Complete the support for RWDT 2021-08-10 11:17:15 -03:00
Sara Souza
61ab4f9f14 xtensa/esp32: Fix the type of enum passed between functions in esp32_rtc_clk 2021-08-10 11:15:51 -03:00
Sara Souza
67d29e7537 xtensa/esp32: initialize RTC in case PM or RTC configs are not set, but RWDT is. 2021-08-10 11:15:51 -03:00
zhuyanlin
5820972727 arch:xtensa: add arch stdarg.h include file for xtensa 
Add arch/include/stdarg.h for xtensa.

Change-Id: Ia914ca0f4c95e86b130983ce690479a994a08b56
 2021-08-09 17:58:25 -03:00
Xiang Xiao
776458143c fs/hostfs: Support fchstat and chstat callback 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-09 17:55:44 -03:00
Xiang Xiao
7e0db977cc arch/arm: Add CONTROL register bit field definition 
and replace all hardcode value

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-07 09:20:10 -03:00
Daniel P. Carvalho
a7be1c9a2e stm32_pmw: fix pwm_stop() function to enable multiple PWM start and stop. 2021-08-05 14:48:44 -03:00
Michal Lenc
a3986eeba3 arch/arm/src/imxrt/imxrt_flexpwm.c: Set LDOK bits after all channels are set 
This commit changes the FLexPWM driver for iMXRT MCU so that LDOK bits in
Master Control Register are set at once after all channels are configured.
Setting LDOK bit enables the driver to load prescaler, modulus and PWM
values of corresponging submodule and start PWM output. Setting all bits
at once instead of doing it separately can help avoiding the channels to
be out of sync with each other.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-08-05 09:57:49 -07:00
zhuyanlin
ec17cad69d arch:xtensa:include chip/irq.h instead of depend on chip config. 
Many duplicate code when more chips add-in,
follow arch/arm/include/irq.h method, use chip/irq.h instead.

Change-Id: I42f516c1dda68e973939c669f627c457cd0bc65e
 2021-08-05 10:08:48 +02:00
zhuyanlin
cec6aeb059 arch:xtensa:vector: fix typo error in level4_ventor 
Change-Id: I66cd3ff30e50e18ed718499aef609dd7aeb82dd3
 2021-08-04 20:16:41 -07:00
zhuyanlin
51d13df317 arch: xtensa: save current SP before overwrting in dispatch_c_isr. 
In levelx(2,3,4,5)_handler, first need to save sp in a12,
then after dispatch_c_isr we can restore sp from a12.

Change-Id: Idb6b64a782da866670a4db80b33435a9b63f02c3
 2021-08-04 20:16:41 -07:00
Daniel P. Carvalho
2593089f84 stm32_dac: add support for DAC3 2021-08-04 20:22:58 +02:00
zhuyanlin
4fc5b62ec3 arch:xtensa: use letter 'i' in inline assemble constraint instead of I 
Some toolchain such as xtensa-xcc is unrecognize with constraint letter 'I',
letter 'i' is more common in GNU assembler.

Change-Id: I00f6a33fd7a5f2b95508c683e9954d402b68755f
 2021-08-04 18:23:40 +02:00
zhuyanlin
9a34705b80 arch:xtensa_testset: remove include arch/spinlock.h 
In config with no "CONFIG_SPINLOCK", include arch/spinlock.h will lead to
build error as multi definition with spinlock_t. Nuttx/spinlock.h will
include arch/spinlock.h when needed.

Change-Id: I33b48503f679ec79af3a0ef1f0fb1536aaf1ce7c
 2021-08-04 18:18:11 +02:00
zhuyanlin
355133f218 arch:xtensa: add new GNU toolchain for xtensa. 
Add support xcc,xclang GUN toolchin in xtensa,
ESP toolchain is default.

Change-Id: Id00bcf4a16c1e16862a106db32b1da3f3713a14c
 2021-08-04 18:16:14 +02:00
Xiang Xiao
6a396eb224 Fix the printf warning after off_t change 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Id46daa2ee690a73d3187b479f0e7ab0e2e361764
 2021-08-04 06:48:30 -07:00
Abdelatif Guettouche
238a96e7de arch/esp32_cpuint.c: Simplify up_disable/enable_irq. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
4f2f2ef9fb arch/xtensa: Get the cpu member out of the read only structure. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
239f0e257b arch/xtensa/esp32: Keep track to which CPU the interrupt was attached. 
This is used when dettaching.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
0ca5fb4edc arch/xtensa/esp32: When calling up_cpu_index no need to check if in SMP 
mode.  up_cpu_index already does that.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
3e44c347fd arch/xtensa/esp32_spi&i2c: Get the CPU index when attaching an 
interrupt.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
licheng
431df45e97 EXC_SECURE and SECURE_STACK just can clear at TRUSTZONE_NONSECURE 2021-08-02 23:20:34 -07:00
Alexander Lunev
95abf562f4 boards: added a basic support for chipKIT Wi-FIRE board; 
added Sourcery CodeBench Lite for MIPS ELF Toolchain option;
corrected inaccuracies in Photon board and EMW3162 board README.txt files.
 2021-08-01 08:45:02 -07:00
buyuer
ae3709819c Use exit func iml host_abort. 
When use poweroff command,host_abort will be called,but may be make __stack_chk_fail irq, and host_abort be called in PANIC(), so bring infinite loop, in turn it can not exit SIM.

Signed-off-by: buyuer <dingddding@163.com>
 2021-07-31 08:02:10 -07:00
Xiang Xiao
5d1a444812 Replace __attribute__ ((unused)) with unused_code 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
69df58c2e8 Replace __attribute__((no_instrument_function)) with noinstrument_function; 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
7bcd29dae0 Replace __attribute__((naked, no_instrument_function)) with naked_function 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
919f8a9a72 Define __ramfunc__ to "locate_code(".ramfunc") farcall_function noinline_function" 
instead of "__attribute__ ((section(".ramfunc"),long_call,noinline))"

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
21b69cfd5d Replace all __attribute__((weak)) with weak_data/weak_function 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
007adc7736 Replace all __attribute__((section(x)) with locate_data(x) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
b3f9ffbe72 Replace all __attribute__((aligned(x)) with aligned_data(x) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Gustavo Henrique Nihei
a7a922611b xtensa/esp32: Enable the allocation of multiple SPI Flash partitions 
Currently the "esp32_spiflash_alloc_mtdpart" allocates a
statically-defined partition from "offset" and "size" set via
Kconfig.
This commit changes the function interface to receive those information
as arguments, enabling the creation of multiple MTD partitions with
different offsets and sizes.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-29 20:17:13 +02:00
Alexander Lunev
98e7776714 pic32mz: added support for PIC32MZ2048EFG MCU 2021-07-29 07:46:26 -07:00
raiden00pl
f9937b28cc stm32g4: add CORDIC driver 2021-07-28 14:23:13 -03:00
raiden00pl
6128b298ee stm32g4: add CORDIC definitions 2021-07-28 14:23:13 -03:00
Sara Souza
cdbfacc1fe risc-v/esp32-c3: Adds systimer support and make rt_timer rely on it 2021-07-27 20:43:34 -07:00
Sara Souza
857414e95d xtensa/esp32: expose SPI2 as a char driver 2021-07-27 09:55:49 -07:00
Michal Lenc
9fc806984c adc: add ioctl command to get the number of configured channels 
Number of configured ADC channels is currently only defined in board
level section, typically in xxx_adc.c file. This commit introduces
ioctl command ANIOC_GET_NCHANNELS that returns the number of configured
channels which is determined by the driver code. The change can allow the
applications to be more flexible when it comes to multiple ADC devices
with different number of configured channels.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-07-26 19:45:47 -07:00
Sara Souza
400d927011 xtensa/esp32s2: Disable wdt and wrap it. 2021-07-26 19:44:30 -07:00
Sara Souza
0794991a07 risc-v/esp32-c3: Disable wdt in the start function. 2021-07-26 19:44:30 -07:00
Sara Souza
5baeb7430b xtensa/esp32: Wrap wdt deinitialization in a function 2021-07-26 19:44:30 -07:00
Jiuzhu Dong
7e393762a7 sim/rptun: optimize multi-core startup and don't need to wait each other. 
Change-Id: I6172823c84a96e4082fa5f33bdb05d7bd1d3b056
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-07-26 19:38:07 -07:00
Gustavo Henrique Nihei
2d676f5e46 xtensa/esp32: Enable configuration of GPIO pad's drive strength 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-26 19:37:06 -07:00
Jiuzhu Dong
e98220c81a sim/cmdline: save boot cmdline to g_argc g_argv 
Change-Id: I989850a09528e3868957284c9f419d0992ae8d1f
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-07-26 19:35:58 -07:00
Xiang Xiao
5e01fe050a arch/sim: Copy include/nuttx/config.h to the local folder 
so the source code compiled by host environment can include config.h
directly and then avoid pass Kconfig option through Makefile manually

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ic9fe6f846082cef2d0808dc717df8ae6ed929edf
 2021-07-27 07:44:33 +09:00
Xiang Xiao
3488a98bd7 sim: Correct the typedef in nuttx/hostfs.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I5fbfd519417c5686325822549c068b1d42f83946
 2021-07-27 07:44:33 +09:00
Jiuzhu Dong
5029712283 renesas/rx65n: add long type for all PRI*PTR 
Error: wqueue/kwork_thread.c:202:3: error: format '%x' expects argument of type 'unsigned int',
 but argument 4 has type 'long unsigned int' [-Werror=format=]
    snprintf(args, 16, "0x%" PRIxPTR, (uintptr_t)wqueue);

Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-07-26 08:44:05 -07:00
Michal Lenc
7354ab187e pwm: add option to break the loops when using multiple PWM channels 
PWM drivers currently use channel number 0 for the channels that are not
used by the application. This commit adds number -1 which indicates that
all following channels are not configured and that the loop can be broken.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-07-26 10:34:16 -03:00
Nathan Hartman
b92aeb8209 Fix various typos 
arch/arm/src/eoss3/eoss3_serial.c:
arch/arm/src/imxrt/hardware/imxrt_flexcan.h:
arch/arm/src/imxrt/imxrt_flexcan.c:
arch/arm/src/imxrt/imxrt_flexpwm.c:
arch/arm/src/imxrt/imxrt_lpi2c.c:
arch/arm/src/kinetis/kinetis_flexcan.c:
arch/arm/src/nrf52/hardware/nrf52_rtc.h:
arch/arm/src/nrf52/nrf52_clockconfig.c:
arch/arm/src/nrf52/nrf52_radio.c:
arch/arm/src/nrf52/nrf52_tim.c:
arch/arm/src/rtl8720c/amebaz_depend.c:
arch/arm/src/s32k1xx/Kconfig:
arch/arm/src/s32k1xx/s32k1xx_flexcan.c:
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c:
arch/arm/src/sama5/hardware/sam_sdmmc.h:
arch/arm/src/sama5/sam_gmac.c:
arch/arm/src/samd5e5/sam_wdt.c:
arch/avr/src/avr32/up_exceptions.S:
arch/avr/src/avr32/up_fullcontextrestore.S:
arch/renesas/src/rx65n/rx65n_dtc.c:
arch/renesas/src/rx65n/rx65n_usbhost.c:
arch/risc-v/src/esp32c3/esp32c3_tickless.c:
boards/arm/stm32h7/stm32h747i-disco/include/board.h:
include/nuttx/lcd/ili9225.h:
libs/libc/stdio/lib_fgetpos.c:
libs/libc/stdio/lib_fseek.c:
libs/libc/stdio/lib_fsetpos.c:

    * Fix typos.
 2021-07-25 18:36:53 -07:00
hartmannathan
c475a71d1c Update arch/arm/src/stm32/Kconfig 
Co-authored-by: Gustavo Henrique Nihei <38959758+gustavonihei@users.noreply.github.com>
 2021-07-25 14:16:22 -03:00
hartmannathan
bb5f302361 Update arch/arm/src/stm32l5/stm32l5_serial.c 
Co-authored-by: saramonteiro <saramonteirosouza44@gmail.com>
 2021-07-25 14:16:22 -03:00
Nathan Hartman
f617c27a8c arch: arm: stm32, stm32f0l0g0, stm32h7, stm32l4, stm32l5: Fix typos. 
arch/arm/src/stm32/stm32_foc.c,
arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h,
arch/arm/src/stm32h7/stm32_allocateheap.c,
arch/arm/src/stm32h7/stm32_fmc.c,
arch/arm/src/stm32h7/stm32_pmstandby.c,
arch/arm/src/stm32h7/stm32_spi.h,
arch/arm/src/stm32h7/stm32_spi_slave.c,
arch/arm/src/stm32h7/stm32_wwdg.c,
arch/arm/src/stm32l4/stm32l4_adc.h,
arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h,
arch/arm/src/stm32l5/stm32l5_gpio.c,
arch/arm/src/stm32l5/stm32l5_gpio.h,
arch/arm/src/stm32l5/stm32l5_irq.c,
arch/arm/src/stm32l5/stm32l5_rcc.c,
arch/arm/src/stm32l5/stm32l5_rcc.h,
arch/arm/src/stm32l5/stm32l5_serial.c, and
arch/arm/src/stm32l5/stm32l5_spi.c:

    * Fix typos in comments. No functional changes.
 2021-07-25 14:16:22 -03:00
Nathan Hartman
3346ba304b arch: arm: stm32, stm32h7, stm32l5: Fix typos in KConfig help texts 
arch/arm/src/stm32/Kconfig:
* In configs STM32_ADC_MAX_SAMPLES, STM32_FOC_HAS_PWM_COMPLEMENTARY:
  Fix typos in help text.

arch/arm/src/stm32h7/Kconfig:
* In configs STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY,
  STM32H7_FLASH_CR_PSIZE, STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY,
  and STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY: Fix typos in help text.

arch/arm/src/stm32l5/Kconfig:
* In configs STM32L5_FLOWCONTROL_BROKEN, STM32L5_SDMMC1_DMAPRIO: Fix
  typos in help text.
 2021-07-25 14:16:22 -03:00
Nathan Hartman
d178ff8a02 arch: arm: stm: Fix STM32_EXTI2_OFFSET 
arch/arm/src/stm32/hardware/stm32_exti.h:
* Change STM32_EXTI2_OFFSET (offset to EXTI2 registers) from 0x18
  to 0x20. This symbol is defined when CONFIG_STM32_STM32F30XX or
  CONFIG_STM32_STM32F33XX. According to the current reference
  manuals for STM32F334xx (RM0364 rev 4) and STM32F302xx (RM0365
  rev 8), EXTI_IMR1 is at offset 0x00 and EXTI_IMR2 is at offset
  0x20, i.e., 0x20 apart. The same offset applies to the rest of
  the registers: EMR1/EMR2, RTSR1/RTSR2, etc.
 2021-07-24 16:53:14 +02:00
Michal Lenc
4985f47155 arch/arm/src/stm32/stm32_qencoder.c: print uint32_t by using standard format PRIx32 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-07-24 04:22:11 -07:00
jordi
b87333bae8 Kconfig: remove empty help sections 
To avoid the setconfig warning: "has 'help' but empty help text"
 2021-07-23 02:32:19 -07:00
jordi
1e44270558 Kconfig: add quotes in default string value 
To avoid the setconfig warning: "style: quotes recommended around
default value for string symbol"
 2021-07-23 02:32:19 -07:00
jordi
f3af6edf93 Kconfig: add quotes in source to clean warnings from setconfig 
To avoid the setconfig warning "style: quotes recommended around xxx in
source xxx"
 2021-07-23 02:32:19 -07:00
Masayuki Ishikawa
6d65e9f38e arch: sim: Add NuttX symbols to make SMP work correctly 
Summary:
- I noticed that sim:smp does not work correctly on macOS
  due to the recent changes
- Actually, it can not receive the IPI host signal, so if
  a new task is scheduled on CPU1/2/3, it hangs.
- Finally, I found that sim_cpu_start() calls pthread_attr_init()
  which locates not on the host OS but on the NuttX
- This commit fixes this issue by adding the symbol names
  to nuttx-names.in

Impact:
- sim in SMP mode
- NOTE: stack usage for CPU1/2/3 IDLE is still incorrect on macOS

Testing:
- Tested with ostest on Ubuntu 18.04 (x86_64) and macOS 11.4 (x86_64)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-07-22 09:03:30 -07:00
Masayuki Ishikawa
4f1e63f939 Revert "arch: sim: Workaround to make the IPI work on macOS" 
This reverts commit b68fc9eb1d.
 2021-07-22 09:03:30 -07:00
Xiang Xiao
2ef6428aa8 arch/sim: Don't need pass CONFIG_SCHED_INSTRUMENTATION to host side 
since this macro isn't check from host side after:
commit cee43ce280
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date:   Fri Jul 16 02:23:59 2021 +0800

    arch/sim: Initialize the idle thread stack info correctly

    and change the default value of IDLETHREAD_STACKSIZE to 65536

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-22 07:59:58 -07:00
ligd
4919d9b7df arm: add up_secure_irq support 
Change-Id: Ibc9402dcef4045ca122da400940d57de6b508308
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-07-22 10:50:53 -03:00
ligd
29d6a6dcd3 arch: add depends to trigger_irq 
Change-Id: I334f625f8f1a6ebaa4fa5ea292de142a93120f51
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-07-22 10:50:53 -03:00
Masayuki Ishikawa
b68fc9eb1d arch: sim: Workaround to make the IPI work on macOS 
Summary:
- I noticed that sim:smp does not work correctly on macOS
  due to the recent changes
- Actually, it can not receive the IPI host signal, so if
  a new task is scheduled on CPU1/2/3, it hangs.
- Finally, I found the issue depends on pthread stack settings
  and perhaps it might affect the host signal handling.
- This commit fixes this issue by just reverting the pthread
  stack setting only for macOS.

Impact:
- sim:smp on macOS
- Stack usage for CPU1/2/3 IDLE will be incorrect

Testing:
- Tested with ostest on macOS 11.4 (x86_64)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-07-22 09:47:19 +02:00
Abdelatif Guettouche
e85b119363 arch/: Clean what was made during context in distclean. 
Cleaning during `clean_context` had the issue of remaking everything
when `menuconfig` was issued.  That's because `menuconfig` has a
`clean_context` on its way.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-07-21 16:52:36 -03:00
Abdelatif Guettouche
315ba8c77f esp32_allocateheap.c: Remove the amount reserved to himem from the heap. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-07-21 08:58:18 -07:00
Alan C. Assis
011c938116 Remove xtensa_backtrace.S reference from esp32s2 as well 2021-07-20 19:30:09 -07:00
Alan C. Assis
d2eeeee262 Fix xtensa_btdump() to look at the exception frame 
Remove xtensa_backtrace_start() since it is not used anymore
 2021-07-20 19:30:09 -07:00
David Sidrane
19fddc451c Kintis:LPUART add RX DMA 2021-07-20 19:28:51 -07:00
David Sidrane
34eb918665 kinetis:LPUART Add IOCTL for invert 2021-07-20 19:28:51 -07:00
Nathan Hartman
609ee6b54b Fix typos in comments and identifiers 2021-07-19 22:55:30 -03:00
ligd
aac0db368c ARM: fix CPSR corruption after exception handling 
It seems to be caused by the corrupted or wrong CPSR restored on return
from exception. NuttX restores the context using code like this:

    msr spsr, r1

GCC translates this to:

    msr spsr_fc, r1

As a result, not all SPSR fields are updated on exception return. This
should be:

    msr spsr_fsxc, r1

This bug has been fixed by Heesub Shin in:
343243c7c0

Change-Id: Ibc64db7bceecd0fb6ef39284fb5bc467f5603e2e
 2021-07-19 08:41:06 -03:00
Gustavo Henrique Nihei
c05feda208 risc-v/esp32c3: Implement MTDIOC_ERASESTATE for SPI Flash driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-17 09:00:41 -07:00
Gustavo Henrique Nihei
50ea22314e arm/lpc43xx: Implement MTDIOC_ERASESTATE for SPIFI Flash driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-17 09:00:41 -07:00
Gustavo Henrique Nihei
df2e890cfc xtensa/esp32: Implement MTDIOC_ERASESTATE for SPI Flash driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-17 09:00:41 -07:00
Xiang Xiao
4444c13c14 arch/sim: The second CPU shouldn't call up_irqinitialize 
since the signal handler the process concept

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-17 07:48:27 +09:00
Xiang Xiao
98b5724b59 arch: Fix rtcb can't found error 
use the same condition check in declaration and reference

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I7b05316e914708fceeddac394d784ee3720a3c1b
 2021-07-16 12:48:09 -03:00
Xiang Xiao
3204c75c1d arch/sim: Remove the unused sim_host_timer_handler 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Icacbe74308580b7fc2449cdf9e41f85fce43d5a4
 2021-07-16 17:41:00 +09:00
ChenWen
2abb75fee7 risc-v/esp32c3: Fix some ESP32-C3 Wi-Fi driver issues 2021-07-15 23:20:29 -07:00
Roberto Bucher
fc810e3db4 Restored previous files 2021-07-15 23:19:59 -07:00
Xiang Xiao
cee43ce280 arch/sim: Initialize the idle thread stack info correctly 
and change the default value of IDLETHREAD_STACKSIZE to 65536

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia54efbbca4b69706150bc4178844b316688a104e
 2021-07-16 08:37:53 +09:00
David Sidrane
da01a39e39 Revert "Kinetis:Serial No DMA Poll needed" 
This reverts commit e659ae83b0.

    It turns out the DMA polling is needed. The IDLE INT will
    not happen on repetitive signals.
 2021-07-15 12:28:04 -07:00
Daniel P. Carvalho
3ca46ea8e2 Change DAC driver to support STM32G4. 2021-07-15 14:33:15 -03:00
Fotis Panagiotopoulos
7f361daf60 lpc17_40: style fix in WDT definitions. 2021-07-13 08:32:42 -07:00
Michal Lenc
3d26c3efb6 fix nxstyle errors and warnings 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-07-13 09:55:29 -03:00
Michal Lenc
b2a9f853e8 arch/arm/src/imxrt: added support for Tickless OS 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-07-13 09:55:29 -03:00
Virus.V
063e1d6b74 risc-v/bl602: update wifi firmware and some fixup. 
1. Added check for repeated connection wifi operations.
2. Invoke the carrier on/off operation in the wrong place.
3. The RTC initialization time is incorrect.
4. Reserve 32K I-Cache space in the linker script.
5. Increase the size of the wifi firmware receiving buffer.

Signed-off-by: Virus.V <virusv@live.com>
 2021-07-13 05:12:12 -07:00
Sara Souza
48f2b10ee3 risc-v/esp32-c3: Use systimer 0 to RTOS TICK 2021-07-12 21:03:27 -07:00
Sara Souza
c7bf5c7a1d xtensa/esp32: Make UART TX DMA depends on EXPERIMENTAL and adds caveats regarding its use 2021-07-12 21:03:06 -07:00
Sara Souza
2abeba041d xtensa/esp32: Fixes termios issue. 2021-07-12 21:02:26 -07:00
Dong Heng
f5eaf82c93 risc-v/esp32c3: Use onexit to free thread private semaphore 2021-07-12 09:38:21 -03:00
Jiuzhu Dong
9b1f554429 sched: Dynamically extend the pid hash table 
Change-Id: I3a719bc575cd408cd530a39efa203f507b44fa9c
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-07-11 19:42:30 -07:00
Xiang Xiao
5fe51b923a mm: Simplify the semaphore handling 
1.Move all special process to mm_takesemaphore
2.Remove the support of recurive lock
3.Remove mm_trysemaphore function

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ie216a6294ab67c5d427f31b089beb15c532f08fe
 2021-07-10 16:10:32 -03:00
ligd
f5279f8583 sim: fix loop add delaylist when mm_free in IDLE thread 
Change-Id: I1827c663275f47c9dc30d63e17e3d016b0000166
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-07-10 16:10:32 -03:00
Fotis Panagiotopoulos
61cb524fa2 lpc17_40: Fixed progmem driver. 2021-07-09 21:49:16 -07:00
Jerry_tang
1e3a985155 AmebaZ2: Add soc src code 
Add soc src code for rtl8720c

Signed-off-by: Jerry_tang <jerry_tang@realsil.com.cn>
 2021-07-09 14:29:06 -03:00
guowei15
95b5dc523e arm/setjmp.h:add c++ support 
N/A

Change-Id: I619cc15570adeff10f3a9b69bf9a3cff83e625c1
Signed-off-by: guowei15 <guowei15@xiaomi.com>
 2021-07-09 14:06:10 -03:00
David Sidrane
282ab797bf stm32h7:Ethernet Add some delays so that ifup() does not hog the CPU. 2021-07-08 21:14:29 -05:00
David Sidrane
70c9cd1508 stm32h7:ethernet add timeout on MAC reset 2021-07-08 21:14:29 -05:00
David Sidrane
bf4e97177a stm32h7:Ethernet fix formating 2021-07-08 21:14:29 -05:00
Xiang Xiao
e97ffb1f79 arch/armv7-a: Remove the special SMP SGI process 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Iaf7fe77a3ab7cbf145d907dafb0b7ca54cc4a012
 2021-07-09 07:53:05 +09:00
Daniel P. Carvalho
2692b61a72 Fix newline at end of file. 2021-07-07 21:34:58 -03:00
Daniel P. Carvalho
ea701a84f2 Fix comments. 2021-07-07 21:34:58 -03:00
Daniel P. Carvalho
2a21c45e0a Add STM32G43XX Analog Comparator driver. 2021-07-07 21:34:58 -03:00
Xiang Xiao
76cdd5c329 mm: Remove mm_heap_impl_s struct 
it's more simple to make mm_heap_s opaque outside of mm

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I5c8e435f6baba6d22b10c5f7e8d9191104fb5af2
 2021-07-07 04:25:15 -07:00
cgeng
d656417917 Fix compilation error when CONFIG_DEBUG_PWM_INFO on stm32h7 2021-07-07 03:46:31 -05:00
Alexander Lunev
8fd64854f5 stm32,stm32f7,stm32h7: supported ETH MAC promiscuous mode 2021-07-06 19:11:56 -03:00
Fotis Panagiotopoulos
9976635390 lpc17_40: fixed compiler warnings. 2021-07-06 06:17:59 -05:00
Sara Souza
a5bf47b93e xtensa/esp32: Fixes issue with UART 2 2021-07-05 23:20:26 -05:00
Sara Souza
d67852da4b xtensa/esp32: Change default pins of UART2 2021-07-05 23:20:26 -05:00
Dong Heng
475becac37 risc-v/esp32c3: Add board_ioctl and board_uniqueid 2021-07-05 23:12:17 -05:00
Fotis Panagiotopoulos
2f0b4eb363 lpc17xx: Added WDT driver. 2021-07-05 11:25:51 -05:00
Xiang Xiao
75bfa4584c mm: Add kmm_malloc_size and mm_malloc_size 
make malloc_size implementation align with malloc

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I8d7781925f06e58a880437a16569dccbfd2ea035
 2021-07-05 14:23:24 +09:00
Xiang Xiao
ddaa3e42b9 mm: Move the real implementation of mm_sbrk to sbrk 
and remove mm_sbrk and kmm_sbrk since it's wrong to expose
sbrk to other heaps except the default userspace heap.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-05 08:02:08 +09:00
Xiang Xiao
b3f568c216 boards/sim: Add asan config to test the custom heap 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 18:53:44 -03:00
Xiang Xiao
4589c369be arch/sim: Implement mm_mallinfo for the custom heap 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 18:53:44 -03:00
Xiang Xiao
8ebf9c92cf arch/sim: Implement malloc_size for the custom heap 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 18:53:44 -03:00
Xiang Xiao
f240b2e631 arch/sim: Remove host_malloc and host_calloc 
use host_realloc instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 18:53:44 -03:00
Xiang Xiao
97216c220b mm: Support malloc_size function 
and rename malloc_usable_size to malloc_size

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 18:53:44 -03:00
Xiang Xiao
0941bad877 note: Move up_schednote.c to drivers/note folder 
since it is general enough to work on other target

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 18:52:32 -03:00
Nathan Hartman
ce20211357 Fix various typos in comments and documentation 
Fix typos in these files:
    * Documentation/components/drivers/character/foc.rst
    * Documentation/guides/cpp_cmake.rst
    * Kconfig
    * arch/arm/src/imxrt/imxrt_lpspi.c
    * arch/arm/src/kinetis/kinetis_spi.c
    * arch/arm/src/kl/kl_spi.c
    * arch/arm/src/lpc31xx/lpc31_spi.c
    * arch/arm/src/nrf52/nrf52_radio.h
    * arch/arm/src/s32k1xx/s32k1xx_lpspi.c
    * arch/arm/src/stm32/Kconfig
    * arch/arm/src/stm32/stm32_adc.c
    * arch/arm/src/stm32/stm32_foc.c
    * arch/arm/src/stm32/stm32_foc.h
    * arch/arm/src/stm32/stm32_pwm.c
    * arch/arm/src/stm32/stm32_spi.c
    * arch/arm/src/stm32f0l0g0/stm32_spi.c
    * arch/arm/src/stm32f7/Kconfig
    * arch/arm/src/stm32f7/stm32_spi.c
    * arch/arm/src/stm32h7/Kconfig
    * arch/arm/src/stm32h7/stm32_allocateheap.c
    * arch/arm/src/stm32h7/stm32_fmc.c
    * arch/arm/src/stm32h7/stm32_fmc.h
    * arch/arm/src/stm32h7/stm32_pwm.c
    * arch/arm/src/stm32h7/stm32_qspi.c
    * arch/arm/src/stm32h7/stm32_spi.c
    * arch/arm/src/stm32l4/stm32l4_pwm.c
    * arch/arm/src/stm32l4/stm32l4_spi.c
    * arch/arm/src/stm32l5/Kconfig
    * arch/arm/src/stm32l5/stm32l5_spi.c
    * arch/renesas/src/rx65n/rx65n_dtc.c
    * arch/renesas/src/rx65n/rx65n_usbdev.c
    * arch/risc-v/src/rv32m1/rv32m1_serial.c
    * boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c
    * boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c
    * boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c
    * boards/arm/stm32h7/nucleo-h743zi2/README.txt
    * boards/risc-v/rv32m1/rv32m1-vega/README.txt
    * boards/sim/sim/sim/scripts/Make.defs
    * drivers/1wire/1wire.c
    * drivers/1wire/1wire_internal.h
    * drivers/lcd/Kconfig
    * drivers/syslog/ramlog.c
    * fs/fat/Kconfig
    * libs/libc/debug/Kconfig
    * libs/libc/machine/Kconfig
    * libs/libc/stdio/lib_libvsprintf.c
    * libs/libc/stdlib/lib_div.c
    * libs/libc/stdlib/lib_ldiv.c
    * libs/libc/stdlib/lib_lldiv.c
    * libs/libdsp/lib_observer.c
 2021-07-04 11:23:26 -05:00
SPRESENSE
b3389cf751 arch: cxd56x: Add support for power management debug output 
Add support for power management debug output.
 2021-07-04 00:36:07 -05:00
SPRESENSE
7af6b394de arch: cxd56x: Add Kconfig for power management debug output 
Add configurations for power management debug output to Kconfig.
 2021-07-04 00:36:07 -05:00
SPRESENSE
4738f69569 arch: cxd56x: pmic: Fix a compile error 
Replace undefined logerr to _err function.
 2021-07-04 00:36:07 -05:00
SPRESENSE
5c26d68f31 arch: cxd56x: Add a configuration for PMIC interrupts 
Add a configuration for PMIC interrupts to Kconfig.
 2021-07-04 00:36:07 -05:00
SPRESENSE
618661df93 arch: cxd56xx: Fix compile error when CONFIG_LIBM is disabled 
It is no longer necessary to define CONFIG_ARCH_MATH_H when we would
like to link libm.a other than nuttx math library. So, this commit
removes the error condition.
 2021-07-04 00:36:07 -05:00
SPRESENSE
d29db87bdc arch: cxd56xx: Add eMMC configuration for vendor-specific commands 
The eMMC driver for cxd56xx has been implemented a vendor-specific command
for Toshiba eMMC device, and so add a new configuration to enable the code.
 2021-07-04 00:36:07 -05:00
SPRESENSE
cd06fc9761 arch: cxd56x: sdhci: Minor fix configuration name 
Modify the referenced CONFIG to CONFIG_DEBUG_MEMCARD_INFO.
 2021-07-04 00:36:07 -05:00
SPRESENSE
6a2733dd05 arch: cxd56x: emmc: Minor fix undefined configuration name 
Replace obsolete CONFIG_DEBUG_VERBOSE to CONFIG_DEBUG_FS_INFO.
 2021-07-04 00:36:07 -05:00
SPRESENSE
fa12fe9df1 arch: cxd56x: scu: Fix some printf format warnings 
Fix some printf format warnings by -Wformat.
 2021-07-04 00:36:07 -05:00
SPRESENSE
845da344fd arch: cxd56xx: Fix compile warning 
Fix warning by -Wimplicit-function-declaration
 2021-07-04 00:36:07 -05:00
SPRESENSE
75b6a260e0 arch: cxd56xx: Rename to nxsem_set_protocol 
nxsem_setprotocol function name was changed to nxsem_set_protocol.
Replace and fix hostif compile error.
 2021-07-04 00:36:07 -05:00
SPRESENSE
4364a291f0 arch: cxd56xx: Use arm_arch.h instead of up_arch.h 
Use arm_arch.h instead of up_arch.h and fix hostif compile error.
 2021-07-04 00:36:07 -05:00