Commit Graph

13 Commits

Author SHA1 Message Date
Xiang Xiao
cde88cabcc Run codespell -w with the latest dictonary again
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-02-23 22:27:46 +01:00
Juha Niskanen
2589fc943e arch/arm/src/stm32l4: Add initial support to STM32L4+ chips 2018-08-13 07:06:51 -06:00
Juha Niskanen
e402dadf5d arch/arm/src/stm32l4: Avoid using redundant CONFIG_STM32L4_STM32L4X2. This is almost always same as CONFIG_STM32L4_STM32L4X3. Avoid duplication to reduce macro clutter. This patch limits CONFIG_STM32L4_STM32L4X2 usage to dependency tracking and pinmap. Also enable ADC for CONFIG_STM32L4_STM32L4X5 (untested, but same RM). 2018-08-09 06:42:54 -06:00
Juha Niskanen
84f8e01c17 arch/arm/src/stm32l4: Fix ADC and COMP breakage caused by CONFIG_STM32L4_STM32L4X2 separation in 9223123c 2018-08-08 06:55:25 -06:00
Gregory Nutt
1567b82429 Make sure that labeling is used consistently in all function headers (part 2). 2018-02-01 12:03:55 -06:00
Gregory Nutt
7cf88d7dbd Make sure that labeling is used consistently in all function headers. 2018-02-01 10:00:02 -06:00
Juha Niskanen
9653255cff Merged in juniskane/nuttx_stm32l4/stm32l1_stm32l4_rtc_update_pr (pull request #514)
STM32L1, STM32L4 RTC: add periodic interrupts, update L1 RTC implementation

* STM32L4 RTC: add support experimental CONFIG_RTC_PERIODIC

* STM32 RTC: separate STM32L1 RTC into a separate file

    STM32L1 RTC is very close to F4 or L4 versions, with two alarms
    and periodic wakeup support so backported L4 peripheral to L1.

* RTC: add periodic alarms to upper and lower halves

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-10-20 17:15:17 +00:00
Juha Niskanen
2997a49e51 Merged in juniskane/nuttx_stm32l4/stm32l4_rtc_pm_fixes_pr (pull request #502)
STM32L4 RTC, PM: small fixes to subseconds handling, ADC power-management hooks

* STM32L4 ADC: add PM hooks from Motorola MDK

* STM32L4 RTC: add up_rtc_getdatetime_with_subseconds

* STM32 RTC: workaround for potential subseconds race condition

    In all recent STM32 chips reading either RTC_SSR or RTC_TR is supposed to lock
    the values in the higher-order calendar shadow registers until RTC_DR is read.
    However many old chips have in their errata this silicon bug (at least F401xB/C,
    F42xx, F43xx, L15xxE, L15xVD and likely others):

    "When reading the calendar registers with BYPSHAD=0, the RTC_TR and RTC_DR
    registers may not be locked after reading the RTC_SSR register. This happens
    if the read operation is initiated one APB clock period before the shadow
    registers are updated. This can result in a non-consistency of the three
    registers. Similarly, RTC_DR register can be updated after reading the RTC_TR
    register instead of being locked."

* STM32L4 RTC: correct RTC_SSR and RTC_TR read ordering

    In all recent STM32 chips reading either RTC_SSR or RTC_TR is supposed to lock
    the values in the higher-order calendar shadow registers until RTC_DR is read.
    Change the register read ordering to match this and don't keep a workaround
    for a hypothetical race condition (not in any L4 errata, lets for once assume
    ST's silicon works as it is documented...)

* STM32L4 PM: remove useless #ifdefs and old non-L4 STM32 code

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-10-03 16:39:51 +00:00
Juha Niskanen
abcaedb990 Merged in juniskane/nuttx_stm32l4/dfsdm_adc_work_pr (pull request #487)
STM32L4 ADC, DFSDM: add routing of ADC data to DFSDM filters

* configs/nucleo-l496zg: add DFSDM initialization

* STM32L4 ADC: add option for routing ADC data to DFSDM, fix DFSDM DMA

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-09-20 12:20:45 +00:00
Juha Niskanen
3719d0a395 Merged in juniskane/nuttx_stm32l4/stm32l4_adc_kconfig_pr (pull request #478)
STM32L4: ADC, Kconfig small changes

* STM32L4 ADC: port analog watchdog ioctls from the Motorola MDK

* STM32L4: Kconfig: add some L486 and L496 chips, remove duplicates

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-09-06 22:05:44 +00:00
Juha Niskanen
4025205772 STM32L4 DAC: add option for routing DAC output to ADC
Actually write something to the DAC DMA buffer.

Change-Id: I1b2516ac26fb17f5242611b56be8926c5f40c2c7
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2017-09-01 10:00:46 +03:00
Juha Niskanen
809569cda9 STM32L4 ADC: implement peripheral 2017-08-28 07:05:33 -06:00
Juha Niskanen
f383308a02 STM32L4 ADC: add ADC register definitions 2017-08-14 06:47:12 -06:00