Commit Graph

136 Commits

Author SHA1 Message Date
Sara Souza
6a6121378c xtensa/esp32: Fixed wdt typos 2020-12-22 20:32:38 +01:00
Sara Souza
16b1a87da4 xtensa/esp32: Added watcher defconfig 2020-12-21 20:20:43 +01:00
YAMAMOTO Takashi
7a9f180faf esp32: Bump NAME_MAX where CONFIG_ESP32_WIFI_SAVE_PARAM=y
CONFIG_ESP32_WIFI_SAVE_PARAM seems to use a bit long names
on the filesystem.
eg. "wifi.nvs.net80211.sta.scan_method", which is 33 characters long.
2020-12-21 09:58:22 +01:00
Sara Souza
add46d0408 xtensa/esp32: Added support for RTC WDT 2020-12-16 14:37:39 +01:00
John Bampton
ba12c6c0cf Fix spelling 2020-12-12 19:18:08 +01:00
Abdelatif Guettouche
2a9329615a boards/xtensa/esp32: Normalize all the configs.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-10 12:31:17 -06:00
Abdelatif Guettouche
cda3dd6816 baords/xtensa/esp32: Add WAPI and LEDs configs.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-10 12:31:17 -06:00
Abdelatif Guettouche
c95aba84f1 boards/xtensa/esp32: Move the LED definition to the private header and
remove userleds for boards that don't have that.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-10 12:31:17 -06:00
Abdelatif Guettouche
f7c5b467e1 arch/xtensa/src/esp32: Remove the EXPERIMENTAL config from the Wireless.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-10 12:31:17 -06:00
Abdelatif Guettouche
452b52a61e boards/xtensa/esp32/common: Fix functions' descriptions.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-10 12:31:17 -06:00
Abdelatif Guettouche
bb336498e4 boards/xtensa/esp32/esp32-wrover-kit: Add autoleds.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-10 12:31:17 -06:00
Abdelatif Guettouche
9d74362d75 boards: Add the new boards to the boards's Kconfig.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-10 12:31:17 -06:00
Abdelatif Guettouche
bb3b5cd1ee boards/xtensa/esp32: Add initial support for the ESP-WROVER-KIT.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-10 12:31:17 -06:00
Abdelatif Guettouche
cea53ed2ff boards/xtensa/esp32: Rename the common files as esp32_board_* to avoid
any naming collisions.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-10 12:31:17 -06:00
Abdelatif Guettouche
e097890f22 boards/xtensa/esp32: Initial support for the ESP32 Ethernet Kit.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-10 12:31:17 -06:00
Abdelatif Guettouche
a8f7959a21 boards/xtensa/esp32: Remove the experimental and debug configs.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-10 12:31:17 -06:00
Abdelatif Guettouche
3ba5018b37 boards/xtensa/esp32: A bit of re-organisation in the ESP32 boards.
Move the common files into the common directory.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-10 12:31:17 -06:00
Dong Heng
a59062f719 xtensa/esp32: Optimize IRAM usage based on esp-idf
Decrease about 87KB IRAM space cost from Wi-Fi related libs.
2020-12-04 14:33:30 -03:00
Dong Heng
3bb9a42c6b xtensa/esp32: Refactor ESP32 Wi-Fi driver 2020-12-04 09:39:11 -03:00
Alan C. Assis
3865960b89 esp32/esp32-core: Fix #ifdef warning and update MM_SECTIONS 2020-12-01 21:36:07 +01:00
Abdelatif Guettouche
81968ce562 boards: Allow boards to extend clean and distclean by a double colon
target instead of calling a variable.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-11-28 11:07:28 -06:00
chao.an
b1a042734f style/Document: remove unnecessary trailing whitespace
N/A

Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-28 12:20:30 +01:00
chao.an
32ba194372 style/code: remove unnecessary trailing whitespace
N/A

Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-28 12:20:30 +01:00
chenwen
2991418b2e xtensa/esp32: keep cpu clock while configured cpu clock is consistent with the default 2020-11-25 10:53:05 -03:00
YAMAMOTO Takashi
fc7d8944d7 boards/xtensa/esp32/esp32-core/src/esp32_bringup.c: Fix a syslog format error 2020-11-20 22:22:53 -08:00
Alan C. Assis
50e1a49c6e Fix the SPIRAM_BANKSWITCH that was defined incorrectly 2020-11-18 22:21:53 +01:00
Alan C. Assis
f09d103528 xtensa/esp32: Add high memory support to work with PSRAM 2020-11-18 22:21:53 +01:00
Dong Heng
bfb5214ef8 xtensa/esp32: Add SPI Flash hardware encryption I/O support 2020-11-13 08:37:59 +01:00
Sara Souza
8a1960fdf4 Documentation for Watchdog Timer Driver 2020-11-09 08:06:10 -08:00
Sara Souza
b9d44017cf xtensa/esp32: Watchdog support (MWDTs) 2020-11-08 13:05:24 -03:00
Alan C. Assis
816af60b77 xtensa/esp32: Include cache workaround to PSRAM 2020-11-07 12:08:02 +01:00
Abdelatif Guettouche
f052a9b1e6 baords/xtensa/esp32/esp32-core: Update all configs to add the new region
of memory.
2020-11-06 18:36:41 -03:00
Abdelatif Guettouche
2ac2ce55d2 arch/xtensa/src/esp32/esp32_allocateheap.c: Fix the memory regions with
regards to the data used by the ROM.
Static alloaction sections should end at the begining of the ROM data.
The rest of memory (End of ROM data --> End of DRAM) is added to the
heap.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-11-06 18:36:41 -03:00
Dong Heng
b54f0edff4 xtensa/esp32: Add Partition and OTA device 2020-11-03 21:54:07 +01:00
chao.an
b88561299b make/expression: improving up asm/C/C++ compile times
In the current compilation environment, the recursive assignment(=) for compile
flags will be delayed until every file is actually need to be compile.

For example:
--------------------------------------------------------------------------------
arch/arm/src/Makefile:

INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)common}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)$(ARCH_SUBDIR)}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)sched}

CPPFLAGS += $(INCLUDES) $(EXTRAFLAGS)
CFLAGS += $(INCLUDES) $(EXTRAFLAGS)
CXXFLAGS += $(INCLUDES) $(EXTRAFLAGS)
AFLAGS += $(INCLUDES) $(EXTRAFLAGS)
--------------------------------------------------------------------------------

All compilation options will be included recursively,
which will be delayed until the compilation options are actually used:

tools/Config.mk:

--------------------------------------------------------------------------------
define COMPILE
  @echo "CC: $1"
  $(Q) $(CC) -c $(CFLAGS) $($(strip $1)_CFLAGS) $1 -o $2
endef
--------------------------------------------------------------------------------

All compile flags to be reexecuted $(INCDIR) as long as one file needs to be compiled,
but in fact, the compilation options have not changed in the current directory.

So the we recommand to change the syntax of assignment
From
    Recursive (=)
To
    Simple    (:=)

In this way, we can ensure that all compilation options are expanded only once and reducing repeated works.

Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-02 07:53:53 -08:00
Brennan Ashton
162da1169e CI: Store artifacts durring build
Add new option -A is added to tools/testbuild.sh that will take the
created build executable and store it in a folder for the config
that generated it under $ARTIFACTDIR which can be set via an
environment variable or defaulted to $(TOPDIR)/buildartifacts

This is also helpful for local testing because you can now run
tools/testbuild.sh -A sim.dat and have all of the simulation
targets generated without having to rebuild along the way.

In the GitHub Actions workflow the artifacs are uploaded
two two bundles one for macOS and one for Linux

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
2020-10-28 11:32:21 -07:00
Sara Souza
ddc0d30063 xtensa/esp32: Added Userled support 2020-10-27 15:38:03 -03:00
YAMAMOTO Takashi
d8bee6769a esp32_flash.ld: Avoid having too many sections
Fixes an issue I saw when trying libcxx.

esptool.py has a limit of 16 sections.

It complains like:

    A fatal error occurred: Invalid segment count 23 (max 16).
    Usually this indicates a linker script problem.
2020-10-25 19:42:21 -07:00
Abdelatif Guettouche
9b98f20969 arch/xtensa: Fix the naming of the internal heap functions. They should
be prefixed by xtensa_ instead of up_.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-10-25 20:20:01 -03:00
Abdelatif Guettouche
c91db9eb40 baords/xtensa/esp32/esp32-core: Refresh all the defconfigs
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-10-25 20:20:01 -03:00
Abdelatif Guettouche
f0ae1dd54a arch/xtensa/src/esp32: Fix PR #1958 nxstyle issues.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-10-25 20:20:01 -03:00
Abdelatif Guettouche
430e2d766d boards/xtensa/esp32/esp32-core/configs: When there is no PSRAM, only one
memory region is available.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-10-25 20:20:01 -03:00
Abdelatif Guettouche
1b12d20225 arch/xtensa/src/esp32/esp32_spiflash.c&esp32_spi.c: Allocate a buffer from DRAM
when the given buffer is from PSRAM.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-10-25 20:20:01 -03:00
Abdelatif Guettouche
7ac5f7a35b arch/xtensa/src/esp32: Add a PROCFS entry for the internal memory
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-10-25 20:20:01 -03:00
chenwen
67c0af650f xtensa/esp32: Add power management of deep-sleep 2020-10-17 19:38:14 -03:00
Alan C. Assis
fdc44dc6fc Add PSRAM board config test and update README 2020-10-17 20:02:43 +01:00
Dong Heng
a0b84ae53e xtensa/esp32: Add ESP32 WiFi adapter and driver 2020-10-17 22:46:27 +09:00
Sara Souza
0faf861256 xtensa/esp32: Added Timer Support 2020-10-07 14:12:22 -03:00
Abdelatif Guettouche
caa945cb24 arch/xtensa/src/esp32: Add a way to retrieve reset cause.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-10-07 11:51:47 -03:00
Abdelatif Guettouche
c20c8c6dd5 arch/xtensa/esp32: Implement system reset.
Both CPUs are soft-reset with a call to board_reset.  This is actually a
Core Reset, so both cores and all registers are reset.  The only
exception is RTC.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-10-07 11:51:47 -03:00