Xiang Xiao
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2f24d2c265
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arch/ceva: Replace OUTDIR with TOPDIR
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-02-21 09:25:26 +01:00 |
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Xiang Xiao
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163fe4ff0b
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boards: Replace CONFIG_CYGWIN_WINTOOL with CONVERT_PATH
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-02-20 21:15:36 +01:00 |
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Xiang Xiao
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69a6072946
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arch/ceva: Replace adj_stack_ptr with stack_base_ptr
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-02-17 11:06:09 +09:00 |
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Xiang Xiao
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814cab1cd1
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arch/ceva: Mark the allocated stack with TCB_FLAG_FREE_STACK
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-02-17 11:06:09 +09:00 |
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Xiang Xiao
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f8df491d5d
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arch/ceva: Update tls handle to the latest mainline
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-02-17 11:06:09 +09:00 |
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Xiang Xiao
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4bc5b246ac
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arch/ceva: Remove B2C and C2B
since TL420 doesn't support anymore, we
can safely remove the special hack for it
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-02-17 11:06:09 +09:00 |
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Xiang Xiao
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17a7d612df
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arch: Replace nx_vsyslog with vsyslog
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-02-14 09:41:45 -03:00 |
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Xiang Xiao
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77792a1598
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sched: Define CONFIG_SMP_NCPUS to 1 in no SMP case
to simplify the SMP related code logic
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-01-20 23:21:21 +08:00 |
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Petro Karashchenko
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8d3bf05fd2
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include: fix double include pre-processor guards
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
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2022-01-16 11:11:14 -03:00 |
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ligd
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ee916bdb91
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CEVA: add ceva platform xc5 xm6 support
Signed-off-by: ligd <liguiding1@xiaomi.com>
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2022-01-07 09:31:59 -03:00 |
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