Commit Graph

109 Commits

Author SHA1 Message Date
Xiang Xiao
44bd3212d4 arch: Remove SYS_RESERVED from Kconfg
let's arch define the correct value instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
Xiang Xiao
087b9e5ff3 arch: Move the content from svcall.h to syscall.h
and remove svcall.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
Huang Qi
e8552156b6 arch/risc-v: Remove unneeded ISA specifc interface
They are not really defined and used in any where:
uint32_t up_getmisa(void);
uint32_t up_getarchid(void);
uint32_t up_getimpid(void);
uint32_t up_getvendorid(void);
uint32_t up_gethartid(void);

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-25 20:36:16 +08:00
Huang Qi
8b66280b4f arch/risc-v: Update outdated comments
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-25 20:36:16 +08:00
Ville Juven
81188d9c94 Extend the RISC-V PMP functionality
- Add test for mode support, which is architecture dependent
- Add tests for address alignment and region size
- Add option to query for access rights
 - The function goes through every PMP entry and tests if an address
   range from [base, base+size] has been configured for desired
   access rights.
 - If several PMP entries match the range and access rights, the
   information is combined
 - End result is either no access, a partial match was found, or a full
   match was found. Details about the partial match are not provided.

The intent for testing access rights and not just blindly applying them
is a case where they are already set in e.g. a bootloader. In this
case, nothing should be done, unless the configuration does not match,
in which case the software must not continue further.
2022-01-25 20:22:34 +08:00
Huang Qi
b803919b9d arch/risc-v: Merge mcause.h into irq.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-22 14:57:05 +08:00
Huang Qi
d846bb0235 arch/risc-v: Remove dupped irq code from mpfs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
6dc4dd207f arch/risc-v: Remove dupped irq code from rv32m1
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
089dc2e090 arch/risc-v: Remove dupped irq code from litex
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
d1edd887d5 arch/risc-v: Remove dupped irq code from c906
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
bd57229f3c arch/risc-v: Remove dupped irq code from bl602
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
8532feda78 arch/risc-v: Remove dupped irq code from fe310
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
e81439a367 arch/risc-v: Remove dupped irq code from k210
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
7738bb98fc arch/risc-v: Remove dupped irq code from qemu-rv
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
f43d677c2e arch/risc-v: Unify common irq code to arch/irq.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
5792d851e5 arch/risc-v/qemu-rv: Support both rv32/rv64 core
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-15 11:42:01 +08:00
Huang Qi
10bb48b9b4 arch/risc-v: Merge rv32im and rv64gc into common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-11 23:24:33 +08:00
Huang Qi
3a0e86c99b arch/risc-v: Replace __LP64__ with CONFIG_ARCH_RV64
It can provide better auto complete experience for modern code editor,
since they use clang/gcc based parser to analyze code but lacks some
target dependent info such as __LP64__ for riscv64.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-04 23:22:43 +08:00
Huang Qi
a6662c2887 arch/risc-v: Refine arch.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-04 14:46:24 +08:00
Huang Qi
2de22980e5 arch/risc-v: Refine syscall interface
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-30 11:47:42 +08:00
Huang Qi
d71cfc178a arch/risc-v: Remove unneeded kconfigs
CONFIG_RV32IM_HW_MULDIV can be safely removed since this behavior is
controlled by M extension.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 05:02:42 -06:00
Huang Qi
c2e8c92b25 arch/risc-v: Refine Toolchain.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 00:30:10 -06:00
Huang Qi
8ce3337e85 arch/risc-v: Implement TLS support
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-12 10:19:00 -06:00
Xiang Xiao
6357523892 arch: Add _wchar_t typedef like other basic types
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-09 16:57:23 +09:00
Huang Qi
63ab2f4308 arch/risc-v: Introduce basic support for qemu rv32
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-07 23:28:33 -06:00
Xiang Xiao
a0990ee416 arch: Remove the duplicated up_tls_info implementation
Define up_tls_info in arch/arch.h directly if the general one isn't suitable

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-05 20:59:53 -06:00
Alin Jerpelea
15a37c5a5a arch: Omni Hoverboards: update licenses to Apache
Gregory Nutt has submitted the SGA
Omni Hoverboards has submitted the SGA
David Sidrane has submitted the ICLA
Mateusz Szafoni has submitted the ICLA
Sebastien Lorquet has submitted the ICLA
Paul Alexander Patience has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-09-28 04:37:38 -07:00
Gustavo Henrique Nihei
06f4ee850a arch/risc-v: Remove FAR qualifier for RISC-V-specific files
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-22 08:16:01 -03:00
xiewenxiang
8b96edc3a5 riscv/esp32c3: Add esp32c3 BLE driver 2021-06-28 23:14:30 -05:00
Liu Han
04c805207a risc-v/esp32c3: Support ESP32-C3 efuse 2021-06-16 09:35:09 -03:00
Dong Heng
60fb1adaca riscv: Add inline IRQ process functions
Remove functions from RISC-V chips.
2021-06-15 23:25:16 -05:00
Xiang Xiao
6576306bca arch: Rename xxx_getsp to up_getsp
All modern desgin support stack pointer and it's also an
important information, so let's standardize this interface.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-06-09 10:20:02 -07:00
unixjet
68f19a6290 risc-v/rv32m1: Basic port to rv32m1 ri5cy 2021-06-05 17:25:57 -03:00
Janne Rosberg
d6205642ab add support for PolarFire SoC and icicle board
Co-authored-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-05-24 22:55:44 -05:00
Gustavo Henrique Nihei
90a4e8d718 risc-v/esp32c3: Fix DMA channels' interrupt IDs 2021-05-07 16:46:41 -03:00
Gustavo Henrique Nihei
66a15a6f83 risc-v/esp32c3: Fix wrong references to ESP32 2021-04-28 15:41:30 +01:00
Alin Jerpelea
231b8518b7 NuttX: Ken Pettit: update licenses to Apache
Ken Pettit has submitted the ICLA and we can migrate the licenses
 to Apache.

Sebastien Lorquet has submitted the ICLA and we can migrate the licenses
 to Apache.

Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-04-10 06:42:19 -05:00
hotislandn
b4b175cb7f arch:rv64:add memory clobber to inline asm for syscall.
Signed-off-by: hotislandn <hotislandn@hotmail.com>
2021-04-03 00:54:23 -05:00
Alin Jerpelea
5d633d7e0b arch: risc-V: Author Gregory Nutt: update licenses to Apache
Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-31 08:48:51 -07:00
hotislandn
6aa86b469c arch:rv64:c906:add PMP, change mem map for protect build.
Signed-off-by: hotislandn <hotislandn@hotmail.com>
2021-03-28 09:02:48 -05:00
Virus.V
7c80826c21 risc-v/bl602: Add wifi and ble support
tcpip ok

update wifi demo configuration

fix tcpip input cause misalign fault

change some api definetions in nuttx

fix wifi manager strlen copy without suffix null character

fix 602 network buf allocation issue

wifi scan works

[ble] Add controller code

[BLE] Add nuttx adapt code for blecontroller .

[BLE] modified include file path, to fix cflag is too long.

[ble]Test ble peripheral pass, save code.

[ble] Organize the code

[BLE] Add blecontroller config for nuttx

[BLE] Add config for ble example

fix tcp lost packet when rx

support wpa3.

Copy default config from wifi default config. Create ble for local test and ble tester for autopts.

Add config for local test.

Add pts teset config for host test

Add config for mesh test

Create task to init blecontroller

Delete blecontroller rx thread.

using idle task to receive hci command from host

Set ble device name to /dev/ble, and fix code.

1.fix a ke schedule risk 2. CFG_HOST is enabled only in the case that CONFIG_BLE_HOST_DISABLE is not enabled, by lanlan

rm _sp_main stack.

change h/l workq_stack_size 6K

change l workq_stack_size 3K.

[ble] delete file_detach

color idle stack.

clear bl602 netdev code

SCAN is sorted according to RSSI

enlarge nsh command line buffer

fixup stack overflow check checkfail when startup

arch/risc-v/BL602:fix reboot cause crash

reboot default use romapi.

riscv/bl602:netdev support defered input, remove wifi_tx function

risc-v/bl602:fix sem_timedwait usage error in bl_cmds

risc-v/bl602:fix memory access out of bounds when copy ssid

remove ble and wifi source, download when build

add bl602 blob gitignore

risc-v/bl602:remove ble-pts defconfig

Fix some typos in NuttX style naming

Fix the replacement of tab to space

fix wlan interface down still receive packet

fix wapi crash, rx when ifdown,and ble_hci_rx_do

change system reset to rom dirver

change ble hci interval to 50ms

NuttX support wifi enable/disable log via KConfig

support country code configuration in Kconfig

fix ap tx not work
2021-03-25 01:38:45 -07:00
Abdelatif Guettouche
51283bd99a arch/risc-v/syscall.h: Fix syscall function names in comments.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-20 13:02:54 -03:00
Abdelatif Guettouche
fb0fd36a5c arch/risc-v: Internal functions should be prefixed by "riscv_" instead
of "up_"

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-20 13:02:54 -03:00
Dong Heng
458caf2732 riscv/esp32c3: Add ESP32-C3 WLAN netcard driver 2021-03-16 10:42:32 -03:00
Masayuki Ishikawa
bb255d075c arch: risc-v: Author Masayuki Ishikawa: Update license to Apache
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-03-12 16:15:44 +08:00
Gustavo Henrique Nihei
0f508c1a5f risc-v/esp32c3: Fix erroneous index for I2C IRQ 2021-03-11 19:32:03 -03:00
Xiang Xiao
c047c1412f Remove all gap8(risc-v) arch and board source code
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-03-11 10:51:11 -08:00
Xiang Xiao
c54d617f2c Remove nr5m100(risc-v) arch and board source code
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-03-11 10:51:11 -08:00
hotislandn
d898bc445c arch:rv64:c906:enable DP FPU support.
Signed-off-by: hotislandn <hotislandn@hotmail.com>
2021-03-11 10:34:47 +08:00
hotislandn
5e50938726 arch:riscv64:basic porting for C906.
Signed-off-by: hotislandn <hotislandn@hotmail.com>
2021-03-10 19:23:24 +08:00