Juha Niskanen
4487b352c0
arch/arm/src/stm32l4: fix baud rate setting for LPUART
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Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2021-09-14 08:57:25 -07:00
Harri Luhtala
7e3c813346
arch/arm/src/stm32l4: LPUART1 support
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Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>
2021-09-14 08:57:25 -07:00
Abdelatif Guettouche
198c30eaa6
stm32*7/stm32_serial.c: Don't fake an interrupt when interrupts are not
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suppressed.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-14 22:50:43 +08:00
chao.an
ba9b829372
arch/arm: correct the function name from arm_getsp() to up_getsp()
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-09-14 22:48:47 +08:00
Cis van Mierlo
91c945a2e8
s32k1xx: added way to get the reset cause in proc fs
2021-09-14 08:35:41 +02:00
Alin Jerpelea
bb54ed4227
author: OffCode Ltd : update licenses to Apache
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OffCode Ltd has submitted the SGA
as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-09-13 22:43:36 +08:00
Xiang Xiao
850367d5bb
arch/arm: Add ARCH_CORTEXM55 Kconfig for cortex-m55
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-09-12 09:09:42 -03:00
Abdelatif Guettouche
31aa616bf2
stm32_serial.c: Don't fake a TX interrupt when interrupts are not
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suppressed.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-10 15:15:44 -07:00
David Sidrane
41e1696b27
stm32f4:USB otgdev Ensure proper EP state
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Repeated automated sercon, serdis on VBUS proved to fail
for CDCACM DATA IN (device Serial TX). The root cause was
that the EP was left active after disconnect. This resulted
in the first serial write falling to kick-off the EP IN request.
That should restart the EP ISR.
2021-09-09 14:27:41 -04:00
David Sidrane
e488f0047d
stm32h7:USB otgdev Ensure proper EP state
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Repeated automated sercon, serdis on VBUS proved to fail
for CDCACM DATA IN (device Serial TX). The root cause was
that the EP was left active after disconnect. This resulted
in the first serial write falling to kick-off the EP IN request.
That should restart the EP ISR.
2021-09-09 14:27:41 -04:00
David Sidrane
21f049b43a
stm32f7:USB otgdev Ensure proper EP state
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Repeated automated sercon, serdis on VBUS proved to fail
for CDCACM DATA IN (device Serial TX). The root cause was
that the EP was left active after disconnect. This resulted
in the first serial write falling to kick-off the EP IN request.
That should restart the EP ISR.
2021-09-09 14:27:41 -04:00
Harri Luhtala
d4e59b7e8d
arch/arm/src/stm32l4: add control for Vddio2 independent I/Os supply valid
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Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>
2021-09-09 08:26:08 -03:00
YAMAMOTO Takashi
58bdcbab9b
Revert "Make: use gcc as LD"
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This reverts commit 45672c269d
.
Because:
* It's very confusing to have cc as LD.
* I don't see what "-nostartfiles -nodefaultlibs" in LDFLAGS are
supposed to do when we use LD directly. It would be simpler to
remove them from our LDFLAGS.
2021-09-08 09:40:48 +08:00
Jari van Ewijk
5f63fa391f
Fix error in s32k118_pinmux.h
2021-09-07 17:34:19 -07:00
YAMAMOTO Takashi
5ad1cba338
Revert "arch: Replace ar and nm with gcc-ar and gcc-nm"
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This reverts commit b05737d78f
.
Because it broke clang-based builds.
2021-09-07 10:54:15 +08:00
Fotis Panagiotopoulos
eb48a0dbe0
Fix in STM32_UART8 Kconfig.
2021-09-07 10:52:44 +08:00
Jukka Laitinen
1b75b5d5aa
Fix compilation of arm protected build
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Correct typos in include/nuttx/arch.h and suppress
"'noreturn' function does return" warning coming from arm_pthread_exit.c
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-09-07 00:31:47 +08:00
Juha Niskanen
b70ae9ae82
arch/arm/src/stm32l4/stm32l4_flash.c: fix FLASH_CONFIG_I to use dual-bank access
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This is currently only used on STM32L4+ devices. Page erase in
flash_erase() function supports only dual-bank mode so it makes little
sense to configure this for unsupported single-bank mode.
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2021-09-04 14:31:16 +08:00
Juha Niskanen
508215581f
arch/arm/src/stm32l4: fix STM32L4+ option bytes memory address
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Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2021-09-03 09:55:54 -03:00
Alin Jerpelea
a20d4ac4ec
author: Aleksandr Vyhovanec: update licenses to Apache
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Aleksandr Vyhovanec has submitted the ICLA
as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-09-03 17:38:33 +08:00
Xiang Xiao
b05737d78f
arch: Replace ar and nm with gcc-ar and gcc-nm
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to make enable LTO easily
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-09-02 10:02:14 -03:00
Michal Lenc
1ec0258407
arch/arm/src/imxrt/imxrt_flexcan.c: use SW control to check free MBs
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CAN_ESR2 register was having problems of havng the correct values when
the bus was busy (with 3 and more nods). The register bit fields were
incorrectly indicating that there is no free MB and would not updated
itself from this state which was causing the applications to freeze on
write. This change relies only on a software control which should avoid
the problems described above.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-08-31 14:47:41 -03:00
Oleg
e95f23ef8b
arch/arm/stm32f7/stm32_irq: Fix format strings
2021-08-31 16:56:55 +08:00
Xiang Xiao
b0c782255c
libxx: Change CXX_LIBSUPCXX to LIBSUPCXX
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align with other Kconfig(e.g. LIBCXXABI, LIBCXX, UCLIBCXX)
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-28 17:14:48 -03:00
Xiang Xiao
f0001574ed
arch/armv8-m: Update per the latest architecture reference manual
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https://developer.arm.com/documentation/ddi0553/latest
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-27 11:39:27 +02:00
chao.an
bcce3314e5
arch/arm/cortex-m: add up_backtrace support
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add up_backtrace support based on push/branch instruction
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-26 18:31:51 +08:00
chao.an
d5d6297ca1
arch/arm/assert: enhance the assert dump
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show the all tasks info including backtrace and registers
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-26 13:31:08 +08:00
chao.an
f14bd44001
arch/armv7: add up_backtrace support based on frame pointer
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This feature depends on frame pointer, "-fno-omit-frame-pointer" is mandatory
This feature can not be used in THUMB2 mode if you are using GCC toolchain,
More details please refer:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92172
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-26 13:30:08 +08:00
ligd
f1aec38ffa
arm: add ARM_HAVE_NEON to Kconfig
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Change-Id: I112037aa15a6fae76cf4b7c2df10a42899c38a61
Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-08-26 13:25:43 +08:00
Abdelatif Guettouche
5ff703d5d0
arch/*_testset: Fix few typos.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-25 00:20:20 +08:00
Alin Jerpelea
07d528fd8d
license: Ken Pettit: update licenses to Apache
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Ken Pettit is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-08-23 11:41:41 +08:00
chao.an
6cfb132232
arch/cortex-m: replace arm_switchcontext to c-style
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-22 14:44:01 +08:00
Xiang Xiao
af72376773
fs: Remove magic field from partition_info_s
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since it is wrong and impossible to return file
system magic number from the block or mtd layer.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-20 09:19:52 -03:00
Xiang Xiao
4b41579ccf
arch/armv8-m: Add SAU support
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-20 10:22:43 +09:00
raiden00pl
78962165d8
arch/stm32: add 3-phase Hall effect sensor lower half
2021-08-19 08:19:38 -07:00
chao.an
0a8d951837
arch/arm: correct the frame pointer register declare
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In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code.
In AArch64, the frame pointer is stored in register X29.
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-19 01:26:07 -07:00
raiden00pl
532ec126e9
stm32/stm32_serial.c fix compile error when CONFIG_STM32_SERIALBRK_BSDCOMPAT=y.
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Fix for https://github.com/apache/incubator-nuttx/issues/4353
2021-08-18 04:43:32 -07:00
Juha Niskanen
e02e1c25f6
arch/arm/src/stm32l4/Kconfig: add new STM32L4+ chip types
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Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Change-Id: I74050913643db23b4d03abaf516989ff3cdac142
2021-08-17 06:27:18 -07:00
Alin Jerpelea
351091ed75
author: Pierre-noel Bouteville: update licenses to Apache
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Gregory Nutt has submitted the SGA as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-08-16 07:11:32 -07:00
Xiang Xiao
71269811ca
mtd: Implement BIOC_PARTINFO for all drivers
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-16 10:08:26 -03:00
Xiang Xiao
f63d1cfbbb
arch/arm: Add NVIC_FPCCR_XXX macro to avoid the hard code value
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-15 10:50:52 +02:00
Xiang Xiao
fad0c3b38b
arch/arm: Add NVIC_CPACR_CP_XXX(n) macro to avoid the hard code value
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-14 11:41:59 -07:00
Xiang Xiao
33666832c5
arch/arm: Add NVIC_AIRCR_VECTKEY macro to avoid the hard code value
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-14 11:41:59 -07:00
Abdelatif Guettouche
5b350f3a0f
arch/*_reprioritizertr.c: Fix typos in comments.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-14 11:19:34 -07:00
Alexander Vasiljev
4229099944
arch/arm/stm32h7: dma and serial: add TRBUFF flag. It is obligatory for uart.
2021-08-12 08:07:18 -03:00
Xiang Xiao
6b6c11f0ad
mtd: Replace MTDIOC_XIPBASE with BIOC_XIPBASE
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-12 08:01:29 -03:00
Xiang Xiao
d1687418db
mtd: Remove the empty MTDIOC_XIPBASE implmentation
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-11 09:50:51 -03:00
Abdelatif Guettouche
054e284785
*_cpustart.c: Fix typos in function description.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-11 11:06:27 +09:00
Fotis Panagiotopoulos
5b7ff03f40
lpc17_40: Fixed I2C port sanity check.
2021-08-10 09:04:33 -07:00
raiden00pl
2b3106fb47
Qencoder implementations for imxrt, stm32f7, stm32h7, stm32l4 and tivia don't support QEIOC_SETPOSMAX
2021-08-10 11:19:05 -03:00